tcg-target.c@ 36143

Last change on this file since 36143 was 36140, checked in by vboxsync, 14 years ago
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1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24
25	#ifndef NDEBUG
26	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27	"%eax",
28	"%ecx",
29	"%edx",
30	"%ebx",
31	"%esp",
32	"%ebp",
33	"%esi",
34	"%edi",
35	};
36	#endif
37
38	static const int tcg_target_reg_alloc_order[] = {
39	TCG_REG_EAX,
40	TCG_REG_EDX,
41	TCG_REG_ECX,
42	TCG_REG_EBX,
43	TCG_REG_ESI,
44	TCG_REG_EDI,
45	TCG_REG_EBP,
46	};
47
48	static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
49	static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
50
51	static uint8_t *tb_ret_addr;
52
53	static void patch_reloc(uint8_t *code_ptr, int type,
54	tcg_target_long value, tcg_target_long addend)
55	{
56	value += addend;
57	switch(type) {
58	case R_386_32:
59	(uint32_t )code_ptr = value;
60	break;
61	case R_386_PC32:
62	(uint32_t )code_ptr = value - (long)code_ptr;
63	break;
64	default:
65	tcg_abort();
66	}
67	}
68
69	#ifdef VBOX
70	/* emits stack alignment checks for strict builds. */
71	DECLINLINE(void) tcg_gen_stack_alignment_check(TCGContext *s)
72	{
73	# if defined(RT_STRICT) && defined(RT_OS_DARWIN) /** @todo all OSes? */
74	tcg_out8(s, 0xf7); tcg_out8(s, 0xc4); /* test %esp, 1fh */
75	tcg_out32(s, TCG_TARGET_STACK_ALIGN - 1);
76	tcg_out8(s, 0x74); /* jz imm8 */
77	tcg_out8(s, 1); /* $+3 (over int3) */
78	tcg_out8(s, 0xcc); /* int3 */
79	# else
80	NOREF(s);
81	# endif
82	}
83	#endif /* VBOX */
84
85	/* maximum number of register used for input function arguments */
86	static inline int tcg_target_get_call_iarg_regs_count(int flags)
87	{
88	flags &= TCG_CALL_TYPE_MASK;
89	switch(flags) {
90	case TCG_CALL_TYPE_STD:
91	return 0;
92	case TCG_CALL_TYPE_REGPARM_1:
93	case TCG_CALL_TYPE_REGPARM_2:
94	case TCG_CALL_TYPE_REGPARM:
95	return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
96	default:
97	tcg_abort();
98	}
99	}
100
101	/* parse target specific constraints */
102	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
103	{
104	const char *ct_str;
105
106	ct_str = *pct_str;
107	switch(ct_str[0]) {
108	case 'a':
109	ct->ct \|= TCG_CT_REG;
110	tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
111	break;
112	case 'b':
113	ct->ct \|= TCG_CT_REG;
114	tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
115	break;
116	case 'c':
117	ct->ct \|= TCG_CT_REG;
118	tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
119	break;
120	case 'd':
121	ct->ct \|= TCG_CT_REG;
122	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
123	break;
124	case 'S':
125	ct->ct \|= TCG_CT_REG;
126	tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
127	break;
128	case 'D':
129	ct->ct \|= TCG_CT_REG;
130	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
131	break;
132	case 'q':
133	ct->ct \|= TCG_CT_REG;
134	tcg_regset_set32(ct->u.regs, 0, 0xf);
135	break;
136	case 'r':
137	ct->ct \|= TCG_CT_REG;
138	tcg_regset_set32(ct->u.regs, 0, 0xff);
139	break;
140
141	/* qemu_ld/st address constraint */
142	case 'L':
143	ct->ct \|= TCG_CT_REG;
144	tcg_regset_set32(ct->u.regs, 0, 0xff);
145	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
146	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
147	break;
148	default:
149	return -1;
150	}
151	ct_str++;
152	*pct_str = ct_str;
153	return 0;
154	}
155
156	/* test if a constant matches the constraint */
157	static inline int tcg_target_const_match(tcg_target_long val,
158	const TCGArgConstraint *arg_ct)
159	{
160	int ct;
161	ct = arg_ct->ct;
162	if (ct & TCG_CT_CONST)
163	return 1;
164	else
165	return 0;
166	}
167
168	#define ARITH_ADD 0
169	#define ARITH_OR 1
170	#define ARITH_ADC 2
171	#define ARITH_SBB 3
172	#define ARITH_AND 4
173	#define ARITH_SUB 5
174	#define ARITH_XOR 6
175	#define ARITH_CMP 7
176
177	#define SHIFT_SHL 4
178	#define SHIFT_SHR 5
179	#define SHIFT_SAR 7
180
181	#define JCC_JMP (-1)
182	#define JCC_JO 0x0
183	#define JCC_JNO 0x1
184	#define JCC_JB 0x2
185	#define JCC_JAE 0x3
186	#define JCC_JE 0x4
187	#define JCC_JNE 0x5
188	#define JCC_JBE 0x6
189	#define JCC_JA 0x7
190	#define JCC_JS 0x8
191	#define JCC_JNS 0x9
192	#define JCC_JP 0xa
193	#define JCC_JNP 0xb
194	#define JCC_JL 0xc
195	#define JCC_JGE 0xd
196	#define JCC_JLE 0xe
197	#define JCC_JG 0xf
198
199	#define P_EXT 0x100 /* 0x0f opcode prefix */
200
201	static const uint8_t tcg_cond_to_jcc[10] = {
202	[TCG_COND_EQ] = JCC_JE,
203	[TCG_COND_NE] = JCC_JNE,
204	[TCG_COND_LT] = JCC_JL,
205	[TCG_COND_GE] = JCC_JGE,
206	[TCG_COND_LE] = JCC_JLE,
207	[TCG_COND_GT] = JCC_JG,
208	[TCG_COND_LTU] = JCC_JB,
209	[TCG_COND_GEU] = JCC_JAE,
210	[TCG_COND_LEU] = JCC_JBE,
211	[TCG_COND_GTU] = JCC_JA,
212	};
213
214	static inline void tcg_out_opc(TCGContext *s, int opc)
215	{
216	if (opc & P_EXT)
217	tcg_out8(s, 0x0f);
218	tcg_out8(s, opc);
219	}
220
221	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
222	{
223	tcg_out_opc(s, opc);
224	tcg_out8(s, 0xc0 \| (r << 3) \| rm);
225	}
226
227	/* rm == -1 means no register index */
228	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
229	int32_t offset)
230	{
231	tcg_out_opc(s, opc);
232	if (rm == -1) {
233	tcg_out8(s, 0x05 \| (r << 3));
234	tcg_out32(s, offset);
235	} else if (offset == 0 && rm != TCG_REG_EBP) {
236	if (rm == TCG_REG_ESP) {
237	tcg_out8(s, 0x04 \| (r << 3));
238	tcg_out8(s, 0x24);
239	} else {
240	tcg_out8(s, 0x00 \| (r << 3) \| rm);
241	}
242	} else if ((int8_t)offset == offset) {
243	if (rm == TCG_REG_ESP) {
244	tcg_out8(s, 0x44 \| (r << 3));
245	tcg_out8(s, 0x24);
246	} else {
247	tcg_out8(s, 0x40 \| (r << 3) \| rm);
248	}
249	tcg_out8(s, offset);
250	} else {
251	if (rm == TCG_REG_ESP) {
252	tcg_out8(s, 0x84 \| (r << 3));
253	tcg_out8(s, 0x24);
254	} else {
255	tcg_out8(s, 0x80 \| (r << 3) \| rm);
256	}
257	tcg_out32(s, offset);
258	}
259	}
260
261	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
262	{
263	if (arg != ret)
264	tcg_out_modrm(s, 0x8b, ret, arg);
265	}
266
267	static inline void tcg_out_movi(TCGContext *s, TCGType type,
268	int ret, int32_t arg)
269	{
270	if (arg == 0) {
271	/* xor r0,r0 */
272	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret);
273	} else {
274	tcg_out8(s, 0xb8 + ret);
275	tcg_out32(s, arg);
276	}
277	}
278
279	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
280	int arg1, tcg_target_long arg2)
281	{
282	/* movl */
283	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
284	}
285
286	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
287	int arg1, tcg_target_long arg2)
288	{
289	/* movl */
290	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
291	}
292
293	static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
294	{
295	if (val == (int8_t)val) {
296	tcg_out_modrm(s, 0x83, c, r0);
297	tcg_out8(s, val);
298	} else {
299	tcg_out_modrm(s, 0x81, c, r0);
300	tcg_out32(s, val);
301	}
302	}
303
304	void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
305	{
306	if (val != 0)
307	tgen_arithi(s, ARITH_ADD, reg, val);
308	}
309
310	#ifdef VBOX
311	void tcg_out_subi(TCGContext *s, int reg, tcg_target_long val)
312	{
313	if (val != 0)
314	tgen_arithi(s, ARITH_SUB, reg, val);
315	}
316	#endif
317
318	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
319	{
320	int32_t val, val1;
321	TCGLabel *l = &s->labels[label_index];
322
323	if (l->has_value) {
324	val = l->u.value - (tcg_target_long)s->code_ptr;
325	val1 = val - 2;
326	if ((int8_t)val1 == val1) {
327	if (opc == -1)
328	tcg_out8(s, 0xeb);
329	else
330	tcg_out8(s, 0x70 + opc);
331	tcg_out8(s, val1);
332	} else {
333	if (opc == -1) {
334	tcg_out8(s, 0xe9);
335	tcg_out32(s, val - 5);
336	} else {
337	tcg_out8(s, 0x0f);
338	tcg_out8(s, 0x80 + opc);
339	tcg_out32(s, val - 6);
340	}
341	}
342	} else {
343	if (opc == -1) {
344	tcg_out8(s, 0xe9);
345	} else {
346	tcg_out8(s, 0x0f);
347	tcg_out8(s, 0x80 + opc);
348	}
349	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
350	s->code_ptr += 4;
351	}
352	}
353
354	static void tcg_out_brcond(TCGContext *s, int cond,
355	TCGArg arg1, TCGArg arg2, int const_arg2,
356	int label_index)
357	{
358	if (const_arg2) {
359	if (arg2 == 0) {
360	/* test r, r */
361	tcg_out_modrm(s, 0x85, arg1, arg1);
362	} else {
363	tgen_arithi(s, ARITH_CMP, arg1, arg2);
364	}
365	} else {
366	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3), arg2, arg1);
367	}
368	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
369	}
370
371	#ifdef VBOX
372
373	DECLINLINE(void) tcg_out_long_call(TCGContext s, void dst)
374	{
375	intptr_t disp;
376	# ifdef VBOX
377	tcg_gen_stack_alignment_check(s);
378	# endif
379	disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
380	tcg_out8(s, 0xe8); /* call disp32 */
381	tcg_out32(s, disp); /* disp32 */
382	}
383
384	DECLINLINE(void) tcg_out_long_jmp(TCGContext s, void dst)
385	{
386	intptr_t disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
387	tcg_out8(s, 0xe9); /* jmp disp32 */
388	tcg_out32(s, disp); /* disp32 */
389	}
390
391	#endif /* VBOX */
392
393	/* XXX: we implement it at the target level to avoid having to
394	handle cross basic blocks temporaries */
395	static void tcg_out_brcond2(TCGContext *s,
396	const TCGArg args, const int const_args)
397	{
398	int label_next;
399	label_next = gen_new_label();
400	switch(args[4]) {
401	case TCG_COND_EQ:
402	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
403	tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
404	break;
405	case TCG_COND_NE:
406	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
407	tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
408	break;
409	case TCG_COND_LT:
410	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
411	tcg_out_jxx(s, JCC_JNE, label_next);
412	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
413	break;
414	case TCG_COND_LE:
415	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
416	tcg_out_jxx(s, JCC_JNE, label_next);
417	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
418	break;
419	case TCG_COND_GT:
420	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
421	tcg_out_jxx(s, JCC_JNE, label_next);
422	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
423	break;
424	case TCG_COND_GE:
425	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
426	tcg_out_jxx(s, JCC_JNE, label_next);
427	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
428	break;
429	case TCG_COND_LTU:
430	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
431	tcg_out_jxx(s, JCC_JNE, label_next);
432	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
433	break;
434	case TCG_COND_LEU:
435	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
436	tcg_out_jxx(s, JCC_JNE, label_next);
437	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
438	break;
439	case TCG_COND_GTU:
440	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
441	tcg_out_jxx(s, JCC_JNE, label_next);
442	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
443	break;
444	case TCG_COND_GEU:
445	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
446	tcg_out_jxx(s, JCC_JNE, label_next);
447	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
448	break;
449	default:
450	tcg_abort();
451	}
452	tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
453	}
454
455	#if defined(CONFIG_SOFTMMU)
456
457	#include "../../softmmu_defs.h"
458
459	static void *qemu_ld_helpers[4] = {
460	__ldb_mmu,
461	__ldw_mmu,
462	__ldl_mmu,
463	__ldq_mmu,
464	};
465
466	static void *qemu_st_helpers[4] = {
467	__stb_mmu,
468	__stw_mmu,
469	__stl_mmu,
470	__stq_mmu,
471	};
472	#endif
473
474	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
475	static void *vbox_ld_helpers[] = {
476	__ldub_vbox_phys,
477	__lduw_vbox_phys,
478	__ldul_vbox_phys,
479	__ldq_vbox_phys,
480	__ldb_vbox_phys,
481	__ldw_vbox_phys,
482	__ldl_vbox_phys,
483	__ldq_vbox_phys,
484	};
485
486	static void *vbox_st_helpers[] = {
487	__stb_vbox_phys,
488	__stw_vbox_phys,
489	__stl_vbox_phys,
490	__stq_vbox_phys
491	};
492
493	static void tcg_out_vbox_phys_read(TCGContext *s, int index,
494	int addr_reg,
495	int data_reg, int data_reg2)
496	{
497	int useReg2 = ((index & 3) == 3);
498
499	/** @todo: should we make phys address accessors fastcalls - probably not a big deal */
500	/* out parameter (address), note that phys address is always 64-bit */
501	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
502
503	#if 0
504	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
505	tcg_out_push(s, addr_reg);
506	#else
507	/* mov addr_reg, %eax */
508	tcg_out_mov(s, TCG_REG_EAX, addr_reg);
509	#endif
510
511	tcg_out_long_call(s, vbox_ld_helpers[index]);
512
513	/* mov %eax, data_reg */
514	tcg_out_mov(s, data_reg, TCG_REG_EAX);
515
516	/* returned 64-bit value */
517	if (useReg2)
518	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
519	}
520
521	static void tcg_out_vbox_phys_write(TCGContext *s, int index,
522	int addr_reg,
523	int val_reg, int val_reg2) {
524	int useReg2 = ((index & 3) == 3);
525
526	#if 0
527	/* out parameter (value2) */
528	if (useReg2)
529	tcg_out_push(s, val_reg2);
530	/* out parameter (value) */
531	tcg_out_push(s, val_reg);
532	/* out parameter (address), note that phys address is always 64-bit */
533	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
534	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
535	tcg_out_push(s, addr_reg);
536	#else
537	Assert(val_reg != TCG_REG_EAX && (!useReg2 \|\| (val_reg2 != TCG_REG_EAX)));
538	/* mov addr_reg, %eax */
539	tcg_out_mov(s, TCG_REG_EAX, addr_reg);
540	Assert(!useReg2 \|\| (val_reg2 != TCG_REG_EDX));
541	/* mov val_reg, %edx */
542	tcg_out_mov(s, TCG_REG_EDX, val_reg);
543	if (useReg2)
544	tcg_out_mov(s, TCG_REG_ECX, val_reg2);
545
546	#endif
547	/* call it */
548	tcg_out_long_call(s, vbox_st_helpers[index]);
549
550	/* clean stack after us */
551	#if 0
552	tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
553	# endif
554	}
555
556	#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
557
558	/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
559	EAX. It will be useful once fixed registers globals are less
560	common. */
561	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
562	int opc)
563	{
564	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
565	#if defined(CONFIG_SOFTMMU)
566	uint8_t label1_ptr, label2_ptr;
567	#endif
568	#if TARGET_LONG_BITS == 64
569	#if defined(CONFIG_SOFTMMU)
570	uint8_t *label3_ptr;
571	#endif
572	int addr_reg2;
573	#endif
574
575	data_reg = *args++;
576	if (opc == 3)
577	data_reg2 = *args++;
578	else
579	data_reg2 = 0;
580	addr_reg = *args++;
581	#if TARGET_LONG_BITS == 64
582	addr_reg2 = *args++;
583	#endif
584	mem_index = *args;
585	s_bits = opc & 3;
586
587	r0 = TCG_REG_EAX;
588	r1 = TCG_REG_EDX;
589
590	#if defined(CONFIG_SOFTMMU)
591	tcg_out_mov(s, r1, addr_reg);
592
593	tcg_out_mov(s, r0, addr_reg);
594
595	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
596	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
597
598	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
599	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
600
601	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
602	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
603
604	#ifndef VBOX
605	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
606	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
607	tcg_out8(s, (5 << 3) \| r1);
608	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
609	#else
610	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
611	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
612	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
613	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
614	#endif
615
616	/* cmp 0(r1), r0 */
617	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
618
619	tcg_out_mov(s, r0, addr_reg);
620
621	#if TARGET_LONG_BITS == 32
622	/* je label1 */
623	tcg_out8(s, 0x70 + JCC_JE);
624	label1_ptr = s->code_ptr;
625	s->code_ptr++;
626	#else
627	/* jne label3 */
628	tcg_out8(s, 0x70 + JCC_JNE);
629	label3_ptr = s->code_ptr;
630	s->code_ptr++;
631
632	/* cmp 4(r1), addr_reg2 */
633	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
634
635	/* je label1 */
636	tcg_out8(s, 0x70 + JCC_JE);
637	label1_ptr = s->code_ptr;
638	s->code_ptr++;
639
640	/* label3: */
641	*label3_ptr = s->code_ptr - label3_ptr - 1;
642	#endif
643
644	/* XXX: move that code at the end of the TB */
645	#if TARGET_LONG_BITS == 32
646	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
647	#else
648	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
649	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
650	#endif
651	#ifdef VBOX
652	tcg_gen_stack_alignment_check(s);
653	#endif
654	tcg_out8(s, 0xe8);
655	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
656	(tcg_target_long)s->code_ptr - 4);
657
658	switch(opc) {
659	case 0 \| 4:
660	/* movsbl */
661	tcg_out_modrm(s, 0xbe \| P_EXT, data_reg, TCG_REG_EAX);
662	break;
663	case 1 \| 4:
664	/* movswl */
665	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, TCG_REG_EAX);
666	break;
667	case 0:
668	case 1:
669	case 2:
670	default:
671	tcg_out_mov(s, data_reg, TCG_REG_EAX);
672	break;
673	case 3:
674	if (data_reg == TCG_REG_EDX) {
675	tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
676	tcg_out_mov(s, data_reg2, TCG_REG_EAX);
677	} else {
678	tcg_out_mov(s, data_reg, TCG_REG_EAX);
679	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
680	}
681	break;
682	}
683
684	/* jmp label2 */
685	tcg_out8(s, 0xeb);
686	label2_ptr = s->code_ptr;
687	s->code_ptr++;
688
689	/* label1: */
690	*label1_ptr = s->code_ptr - label1_ptr - 1;
691
692	/* add x(r1), r0 */
693	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
694	offsetof(CPUTLBEntry, addr_read));
695	#else
696	r0 = addr_reg;
697	#endif
698
699	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
700	#ifdef TARGET_WORDS_BIGENDIAN
701	bswap = 1;
702	#else
703	bswap = 0;
704	#endif
705	switch(opc) {
706	case 0:
707	/* movzbl */
708	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
709	break;
710	case 0 \| 4:
711	/* movsbl */
712	tcg_out_modrm_offset(s, 0xbe \| P_EXT, data_reg, r0, 0);
713	break;
714	case 1:
715	/* movzwl */
716	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
717	if (bswap) {
718	/* rolw $8, data_reg */
719	tcg_out8(s, 0x66);
720	tcg_out_modrm(s, 0xc1, 0, data_reg);
721	tcg_out8(s, 8);
722	}
723	break;
724	case 1 \| 4:
725	/* movswl */
726	tcg_out_modrm_offset(s, 0xbf \| P_EXT, data_reg, r0, 0);
727	if (bswap) {
728	/* rolw $8, data_reg */
729	tcg_out8(s, 0x66);
730	tcg_out_modrm(s, 0xc1, 0, data_reg);
731	tcg_out8(s, 8);
732
733	/* movswl data_reg, data_reg */
734	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, data_reg);
735	}
736	break;
737	case 2:
738	/* movl (r0), data_reg */
739	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
740	if (bswap) {
741	/* bswap */
742	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
743	}
744	break;
745	case 3:
746	/* XXX: could be nicer */
747	if (r0 == data_reg) {
748	r1 = TCG_REG_EDX;
749	if (r1 == data_reg)
750	r1 = TCG_REG_EAX;
751	tcg_out_mov(s, r1, r0);
752	r0 = r1;
753	}
754	if (!bswap) {
755	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
756	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
757	} else {
758	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
759	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
760
761	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
762	/* bswap */
763	tcg_out_opc(s, (0xc8 + data_reg2) \| P_EXT);
764	}
765	break;
766	default:
767	tcg_abort();
768	}
769	#else /* VBOX */
770	tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
771	#endif
772
773
774	#if defined(CONFIG_SOFTMMU)
775	/* label2: */
776	*label2_ptr = s->code_ptr - label2_ptr - 1;
777	# ifdef VBOX
778	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
779	# endif
780	#endif
781	}
782
783
784	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
785	int opc)
786	{
787	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
788	#if defined(CONFIG_SOFTMMU)
789	uint8_t label1_ptr, label2_ptr;
790	#endif
791	#if TARGET_LONG_BITS == 64
792	#if defined(CONFIG_SOFTMMU)
793	uint8_t *label3_ptr;
794	#endif
795	int addr_reg2;
796	#endif
797	#ifdef VBOX
798	# ifdef RT_OS_DARWIN
799	int bias1 = 12, bias3 = 4;/** @todo TCG_TARGET_STACK_ALIGN. */
800	# else
801	int bias1 = 0, bias3 = 0;
802	# endif
803	NOREF(bias3);
804	#endif
805
806	data_reg = *args++;
807	if (opc == 3)
808	data_reg2 = *args++;
809	else
810	data_reg2 = 0;
811	addr_reg = *args++;
812	#if TARGET_LONG_BITS == 64
813	addr_reg2 = *args++;
814	#endif
815	mem_index = *args;
816
817	s_bits = opc;
818
819	r0 = TCG_REG_EAX;
820	r1 = TCG_REG_EDX;
821
822	#if defined(CONFIG_SOFTMMU)
823	tcg_out_mov(s, r1, addr_reg);
824
825	tcg_out_mov(s, r0, addr_reg);
826
827	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
828	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
829
830	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
831	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
832
833	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
834	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
835
836	#ifndef VBOX
837	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
838	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
839	tcg_out8(s, (5 << 3) \| r1);
840	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
841	#else
842	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
843	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
844	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
845	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
846	#endif
847
848	/* cmp 0(r1), r0 */
849	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
850
851	tcg_out_mov(s, r0, addr_reg);
852
853	#if TARGET_LONG_BITS == 32
854	/* je label1 */
855	tcg_out8(s, 0x70 + JCC_JE);
856	label1_ptr = s->code_ptr;
857	s->code_ptr++;
858	#else
859	/* jne label3 */
860	tcg_out8(s, 0x70 + JCC_JNE);
861	label3_ptr = s->code_ptr;
862	s->code_ptr++;
863
864	/* cmp 4(r1), addr_reg2 */
865	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
866
867	/* je label1 */
868	tcg_out8(s, 0x70 + JCC_JE);
869	label1_ptr = s->code_ptr;
870	s->code_ptr++;
871
872	/* label3: */
873	*label3_ptr = s->code_ptr - label3_ptr - 1;
874	#endif
875
876	/* XXX: move that code at the end of the TB */
877	#if TARGET_LONG_BITS == 32
878	if (opc == 3) {
879	tcg_out_mov(s, TCG_REG_EDX, data_reg);
880	tcg_out_mov(s, TCG_REG_ECX, data_reg2);
881	#ifdef VBOX
882	tcg_out_subi(s, TCG_REG_ESP, bias1);
883	#endif
884	tcg_out8(s, 0x6a); /* push Ib */
885	tcg_out8(s, mem_index);
886	# ifdef VBOX
887	tcg_gen_stack_alignment_check(s);
888	# endif
889	tcg_out8(s, 0xe8);
890	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
891	(tcg_target_long)s->code_ptr - 4);
892	#ifdef VBOX
893	tcg_out_addi(s, TCG_REG_ESP, 4+bias1);
894	#else
895	tcg_out_addi(s, TCG_REG_ESP, 4);
896	#endif
897	} else {
898	switch(opc) {
899	case 0:
900	/* movzbl */
901	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_EDX, data_reg);
902	break;
903	case 1:
904	/* movzwl */
905	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_EDX, data_reg);
906	break;
907	case 2:
908	tcg_out_mov(s, TCG_REG_EDX, data_reg);
909	break;
910	}
911	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
912	# ifdef VBOX
913	tcg_gen_stack_alignment_check(s);
914	# endif
915	tcg_out8(s, 0xe8);
916	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
917	(tcg_target_long)s->code_ptr - 4);
918	}
919	#else
920	if (opc == 3) {
921	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
922	# ifdef VBOX
923	tcg_out_subi(s, TCG_REG_ESP, bias3);
924	# endif
925	tcg_out8(s, 0x6a); /* push Ib */
926	tcg_out8(s, mem_index);
927	tcg_out_opc(s, 0x50 + data_reg2); /* push */
928	tcg_out_opc(s, 0x50 + data_reg); /* push */
929	# ifdef VBOX
930	tcg_gen_stack_alignment_check(s);
931	# endif
932	tcg_out8(s, 0xe8);
933	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
934	(tcg_target_long)s->code_ptr - 4);
935	#ifdef VBOX
936	tcg_out_addi(s, TCG_REG_ESP, 12+bias3);
937	#else
938	tcg_out_addi(s, TCG_REG_ESP, 12);
939	#endif
940	} else {
941	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
942	switch(opc) {
943	case 0:
944	/* movzbl */
945	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_ECX, data_reg);
946	break;
947	case 1:
948	/* movzwl */
949	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_ECX, data_reg);
950	break;
951	case 2:
952	tcg_out_mov(s, TCG_REG_ECX, data_reg);
953	break;
954	}
955	# ifdef VBOX
956	tcg_out_subi(s, TCG_REG_ESP, bias1);
957	# endif
958	tcg_out8(s, 0x6a); /* push Ib */
959	tcg_out8(s, mem_index);
960	# ifdef VBOX
961	tcg_gen_stack_alignment_check(s);
962	# endif
963
964	tcg_out8(s, 0xe8);
965	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
966	(tcg_target_long)s->code_ptr - 4);
967	# if defined(VBOX)
968	tcg_out_addi(s, TCG_REG_ESP, 4 + bias1);
969	# else
970	tcg_out_addi(s, TCG_REG_ESP, 4);
971	# endif
972	}
973	#endif
974
975	/* jmp label2 */
976	tcg_out8(s, 0xeb);
977	label2_ptr = s->code_ptr;
978	s->code_ptr++;
979
980	/* label1: */
981	*label1_ptr = s->code_ptr - label1_ptr - 1;
982
983	/* add x(r1), r0 */
984	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
985	offsetof(CPUTLBEntry, addr_write));
986	#else
987	r0 = addr_reg;
988	#endif
989
990	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
991	#ifdef TARGET_WORDS_BIGENDIAN
992	bswap = 1;
993	#else
994	bswap = 0;
995	#endif
996	switch(opc) {
997	case 0:
998	/* movb */
999	tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
1000	break;
1001	case 1:
1002	if (bswap) {
1003	tcg_out_mov(s, r1, data_reg);
1004	tcg_out8(s, 0x66); /* rolw $8, %ecx */
1005	tcg_out_modrm(s, 0xc1, 0, r1);
1006	tcg_out8(s, 8);
1007	data_reg = r1;
1008	}
1009	/* movw */
1010	tcg_out8(s, 0x66);
1011	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1012	break;
1013	case 2:
1014	if (bswap) {
1015	tcg_out_mov(s, r1, data_reg);
1016	/* bswap data_reg */
1017	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1018	data_reg = r1;
1019	}
1020	/* movl */
1021	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1022	break;
1023	case 3:
1024	if (bswap) {
1025	tcg_out_mov(s, r1, data_reg2);
1026	/* bswap data_reg */
1027	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1028	tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1029	tcg_out_mov(s, r1, data_reg);
1030	/* bswap data_reg */
1031	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1032	tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1033	} else {
1034	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1035	tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1036	}
1037	break;
1038	default:
1039	tcg_abort();
1040	}
1041	#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
1042	tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1043	#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
1044
1045	#if defined(CONFIG_SOFTMMU)
1046	/* label2: */
1047	*label2_ptr = s->code_ptr - label2_ptr - 1;
1048	# ifdef VBOX
1049	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
1050	# endif
1051	#endif
1052	}
1053
1054	static inline void tcg_out_op(TCGContext *s, int opc,
1055	const TCGArg args, const int const_args)
1056	{
1057	int c;
1058
1059	switch(opc) {
1060	case INDEX_op_exit_tb:
1061	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1062	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1063	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1064	break;
1065	case INDEX_op_goto_tb:
1066	if (s->tb_jmp_offset) {
1067	/* direct jump method */
1068	tcg_out8(s, 0xe9); /* jmp im */
1069	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1070	tcg_out32(s, 0);
1071	} else {
1072	/* indirect jump method */
1073	/* jmp Ev */
1074	tcg_out_modrm_offset(s, 0xff, 4, -1,
1075	(tcg_target_long)(s->tb_next + args[0]));
1076	}
1077	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1078	break;
1079	case INDEX_op_call:
1080	#ifdef VBOX
1081	tcg_gen_stack_alignment_check(s);
1082	#endif
1083	if (const_args[0]) {
1084	tcg_out8(s, 0xe8);
1085	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1086	} else {
1087	tcg_out_modrm(s, 0xff, 2, args[0]);
1088	}
1089	break;
1090	case INDEX_op_jmp:
1091	if (const_args[0]) {
1092	tcg_out8(s, 0xe9);
1093	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1094	} else {
1095	tcg_out_modrm(s, 0xff, 4, args[0]);
1096	}
1097	break;
1098	case INDEX_op_br:
1099	tcg_out_jxx(s, JCC_JMP, args[0]);
1100	break;
1101	case INDEX_op_movi_i32:
1102	tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1103	break;
1104	case INDEX_op_ld8u_i32:
1105	/* movzbl */
1106	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1107	break;
1108	case INDEX_op_ld8s_i32:
1109	/* movsbl */
1110	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1111	break;
1112	case INDEX_op_ld16u_i32:
1113	/* movzwl */
1114	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1115	break;
1116	case INDEX_op_ld16s_i32:
1117	/* movswl */
1118	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1119	break;
1120	case INDEX_op_ld_i32:
1121	/* movl */
1122	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1123	break;
1124	case INDEX_op_st8_i32:
1125	/* movb */
1126	tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1127	break;
1128	case INDEX_op_st16_i32:
1129	/* movw */
1130	tcg_out8(s, 0x66);
1131	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1132	break;
1133	case INDEX_op_st_i32:
1134	/* movl */
1135	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1136	break;
1137	case INDEX_op_sub_i32:
1138	c = ARITH_SUB;
1139	goto gen_arith;
1140	case INDEX_op_and_i32:
1141	c = ARITH_AND;
1142	goto gen_arith;
1143	case INDEX_op_or_i32:
1144	c = ARITH_OR;
1145	goto gen_arith;
1146	case INDEX_op_xor_i32:
1147	c = ARITH_XOR;
1148	goto gen_arith;
1149	case INDEX_op_add_i32:
1150	c = ARITH_ADD;
1151	gen_arith:
1152	if (const_args[2]) {
1153	tgen_arithi(s, c, args[0], args[2]);
1154	} else {
1155	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1156	}
1157	break;
1158	case INDEX_op_mul_i32:
1159	if (const_args[2]) {
1160	int32_t val;
1161	val = args[2];
1162	if (val == (int8_t)val) {
1163	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1164	tcg_out8(s, val);
1165	} else {
1166	tcg_out_modrm(s, 0x69, args[0], args[0]);
1167	tcg_out32(s, val);
1168	}
1169	} else {
1170	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1171	}
1172	break;
1173	case INDEX_op_mulu2_i32:
1174	tcg_out_modrm(s, 0xf7, 4, args[3]);
1175	break;
1176	case INDEX_op_div2_i32:
1177	tcg_out_modrm(s, 0xf7, 7, args[4]);
1178	break;
1179	case INDEX_op_divu2_i32:
1180	tcg_out_modrm(s, 0xf7, 6, args[4]);
1181	break;
1182	case INDEX_op_shl_i32:
1183	c = SHIFT_SHL;
1184	gen_shift32:
1185	if (const_args[2]) {
1186	if (args[2] == 1) {
1187	tcg_out_modrm(s, 0xd1, c, args[0]);
1188	} else {
1189	tcg_out_modrm(s, 0xc1, c, args[0]);
1190	tcg_out8(s, args[2]);
1191	}
1192	} else {
1193	tcg_out_modrm(s, 0xd3, c, args[0]);
1194	}
1195	break;
1196	case INDEX_op_shr_i32:
1197	c = SHIFT_SHR;
1198	goto gen_shift32;
1199	case INDEX_op_sar_i32:
1200	c = SHIFT_SAR;
1201	goto gen_shift32;
1202
1203	case INDEX_op_add2_i32:
1204	if (const_args[4])
1205	tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1206	else
1207	tcg_out_modrm(s, 0x01 \| (ARITH_ADD << 3), args[4], args[0]);
1208	if (const_args[5])
1209	tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1210	else
1211	tcg_out_modrm(s, 0x01 \| (ARITH_ADC << 3), args[5], args[1]);
1212	break;
1213	case INDEX_op_sub2_i32:
1214	if (const_args[4])
1215	tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1216	else
1217	tcg_out_modrm(s, 0x01 \| (ARITH_SUB << 3), args[4], args[0]);
1218	if (const_args[5])
1219	tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1220	else
1221	tcg_out_modrm(s, 0x01 \| (ARITH_SBB << 3), args[5], args[1]);
1222	break;
1223	case INDEX_op_brcond_i32:
1224	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1225	break;
1226	case INDEX_op_brcond2_i32:
1227	tcg_out_brcond2(s, args, const_args);
1228	break;
1229
1230	case INDEX_op_qemu_ld8u:
1231	tcg_out_qemu_ld(s, args, 0);
1232	break;
1233	case INDEX_op_qemu_ld8s:
1234	tcg_out_qemu_ld(s, args, 0 \| 4);
1235	break;
1236	case INDEX_op_qemu_ld16u:
1237	tcg_out_qemu_ld(s, args, 1);
1238	break;
1239	case INDEX_op_qemu_ld16s:
1240	tcg_out_qemu_ld(s, args, 1 \| 4);
1241	break;
1242	case INDEX_op_qemu_ld32u:
1243	tcg_out_qemu_ld(s, args, 2);
1244	break;
1245	case INDEX_op_qemu_ld64:
1246	tcg_out_qemu_ld(s, args, 3);
1247	break;
1248
1249	case INDEX_op_qemu_st8:
1250	tcg_out_qemu_st(s, args, 0);
1251	break;
1252	case INDEX_op_qemu_st16:
1253	tcg_out_qemu_st(s, args, 1);
1254	break;
1255	case INDEX_op_qemu_st32:
1256	tcg_out_qemu_st(s, args, 2);
1257	break;
1258	case INDEX_op_qemu_st64:
1259	tcg_out_qemu_st(s, args, 3);
1260	break;
1261
1262	default:
1263	tcg_abort();
1264	}
1265	}
1266
1267	static const TCGTargetOpDef x86_op_defs[] = {
1268	{ INDEX_op_exit_tb, {"", "" } },
1269	{ INDEX_op_goto_tb, {"", "" } },
1270	{ INDEX_op_call, { "ri", "", } },
1271	{ INDEX_op_jmp, { "ri", ""} },
1272	{ INDEX_op_br, {"", "" } },
1273	{ INDEX_op_mov_i32, { "r", "r" } },
1274	{ INDEX_op_movi_i32, { "r" } },
1275	{ INDEX_op_ld8u_i32, { "r", "r" } },
1276	{ INDEX_op_ld8s_i32, { "r", "r" } },
1277	{ INDEX_op_ld16u_i32, { "r", "r" } },
1278	{ INDEX_op_ld16s_i32, { "r", "r" } },
1279	{ INDEX_op_ld_i32, { "r", "r" } },
1280	{ INDEX_op_st8_i32, { "q", "r" } },
1281	{ INDEX_op_st16_i32, { "r", "r" } },
1282	{ INDEX_op_st_i32, { "r", "r" } },
1283
1284	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1285	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1286	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1287	{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1288	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1289	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1290	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1291	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1292	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1293
1294	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1295	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1296	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1297
1298	{ INDEX_op_brcond_i32, { "r", "ri" } },
1299
1300	{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1301	{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1302	{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1303
1304	#if TARGET_LONG_BITS == 32
1305	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1306	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1307	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1308	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1309	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1310	{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
1311
1312	{ INDEX_op_qemu_st8, { "cb", "L" } },
1313	{ INDEX_op_qemu_st16, { "L", "L" } },
1314	{ INDEX_op_qemu_st32, { "L", "L" } },
1315	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1316	#else
1317	{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1318	{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1319	{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1320	{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1321	{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1322	{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1323
1324	{ INDEX_op_qemu_st8, { "cb", "L", "L" } },
1325	{ INDEX_op_qemu_st16, { "L", "L", "L" } },
1326	{ INDEX_op_qemu_st32, { "L", "L", "L" } },
1327	{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1328	#endif
1329	#ifndef VBOX
1330	{ -1 },
1331	#else
1332	{ -1, {"", "", "", ""} },
1333	#endif
1334	};
1335
1336	static int tcg_target_callee_save_regs[] = {
1337	#ifndef VBOX
1338	/* TCG_REG_EBP, / / currently used for the global env, so no
1339	need to save */
1340	TCG_REG_EBX,
1341	TCG_REG_ESI,
1342	TCG_REG_EDI,
1343	#else
1344	TCG_REG_EBP,
1345	TCG_REG_EBX,
1346	/* TCG_REG_ESI, / / currently used for the global env, so no
1347	need to save */
1348	TCG_REG_EDI,
1349	#endif
1350	};
1351
1352	static inline void tcg_out_push(TCGContext *s, int reg)
1353	{
1354	tcg_out_opc(s, 0x50 + reg);
1355	}
1356
1357	static inline void tcg_out_pop(TCGContext *s, int reg)
1358	{
1359	tcg_out_opc(s, 0x58 + reg);
1360	}
1361
1362	/* Generate global QEMU prologue and epilogue code */
1363	void tcg_target_qemu_prologue(TCGContext *s)
1364	{
1365	int i, frame_size, push_size, stack_addend;
1366
1367	/* TB prologue */
1368	/* save all callee saved registers */
1369	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1370	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1371	}
1372	/* reserve some stack space */
1373	push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1374	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1375	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1376	~(TCG_TARGET_STACK_ALIGN - 1);
1377	stack_addend = frame_size - push_size;
1378	tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1379	# ifdef VBOX
1380	tcg_gen_stack_alignment_check(s);
1381	# endif
1382
1383	tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp %eax /
1384
1385	/* TB epilogue */
1386	tb_ret_addr = s->code_ptr;
1387	tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1388	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1389	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1390	}
1391	tcg_out8(s, 0xc3); /* ret */
1392	}
1393
1394	void tcg_target_init(TCGContext *s)
1395	{
1396	/* fail safe */
1397	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1398	tcg_abort();
1399
1400	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1401	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1402	(1 << TCG_REG_EAX) \|
1403	(1 << TCG_REG_EDX) \|
1404	(1 << TCG_REG_ECX));
1405
1406	tcg_regset_clear(s->reserved_regs);
1407	tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1408
1409	tcg_add_target_add_op_defs(x86_op_defs);
1410	}

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source: vbox/trunk/src/recompiler/tcg/i386/tcg-target.c@ 36143

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