| 1 | /*
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| 2 | * Tiny Code Generator for QEMU
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| 3 | *
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| 4 | * Copyright (c) 2008 Fabrice Bellard
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| 5 | *
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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| 7 | * of this software and associated documentation files (the "Software"), to deal
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| 8 | * in the Software without restriction, including without limitation the rights
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| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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| 10 | * copies of the Software, and to permit persons to whom the Software is
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| 11 | * furnished to do so, subject to the following conditions:
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| 12 | *
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| 13 | * The above copyright notice and this permission notice shall be included in
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| 14 | * all copies or substantial portions of the Software.
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| 15 | *
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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| 22 | * THE SOFTWARE.
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| 23 | */
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| 24 |
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| 25 | #ifdef CONFIG_DYNGEN_OP
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| 26 | #include "dyngen-opc.h"
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| 27 | #endif
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| 28 |
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| 29 | #ifndef DEF2
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| 30 | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0)
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| 31 | #endif
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| 32 |
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| 33 | /* predefined ops */
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| 34 | DEF2(end, 0, 0, 0, 0) /* must be kept first */
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| 35 | DEF2(nop, 0, 0, 0, 0)
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| 36 | DEF2(nop1, 0, 0, 1, 0)
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| 37 | DEF2(nop2, 0, 0, 2, 0)
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| 38 | DEF2(nop3, 0, 0, 3, 0)
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| 39 | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */
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| 40 |
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| 41 | DEF2(discard, 1, 0, 0, 0)
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| 42 |
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| 43 | DEF2(set_label, 0, 0, 1, 0)
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| 44 | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
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| 45 | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 46 | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 47 |
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| 48 | DEF2(mov_i32, 1, 1, 0, 0)
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| 49 | DEF2(movi_i32, 1, 0, 1, 0)
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| 50 | /* load/store */
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| 51 | DEF2(ld8u_i32, 1, 1, 1, 0)
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| 52 | DEF2(ld8s_i32, 1, 1, 1, 0)
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| 53 | DEF2(ld16u_i32, 1, 1, 1, 0)
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| 54 | DEF2(ld16s_i32, 1, 1, 1, 0)
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| 55 | DEF2(ld_i32, 1, 1, 1, 0)
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| 56 | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 57 | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 58 | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 59 | /* arith */
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| 60 | DEF2(add_i32, 1, 2, 0, 0)
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| 61 | DEF2(sub_i32, 1, 2, 0, 0)
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| 62 | DEF2(mul_i32, 1, 2, 0, 0)
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| 63 | #ifdef TCG_TARGET_HAS_div_i32
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| 64 | DEF2(div_i32, 1, 2, 0, 0)
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| 65 | DEF2(divu_i32, 1, 2, 0, 0)
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| 66 | DEF2(rem_i32, 1, 2, 0, 0)
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| 67 | DEF2(remu_i32, 1, 2, 0, 0)
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| 68 | #else
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| 69 | DEF2(div2_i32, 2, 3, 0, 0)
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| 70 | DEF2(divu2_i32, 2, 3, 0, 0)
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| 71 | #endif
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| 72 | DEF2(and_i32, 1, 2, 0, 0)
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| 73 | DEF2(or_i32, 1, 2, 0, 0)
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| 74 | DEF2(xor_i32, 1, 2, 0, 0)
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| 75 | /* shifts */
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| 76 | DEF2(shl_i32, 1, 2, 0, 0)
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| 77 | DEF2(shr_i32, 1, 2, 0, 0)
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| 78 | DEF2(sar_i32, 1, 2, 0, 0)
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| 79 |
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| 80 | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 81 | #if TCG_TARGET_REG_BITS == 32
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| 82 | DEF2(add2_i32, 2, 4, 0, 0)
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| 83 | DEF2(sub2_i32, 2, 4, 0, 0)
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| 84 | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 85 | DEF2(mulu2_i32, 2, 2, 0, 0)
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| 86 | #endif
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| 87 | #ifdef TCG_TARGET_HAS_ext8s_i32
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| 88 | DEF2(ext8s_i32, 1, 1, 0, 0)
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| 89 | #endif
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| 90 | #ifdef TCG_TARGET_HAS_ext16s_i32
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| 91 | DEF2(ext16s_i32, 1, 1, 0, 0)
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| 92 | #endif
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| 93 | #ifdef TCG_TARGET_HAS_bswap_i32
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| 94 | DEF2(bswap_i32, 1, 1, 0, 0)
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| 95 | #endif
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| 96 |
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| 97 | #if TCG_TARGET_REG_BITS == 64
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| 98 | DEF2(mov_i64, 1, 1, 0, 0)
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| 99 | DEF2(movi_i64, 1, 0, 1, 0)
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| 100 | /* load/store */
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| 101 | DEF2(ld8u_i64, 1, 1, 1, 0)
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| 102 | DEF2(ld8s_i64, 1, 1, 1, 0)
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| 103 | DEF2(ld16u_i64, 1, 1, 1, 0)
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| 104 | DEF2(ld16s_i64, 1, 1, 1, 0)
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| 105 | DEF2(ld32u_i64, 1, 1, 1, 0)
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| 106 | DEF2(ld32s_i64, 1, 1, 1, 0)
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| 107 | DEF2(ld_i64, 1, 1, 1, 0)
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| 108 | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 109 | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 110 | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 111 | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 112 | /* arith */
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| 113 | DEF2(add_i64, 1, 2, 0, 0)
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| 114 | DEF2(sub_i64, 1, 2, 0, 0)
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| 115 | DEF2(mul_i64, 1, 2, 0, 0)
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| 116 | #ifdef TCG_TARGET_HAS_div_i64
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| 117 | DEF2(div_i64, 1, 2, 0, 0)
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| 118 | DEF2(divu_i64, 1, 2, 0, 0)
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| 119 | DEF2(rem_i64, 1, 2, 0, 0)
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| 120 | DEF2(remu_i64, 1, 2, 0, 0)
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| 121 | #else
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| 122 | DEF2(div2_i64, 2, 3, 0, 0)
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| 123 | DEF2(divu2_i64, 2, 3, 0, 0)
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| 124 | #endif
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| 125 | DEF2(and_i64, 1, 2, 0, 0)
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| 126 | DEF2(or_i64, 1, 2, 0, 0)
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| 127 | DEF2(xor_i64, 1, 2, 0, 0)
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| 128 | /* shifts */
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| 129 | DEF2(shl_i64, 1, 2, 0, 0)
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| 130 | DEF2(shr_i64, 1, 2, 0, 0)
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| 131 | DEF2(sar_i64, 1, 2, 0, 0)
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| 132 |
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| 133 | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 134 | #ifdef TCG_TARGET_HAS_ext8s_i64
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| 135 | DEF2(ext8s_i64, 1, 1, 0, 0)
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| 136 | #endif
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| 137 | #ifdef TCG_TARGET_HAS_ext16s_i64
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| 138 | DEF2(ext16s_i64, 1, 1, 0, 0)
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| 139 | #endif
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| 140 | #ifdef TCG_TARGET_HAS_ext32s_i64
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| 141 | DEF2(ext32s_i64, 1, 1, 0, 0)
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| 142 | #endif
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| 143 | #ifdef TCG_TARGET_HAS_bswap_i64
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| 144 | DEF2(bswap_i64, 1, 1, 0, 0)
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| 145 | #endif
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| 146 | #endif
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| 147 | #ifdef TCG_TARGET_HAS_neg_i32
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| 148 | DEF2(neg_i32, 1, 1, 0, 0)
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| 149 | #endif
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| 150 | #ifdef TCG_TARGET_HAS_neg_i64
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| 151 | DEF2(neg_i64, 1, 1, 0, 0)
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| 152 | #endif
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| 153 |
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| 154 | /* QEMU specific */
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| 155 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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| 156 | DEF2(debug_insn_start, 0, 0, 2, 0)
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| 157 | #else
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| 158 | DEF2(debug_insn_start, 0, 0, 1, 0)
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| 159 | #endif
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| 160 | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 161 | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 162 | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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| 163 | constants must be defined */
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| 164 | #if TCG_TARGET_REG_BITS == 32
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| 165 | #if TARGET_LONG_BITS == 32
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| 166 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 167 | #else
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| 168 | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 169 | #endif
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| 170 | #if TARGET_LONG_BITS == 32
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| 171 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 172 | #else
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| 173 | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 174 | #endif
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| 175 | #if TARGET_LONG_BITS == 32
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| 176 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 177 | #else
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| 178 | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 179 | #endif
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| 180 | #if TARGET_LONG_BITS == 32
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| 181 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 182 | #else
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| 183 | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 184 | #endif
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| 185 | #if TARGET_LONG_BITS == 32
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| 186 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 187 | #else
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| 188 | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 189 | #endif
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| 190 | #if TARGET_LONG_BITS == 32
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| 191 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 192 | #else
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| 193 | DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 194 | #endif
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| 195 | #if TARGET_LONG_BITS == 32
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| 196 | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 197 | #else
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| 198 | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 199 | #endif
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| 200 |
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| 201 | #if TARGET_LONG_BITS == 32
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| 202 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 203 | #else
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| 204 | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 205 | #endif
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| 206 | #if TARGET_LONG_BITS == 32
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| 207 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 208 | #else
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| 209 | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 210 | #endif
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| 211 | #if TARGET_LONG_BITS == 32
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| 212 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 213 | #else
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| 214 | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 215 | #endif
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| 216 | #if TARGET_LONG_BITS == 32
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| 217 | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 218 | #else
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| 219 | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 220 | #endif
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| 221 |
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| 222 | #else /* TCG_TARGET_REG_BITS == 32 */
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| 223 |
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| 224 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 225 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 226 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 227 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 228 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 229 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 230 | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 231 |
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| 232 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 233 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 234 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 235 | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 236 |
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| 237 | #endif /* TCG_TARGET_REG_BITS != 32 */
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| 238 |
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| 239 | #undef DEF2
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