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source: vbox/trunk/src/recompiler/tcg/tcg-opc.h@ 36412

Last change on this file since 36412 was 36175, checked in by vboxsync, 14 years ago

rem: Synced up to v0.11.1 (35bfc7324e2e6946c4113ada5db30553a1a7c40b) from git://git.savannah.nongnu.org/qemu.git.

  • Property svn:eol-style set to native
File size: 8.0 KB
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1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#ifndef DEF2
25#define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0)
26#endif
27
28/* predefined ops */
29DEF2(end, 0, 0, 0, 0) /* must be kept first */
30DEF2(nop, 0, 0, 0, 0)
31DEF2(nop1, 0, 0, 1, 0)
32DEF2(nop2, 0, 0, 2, 0)
33DEF2(nop3, 0, 0, 3, 0)
34DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */
35
36DEF2(discard, 1, 0, 0, 0)
37
38DEF2(set_label, 0, 0, 1, 0)
39DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
40DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
41DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
42
43DEF2(mov_i32, 1, 1, 0, 0)
44DEF2(movi_i32, 1, 0, 1, 0)
45/* load/store */
46DEF2(ld8u_i32, 1, 1, 1, 0)
47DEF2(ld8s_i32, 1, 1, 1, 0)
48DEF2(ld16u_i32, 1, 1, 1, 0)
49DEF2(ld16s_i32, 1, 1, 1, 0)
50DEF2(ld_i32, 1, 1, 1, 0)
51DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
52DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
53DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
54/* arith */
55DEF2(add_i32, 1, 2, 0, 0)
56DEF2(sub_i32, 1, 2, 0, 0)
57DEF2(mul_i32, 1, 2, 0, 0)
58#ifdef TCG_TARGET_HAS_div_i32
59DEF2(div_i32, 1, 2, 0, 0)
60DEF2(divu_i32, 1, 2, 0, 0)
61DEF2(rem_i32, 1, 2, 0, 0)
62DEF2(remu_i32, 1, 2, 0, 0)
63#else
64DEF2(div2_i32, 2, 3, 0, 0)
65DEF2(divu2_i32, 2, 3, 0, 0)
66#endif
67DEF2(and_i32, 1, 2, 0, 0)
68DEF2(or_i32, 1, 2, 0, 0)
69DEF2(xor_i32, 1, 2, 0, 0)
70/* shifts/rotates */
71DEF2(shl_i32, 1, 2, 0, 0)
72DEF2(shr_i32, 1, 2, 0, 0)
73DEF2(sar_i32, 1, 2, 0, 0)
74#ifdef TCG_TARGET_HAS_rot_i32
75DEF2(rotl_i32, 1, 2, 0, 0)
76DEF2(rotr_i32, 1, 2, 0, 0)
77#endif
78
79DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
80#if TCG_TARGET_REG_BITS == 32
81DEF2(add2_i32, 2, 4, 0, 0)
82DEF2(sub2_i32, 2, 4, 0, 0)
83DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
84DEF2(mulu2_i32, 2, 2, 0, 0)
85#endif
86#ifdef TCG_TARGET_HAS_ext8s_i32
87DEF2(ext8s_i32, 1, 1, 0, 0)
88#endif
89#ifdef TCG_TARGET_HAS_ext16s_i32
90DEF2(ext16s_i32, 1, 1, 0, 0)
91#endif
92#ifdef TCG_TARGET_HAS_bswap16_i32
93DEF2(bswap16_i32, 1, 1, 0, 0)
94#endif
95#ifdef TCG_TARGET_HAS_bswap32_i32
96DEF2(bswap32_i32, 1, 1, 0, 0)
97#endif
98#ifdef TCG_TARGET_HAS_not_i32
99DEF2(not_i32, 1, 1, 0, 0)
100#endif
101#ifdef TCG_TARGET_HAS_neg_i32
102DEF2(neg_i32, 1, 1, 0, 0)
103#endif
104
105#if TCG_TARGET_REG_BITS == 64
106DEF2(mov_i64, 1, 1, 0, 0)
107DEF2(movi_i64, 1, 0, 1, 0)
108/* load/store */
109DEF2(ld8u_i64, 1, 1, 1, 0)
110DEF2(ld8s_i64, 1, 1, 1, 0)
111DEF2(ld16u_i64, 1, 1, 1, 0)
112DEF2(ld16s_i64, 1, 1, 1, 0)
113DEF2(ld32u_i64, 1, 1, 1, 0)
114DEF2(ld32s_i64, 1, 1, 1, 0)
115DEF2(ld_i64, 1, 1, 1, 0)
116DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
117DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
118DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
119DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
120/* arith */
121DEF2(add_i64, 1, 2, 0, 0)
122DEF2(sub_i64, 1, 2, 0, 0)
123DEF2(mul_i64, 1, 2, 0, 0)
124#ifdef TCG_TARGET_HAS_div_i64
125DEF2(div_i64, 1, 2, 0, 0)
126DEF2(divu_i64, 1, 2, 0, 0)
127DEF2(rem_i64, 1, 2, 0, 0)
128DEF2(remu_i64, 1, 2, 0, 0)
129#else
130DEF2(div2_i64, 2, 3, 0, 0)
131DEF2(divu2_i64, 2, 3, 0, 0)
132#endif
133DEF2(and_i64, 1, 2, 0, 0)
134DEF2(or_i64, 1, 2, 0, 0)
135DEF2(xor_i64, 1, 2, 0, 0)
136/* shifts/rotates */
137DEF2(shl_i64, 1, 2, 0, 0)
138DEF2(shr_i64, 1, 2, 0, 0)
139DEF2(sar_i64, 1, 2, 0, 0)
140#ifdef TCG_TARGET_HAS_rot_i64
141DEF2(rotl_i64, 1, 2, 0, 0)
142DEF2(rotr_i64, 1, 2, 0, 0)
143#endif
144
145DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
146#ifdef TCG_TARGET_HAS_ext8s_i64
147DEF2(ext8s_i64, 1, 1, 0, 0)
148#endif
149#ifdef TCG_TARGET_HAS_ext16s_i64
150DEF2(ext16s_i64, 1, 1, 0, 0)
151#endif
152#ifdef TCG_TARGET_HAS_ext32s_i64
153DEF2(ext32s_i64, 1, 1, 0, 0)
154#endif
155#ifdef TCG_TARGET_HAS_bswap16_i64
156DEF2(bswap16_i64, 1, 1, 0, 0)
157#endif
158#ifdef TCG_TARGET_HAS_bswap32_i64
159DEF2(bswap32_i64, 1, 1, 0, 0)
160#endif
161#ifdef TCG_TARGET_HAS_bswap64_i64
162DEF2(bswap64_i64, 1, 1, 0, 0)
163#endif
164#ifdef TCG_TARGET_HAS_not_i64
165DEF2(not_i64, 1, 1, 0, 0)
166#endif
167#ifdef TCG_TARGET_HAS_neg_i64
168DEF2(neg_i64, 1, 1, 0, 0)
169#endif
170#endif
171
172/* QEMU specific */
173#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
174DEF2(debug_insn_start, 0, 0, 2, 0)
175#else
176DEF2(debug_insn_start, 0, 0, 1, 0)
177#endif
178DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
179DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
180/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
181 constants must be defined */
182#if TCG_TARGET_REG_BITS == 32
183#if TARGET_LONG_BITS == 32
184DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
185#else
186DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
187#endif
188#if TARGET_LONG_BITS == 32
189DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
190#else
191DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
192#endif
193#if TARGET_LONG_BITS == 32
194DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
195#else
196DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
197#endif
198#if TARGET_LONG_BITS == 32
199DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
200#else
201DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
202#endif
203#if TARGET_LONG_BITS == 32
204DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
205#else
206DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
207#endif
208#if TARGET_LONG_BITS == 32
209DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
210#else
211DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
212#endif
213#if TARGET_LONG_BITS == 32
214DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
215#else
216DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
217#endif
218
219#if TARGET_LONG_BITS == 32
220DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
221#else
222DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
223#endif
224#if TARGET_LONG_BITS == 32
225DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
226#else
227DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
228#endif
229#if TARGET_LONG_BITS == 32
230DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
231#else
232DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
233#endif
234#if TARGET_LONG_BITS == 32
235DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
236#else
237DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
238#endif
239
240#else /* TCG_TARGET_REG_BITS == 32 */
241
242DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
243DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
244DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
245DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
246DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
247DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
248DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
249
250DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
251DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
252DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
253DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
254
255#endif /* TCG_TARGET_REG_BITS != 32 */
256
257#undef DEF2
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