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source: vbox/trunk/src/recompiler/tcg/tcg-opc.h@ 39615

Last change on this file since 39615 was 37689, checked in by vboxsync, 13 years ago

recompiler: Merged in changes from 0.13.0.

  • Property svn:eol-style set to native
File size: 8.8 KB
Line 
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25/*
26 * DEF(name, oargs, iargs, cargs, flags)
27 */
28
29/* predefined ops */
30DEF(end, 0, 0, 0, 0) /* must be kept first */
31DEF(nop, 0, 0, 0, 0)
32DEF(nop1, 0, 0, 1, 0)
33DEF(nop2, 0, 0, 2, 0)
34DEF(nop3, 0, 0, 3, 0)
35DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
36
37DEF(discard, 1, 0, 0, 0)
38
39DEF(set_label, 0, 0, 1, 0)
40DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
41DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
42DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
43
44DEF(mov_i32, 1, 1, 0, 0)
45DEF(movi_i32, 1, 0, 1, 0)
46DEF(setcond_i32, 1, 2, 1, 0)
47/* load/store */
48DEF(ld8u_i32, 1, 1, 1, 0)
49DEF(ld8s_i32, 1, 1, 1, 0)
50DEF(ld16u_i32, 1, 1, 1, 0)
51DEF(ld16s_i32, 1, 1, 1, 0)
52DEF(ld_i32, 1, 1, 1, 0)
53DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
54DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
55DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
56/* arith */
57DEF(add_i32, 1, 2, 0, 0)
58DEF(sub_i32, 1, 2, 0, 0)
59DEF(mul_i32, 1, 2, 0, 0)
60#ifdef TCG_TARGET_HAS_div_i32
61DEF(div_i32, 1, 2, 0, 0)
62DEF(divu_i32, 1, 2, 0, 0)
63DEF(rem_i32, 1, 2, 0, 0)
64DEF(remu_i32, 1, 2, 0, 0)
65#endif
66#ifdef TCG_TARGET_HAS_div2_i32
67DEF(div2_i32, 2, 3, 0, 0)
68DEF(divu2_i32, 2, 3, 0, 0)
69#endif
70DEF(and_i32, 1, 2, 0, 0)
71DEF(or_i32, 1, 2, 0, 0)
72DEF(xor_i32, 1, 2, 0, 0)
73/* shifts/rotates */
74DEF(shl_i32, 1, 2, 0, 0)
75DEF(shr_i32, 1, 2, 0, 0)
76DEF(sar_i32, 1, 2, 0, 0)
77#ifdef TCG_TARGET_HAS_rot_i32
78DEF(rotl_i32, 1, 2, 0, 0)
79DEF(rotr_i32, 1, 2, 0, 0)
80#endif
81
82DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
83#if TCG_TARGET_REG_BITS == 32
84DEF(add2_i32, 2, 4, 0, 0)
85DEF(sub2_i32, 2, 4, 0, 0)
86DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
87DEF(mulu2_i32, 2, 2, 0, 0)
88DEF(setcond2_i32, 1, 4, 1, 0)
89#endif
90#ifdef TCG_TARGET_HAS_ext8s_i32
91DEF(ext8s_i32, 1, 1, 0, 0)
92#endif
93#ifdef TCG_TARGET_HAS_ext16s_i32
94DEF(ext16s_i32, 1, 1, 0, 0)
95#endif
96#ifdef TCG_TARGET_HAS_ext8u_i32
97DEF(ext8u_i32, 1, 1, 0, 0)
98#endif
99#ifdef TCG_TARGET_HAS_ext16u_i32
100DEF(ext16u_i32, 1, 1, 0, 0)
101#endif
102#ifdef TCG_TARGET_HAS_bswap16_i32
103DEF(bswap16_i32, 1, 1, 0, 0)
104#endif
105#ifdef TCG_TARGET_HAS_bswap32_i32
106DEF(bswap32_i32, 1, 1, 0, 0)
107#endif
108#ifdef TCG_TARGET_HAS_not_i32
109DEF(not_i32, 1, 1, 0, 0)
110#endif
111#ifdef TCG_TARGET_HAS_neg_i32
112DEF(neg_i32, 1, 1, 0, 0)
113#endif
114#ifdef TCG_TARGET_HAS_andc_i32
115DEF(andc_i32, 1, 2, 0, 0)
116#endif
117#ifdef TCG_TARGET_HAS_orc_i32
118DEF(orc_i32, 1, 2, 0, 0)
119#endif
120#ifdef TCG_TARGET_HAS_eqv_i32
121DEF(eqv_i32, 1, 2, 0, 0)
122#endif
123#ifdef TCG_TARGET_HAS_nand_i32
124DEF(nand_i32, 1, 2, 0, 0)
125#endif
126#ifdef TCG_TARGET_HAS_nor_i32
127DEF(nor_i32, 1, 2, 0, 0)
128#endif
129
130#if TCG_TARGET_REG_BITS == 64
131DEF(mov_i64, 1, 1, 0, 0)
132DEF(movi_i64, 1, 0, 1, 0)
133DEF(setcond_i64, 1, 2, 1, 0)
134/* load/store */
135DEF(ld8u_i64, 1, 1, 1, 0)
136DEF(ld8s_i64, 1, 1, 1, 0)
137DEF(ld16u_i64, 1, 1, 1, 0)
138DEF(ld16s_i64, 1, 1, 1, 0)
139DEF(ld32u_i64, 1, 1, 1, 0)
140DEF(ld32s_i64, 1, 1, 1, 0)
141DEF(ld_i64, 1, 1, 1, 0)
142DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
143DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
144DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
145DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
146/* arith */
147DEF(add_i64, 1, 2, 0, 0)
148DEF(sub_i64, 1, 2, 0, 0)
149DEF(mul_i64, 1, 2, 0, 0)
150#ifdef TCG_TARGET_HAS_div_i64
151DEF(div_i64, 1, 2, 0, 0)
152DEF(divu_i64, 1, 2, 0, 0)
153DEF(rem_i64, 1, 2, 0, 0)
154DEF(remu_i64, 1, 2, 0, 0)
155#endif
156#ifdef TCG_TARGET_HAS_div2_i64
157DEF(div2_i64, 2, 3, 0, 0)
158DEF(divu2_i64, 2, 3, 0, 0)
159#endif
160DEF(and_i64, 1, 2, 0, 0)
161DEF(or_i64, 1, 2, 0, 0)
162DEF(xor_i64, 1, 2, 0, 0)
163/* shifts/rotates */
164DEF(shl_i64, 1, 2, 0, 0)
165DEF(shr_i64, 1, 2, 0, 0)
166DEF(sar_i64, 1, 2, 0, 0)
167#ifdef TCG_TARGET_HAS_rot_i64
168DEF(rotl_i64, 1, 2, 0, 0)
169DEF(rotr_i64, 1, 2, 0, 0)
170#endif
171
172DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
173#ifdef TCG_TARGET_HAS_ext8s_i64
174DEF(ext8s_i64, 1, 1, 0, 0)
175#endif
176#ifdef TCG_TARGET_HAS_ext16s_i64
177DEF(ext16s_i64, 1, 1, 0, 0)
178#endif
179#ifdef TCG_TARGET_HAS_ext32s_i64
180DEF(ext32s_i64, 1, 1, 0, 0)
181#endif
182#ifdef TCG_TARGET_HAS_ext8u_i64
183DEF(ext8u_i64, 1, 1, 0, 0)
184#endif
185#ifdef TCG_TARGET_HAS_ext16u_i64
186DEF(ext16u_i64, 1, 1, 0, 0)
187#endif
188#ifdef TCG_TARGET_HAS_ext32u_i64
189DEF(ext32u_i64, 1, 1, 0, 0)
190#endif
191#ifdef TCG_TARGET_HAS_bswap16_i64
192DEF(bswap16_i64, 1, 1, 0, 0)
193#endif
194#ifdef TCG_TARGET_HAS_bswap32_i64
195DEF(bswap32_i64, 1, 1, 0, 0)
196#endif
197#ifdef TCG_TARGET_HAS_bswap64_i64
198DEF(bswap64_i64, 1, 1, 0, 0)
199#endif
200#ifdef TCG_TARGET_HAS_not_i64
201DEF(not_i64, 1, 1, 0, 0)
202#endif
203#ifdef TCG_TARGET_HAS_neg_i64
204DEF(neg_i64, 1, 1, 0, 0)
205#endif
206#ifdef TCG_TARGET_HAS_andc_i64
207DEF(andc_i64, 1, 2, 0, 0)
208#endif
209#ifdef TCG_TARGET_HAS_orc_i64
210DEF(orc_i64, 1, 2, 0, 0)
211#endif
212#ifdef TCG_TARGET_HAS_eqv_i64
213DEF(eqv_i64, 1, 2, 0, 0)
214#endif
215#ifdef TCG_TARGET_HAS_nand_i64
216DEF(nand_i64, 1, 2, 0, 0)
217#endif
218#ifdef TCG_TARGET_HAS_nor_i64
219DEF(nor_i64, 1, 2, 0, 0)
220#endif
221#endif
222
223/* QEMU specific */
224#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
225DEF(debug_insn_start, 0, 0, 2, 0)
226#else
227DEF(debug_insn_start, 0, 0, 1, 0)
228#endif
229DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
230DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
231/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
232 constants must be defined */
233#if TCG_TARGET_REG_BITS == 32
234#if TARGET_LONG_BITS == 32
235DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
236#else
237DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
238#endif
239#if TARGET_LONG_BITS == 32
240DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
241#else
242DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
243#endif
244#if TARGET_LONG_BITS == 32
245DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
246#else
247DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
248#endif
249#if TARGET_LONG_BITS == 32
250DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
251#else
252DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
253#endif
254#if TARGET_LONG_BITS == 32
255DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
256#else
257DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
258#endif
259#if TARGET_LONG_BITS == 32
260DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
261#else
262DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
263#endif
264
265#if TARGET_LONG_BITS == 32
266DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
267#else
268DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
269#endif
270#if TARGET_LONG_BITS == 32
271DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
272#else
273DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
274#endif
275#if TARGET_LONG_BITS == 32
276DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
277#else
278DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
279#endif
280#if TARGET_LONG_BITS == 32
281DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
282#else
283DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
284#endif
285
286#else /* TCG_TARGET_REG_BITS == 32 */
287
288DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
289DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
290DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
291DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
292DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
293DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
294DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
295DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
296
297DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
298DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
299DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
300DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
301
302#endif /* TCG_TARGET_REG_BITS != 32 */
303
304#undef DEF
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