tcg-target.c@ 33366

Last change on this file since 33366 was 29520, checked in by vboxsync, 15 years ago
fix wrong license headers
Property svn:eol-style set to `native`
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1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24
25	#ifndef NDEBUG
26	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27	"%rax",
28	"%rcx",
29	"%rdx",
30	"%rbx",
31	"%rsp",
32	"%rbp",
33	"%rsi",
34	"%rdi",
35	"%r8",
36	"%r9",
37	"%r10",
38	"%r11",
39	"%r12",
40	"%r13",
41	"%r14",
42	"%r15",
43	};
44	#endif
45
46	static const int tcg_target_reg_alloc_order[] = {
47	TCG_REG_RDI,
48	TCG_REG_RSI,
49	TCG_REG_RDX,
50	TCG_REG_RCX,
51	TCG_REG_R8,
52	TCG_REG_R9,
53	TCG_REG_RAX,
54	TCG_REG_R10,
55	TCG_REG_R11,
56
57	TCG_REG_RBP,
58	TCG_REG_RBX,
59	TCG_REG_R12,
60	TCG_REG_R13,
61	TCG_REG_R14,
62	TCG_REG_R15,
63	};
64
65	static const int tcg_target_call_iarg_regs[6] = {
66	TCG_REG_RDI,
67	TCG_REG_RSI,
68	TCG_REG_RDX,
69	TCG_REG_RCX,
70	TCG_REG_R8,
71	TCG_REG_R9,
72	};
73
74	static const int tcg_target_call_oarg_regs[2] = {
75	TCG_REG_RAX,
76	TCG_REG_RDX
77	};
78
79	static uint8_t *tb_ret_addr;
80
81	static void patch_reloc(uint8_t *code_ptr, int type,
82	tcg_target_long value, tcg_target_long addend)
83	{
84	value += addend;
85	switch(type) {
86	case R_X86_64_32:
87	if (value != (uint32_t)value)
88	tcg_abort();
89	(uint32_t )code_ptr = value;
90	break;
91	case R_X86_64_32S:
92	if (value != (int32_t)value)
93	tcg_abort();
94	(uint32_t )code_ptr = value;
95	break;
96	case R_386_PC32:
97	value -= (long)code_ptr;
98	if (value != (int32_t)value)
99	tcg_abort();
100	(uint32_t )code_ptr = value;
101	break;
102	default:
103	tcg_abort();
104	}
105	}
106
107	/* maximum number of register used for input function arguments */
108	static inline int tcg_target_get_call_iarg_regs_count(int flags)
109	{
110	return 6;
111	}
112
113	/* parse target specific constraints */
114	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
115	{
116	const char *ct_str;
117
118	ct_str = *pct_str;
119	switch(ct_str[0]) {
120	case 'a':
121	ct->ct \|= TCG_CT_REG;
122	tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
123	break;
124	case 'b':
125	ct->ct \|= TCG_CT_REG;
126	tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
127	break;
128	case 'c':
129	ct->ct \|= TCG_CT_REG;
130	tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
131	break;
132	case 'd':
133	ct->ct \|= TCG_CT_REG;
134	tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
135	break;
136	case 'S':
137	ct->ct \|= TCG_CT_REG;
138	tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
139	break;
140	case 'D':
141	ct->ct \|= TCG_CT_REG;
142	tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
143	break;
144	case 'q':
145	ct->ct \|= TCG_CT_REG;
146	tcg_regset_set32(ct->u.regs, 0, 0xf);
147	break;
148	case 'r':
149	ct->ct \|= TCG_CT_REG;
150	tcg_regset_set32(ct->u.regs, 0, 0xffff);
151	break;
152	case 'L': /* qemu_ld/st constraint */
153	ct->ct \|= TCG_CT_REG;
154	tcg_regset_set32(ct->u.regs, 0, 0xffff);
155	tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
156	tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
157	break;
158	case 'e':
159	ct->ct \|= TCG_CT_CONST_S32;
160	break;
161	case 'Z':
162	ct->ct \|= TCG_CT_CONST_U32;
163	break;
164	default:
165	return -1;
166	}
167	ct_str++;
168	*pct_str = ct_str;
169	return 0;
170	}
171
172	/* test if a constant matches the constraint */
173	static inline int tcg_target_const_match(tcg_target_long val,
174	const TCGArgConstraint *arg_ct)
175	{
176	int ct;
177	ct = arg_ct->ct;
178	if (ct & TCG_CT_CONST)
179	return 1;
180	else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
181	return 1;
182	else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
183	return 1;
184	else
185	return 0;
186	}
187
188	#define ARITH_ADD 0
189	#define ARITH_OR 1
190	#define ARITH_ADC 2
191	#define ARITH_SBB 3
192	#define ARITH_AND 4
193	#define ARITH_SUB 5
194	#define ARITH_XOR 6
195	#define ARITH_CMP 7
196
197	#define SHIFT_SHL 4
198	#define SHIFT_SHR 5
199	#define SHIFT_SAR 7
200
201	#define JCC_JMP (-1)
202	#define JCC_JO 0x0
203	#define JCC_JNO 0x1
204	#define JCC_JB 0x2
205	#define JCC_JAE 0x3
206	#define JCC_JE 0x4
207	#define JCC_JNE 0x5
208	#define JCC_JBE 0x6
209	#define JCC_JA 0x7
210	#define JCC_JS 0x8
211	#define JCC_JNS 0x9
212	#define JCC_JP 0xa
213	#define JCC_JNP 0xb
214	#define JCC_JL 0xc
215	#define JCC_JGE 0xd
216	#define JCC_JLE 0xe
217	#define JCC_JG 0xf
218
219	#define P_EXT 0x100 /* 0x0f opcode prefix */
220	#define P_REXW 0x200 /* set rex.w = 1 */
221	#define P_REXB 0x400 /* force rex use for byte registers */
222
223	static const uint8_t tcg_cond_to_jcc[10] = {
224	[TCG_COND_EQ] = JCC_JE,
225	[TCG_COND_NE] = JCC_JNE,
226	[TCG_COND_LT] = JCC_JL,
227	[TCG_COND_GE] = JCC_JGE,
228	[TCG_COND_LE] = JCC_JLE,
229	[TCG_COND_GT] = JCC_JG,
230	[TCG_COND_LTU] = JCC_JB,
231	[TCG_COND_GEU] = JCC_JAE,
232	[TCG_COND_LEU] = JCC_JBE,
233	[TCG_COND_GTU] = JCC_JA,
234	};
235
236	static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
237	{
238	int rex;
239	rex = ((opc >> 6) & 0x8) \| ((r >> 1) & 0x4) \|
240	((x >> 2) & 2) \| ((rm >> 3) & 1);
241	if (rex \|\| (opc & P_REXB)) {
242	tcg_out8(s, rex \| 0x40);
243	}
244	if (opc & P_EXT)
245	tcg_out8(s, 0x0f);
246	tcg_out8(s, opc);
247	}
248
249	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
250	{
251	tcg_out_opc(s, opc, r, rm, 0);
252	tcg_out8(s, 0xc0 \| ((r & 7) << 3) \| (rm & 7));
253	}
254
255	static inline void tcg_out_push(TCGContext *s, int reg)
256	{
257	tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
258	}
259
260	static inline void tcg_out_pop(TCGContext *s, int reg)
261	{
262	tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
263	}
264
265
266	/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
267	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
268	tcg_target_long offset)
269	{
270	if (rm < 0) {
271	tcg_target_long val;
272	tcg_out_opc(s, opc, r, 0, 0);
273	val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
274	if (val == (int32_t)val) {
275	/* eip relative */
276	tcg_out8(s, 0x05 \| ((r & 7) << 3));
277	tcg_out32(s, val);
278	} else if (offset == (int32_t)offset) {
279	tcg_out8(s, 0x04 \| ((r & 7) << 3));
280	tcg_out8(s, 0x25); /* sib */
281	tcg_out32(s, offset);
282	} else {
283	tcg_abort();
284	}
285	} else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
286	tcg_out_opc(s, opc, r, rm, 0);
287	if ((rm & 7) == TCG_REG_RSP) {
288	tcg_out8(s, 0x04 \| ((r & 7) << 3));
289	tcg_out8(s, 0x24);
290	} else {
291	tcg_out8(s, 0x00 \| ((r & 7) << 3) \| (rm & 7));
292	}
293	} else if ((int8_t)offset == offset) {
294	tcg_out_opc(s, opc, r, rm, 0);
295	if ((rm & 7) == TCG_REG_RSP) {
296	tcg_out8(s, 0x44 \| ((r & 7) << 3));
297	tcg_out8(s, 0x24);
298	} else {
299	tcg_out8(s, 0x40 \| ((r & 7) << 3) \| (rm & 7));
300	}
301	tcg_out8(s, offset);
302	} else {
303	tcg_out_opc(s, opc, r, rm, 0);
304	if ((rm & 7) == TCG_REG_RSP) {
305	tcg_out8(s, 0x84 \| ((r & 7) << 3));
306	tcg_out8(s, 0x24);
307	} else {
308	tcg_out8(s, 0x80 \| ((r & 7) << 3) \| (rm & 7));
309	}
310	tcg_out32(s, offset);
311	}
312	}
313
314	#if defined(CONFIG_SOFTMMU)
315	/* XXX: incomplete. index must be different from ESP */
316	static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
317	int index, int shift,
318	tcg_target_long offset)
319	{
320	int mod;
321	if (rm == -1)
322	tcg_abort();
323	if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
324	mod = 0;
325	} else if (offset == (int8_t)offset) {
326	mod = 0x40;
327	} else if (offset == (int32_t)offset) {
328	mod = 0x80;
329	} else {
330	tcg_abort();
331	}
332	if (index == -1) {
333	tcg_out_opc(s, opc, r, rm, 0);
334	if ((rm & 7) == TCG_REG_RSP) {
335	tcg_out8(s, mod \| ((r & 7) << 3) \| 0x04);
336	tcg_out8(s, 0x04 \| (rm & 7));
337	} else {
338	tcg_out8(s, mod \| ((r & 7) << 3) \| (rm & 7));
339	}
340	} else {
341	tcg_out_opc(s, opc, r, rm, index);
342	tcg_out8(s, mod \| ((r & 7) << 3) \| 0x04);
343	tcg_out8(s, (shift << 6) \| ((index & 7) << 3) \| (rm & 7));
344	}
345	if (mod == 0x40) {
346	tcg_out8(s, offset);
347	} else if (mod == 0x80) {
348	tcg_out32(s, offset);
349	}
350	}
351	#endif
352
353	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
354	{
355	tcg_out_modrm(s, 0x8b \| P_REXW, ret, arg);
356	}
357
358	static inline void tcg_out_movi(TCGContext *s, TCGType type,
359	int ret, tcg_target_long arg)
360	{
361	if (arg == 0) {
362	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
363	} else if (arg == (uint32_t)arg \|\| type == TCG_TYPE_I32) {
364	tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
365	tcg_out32(s, arg);
366	} else if (arg == (int32_t)arg) {
367	tcg_out_modrm(s, 0xc7 \| P_REXW, 0, ret);
368	tcg_out32(s, arg);
369	} else {
370	tcg_out_opc(s, (0xb8 + (ret & 7)) \| P_REXW, 0, ret, 0);
371	tcg_out32(s, arg);
372	tcg_out32(s, arg >> 32);
373	}
374	}
375
376	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
377	int arg1, tcg_target_long arg2)
378	{
379	if (type == TCG_TYPE_I32)
380	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
381	else
382	tcg_out_modrm_offset(s, 0x8b \| P_REXW, ret, arg1, arg2); /* movq */
383	}
384
385	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
386	int arg1, tcg_target_long arg2)
387	{
388	if (type == TCG_TYPE_I32)
389	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
390	else
391	tcg_out_modrm_offset(s, 0x89 \| P_REXW, arg, arg1, arg2); /* movq */
392	}
393
394	static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
395	{
396	if (val == (int8_t)val) {
397	tcg_out_modrm(s, 0x83, c, r0);
398	tcg_out8(s, val);
399	} else if (c == ARITH_AND && val == 0xffu) {
400	/* movzbl */
401	tcg_out_modrm(s, 0xb6 \| P_EXT \| P_REXB, r0, r0);
402	} else if (c == ARITH_AND && val == 0xffffu) {
403	/* movzwl */
404	tcg_out_modrm(s, 0xb7 \| P_EXT, r0, r0);
405	} else {
406	tcg_out_modrm(s, 0x81, c, r0);
407	tcg_out32(s, val);
408	}
409	}
410
411	static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
412	{
413	if (val == (int8_t)val) {
414	tcg_out_modrm(s, 0x83 \| P_REXW, c, r0);
415	tcg_out8(s, val);
416	} else if (c == ARITH_AND && val == 0xffu) {
417	/* movzbl */
418	tcg_out_modrm(s, 0xb6 \| P_EXT \| P_REXW, r0, r0);
419	} else if (c == ARITH_AND && val == 0xffffu) {
420	/* movzwl */
421	tcg_out_modrm(s, 0xb7 \| P_EXT \| P_REXW, r0, r0);
422	} else if (c == ARITH_AND && val == 0xffffffffu) {
423	/* 32-bit mov zero extends */
424	tcg_out_modrm(s, 0x8b, r0, r0);
425	} else if (val == (int32_t)val) {
426	tcg_out_modrm(s, 0x81 \| P_REXW, c, r0);
427	tcg_out32(s, val);
428	} else if (c == ARITH_AND && val == (uint32_t)val) {
429	tcg_out_modrm(s, 0x81, c, r0);
430	tcg_out32(s, val);
431	} else {
432	tcg_abort();
433	}
434	}
435
436	static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
437	{
438	if (val != 0)
439	tgen_arithi64(s, ARITH_ADD, reg, val);
440	}
441
442	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
443	{
444	int32_t val, val1;
445	TCGLabel *l = &s->labels[label_index];
446
447	if (l->has_value) {
448	val = l->u.value - (tcg_target_long)s->code_ptr;
449	val1 = val - 2;
450	if ((int8_t)val1 == val1) {
451	if (opc == -1)
452	tcg_out8(s, 0xeb);
453	else
454	tcg_out8(s, 0x70 + opc);
455	tcg_out8(s, val1);
456	} else {
457	if (opc == -1) {
458	tcg_out8(s, 0xe9);
459	tcg_out32(s, val - 5);
460	} else {
461	tcg_out8(s, 0x0f);
462	tcg_out8(s, 0x80 + opc);
463	tcg_out32(s, val - 6);
464	}
465	}
466	} else {
467	if (opc == -1) {
468	tcg_out8(s, 0xe9);
469	} else {
470	tcg_out8(s, 0x0f);
471	tcg_out8(s, 0x80 + opc);
472	}
473	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
474	s->code_ptr += 4;
475	}
476	}
477
478	static void tcg_out_brcond(TCGContext *s, int cond,
479	TCGArg arg1, TCGArg arg2, int const_arg2,
480	int label_index, int rexw)
481	{
482	if (const_arg2) {
483	if (arg2 == 0) {
484	/* test r, r */
485	tcg_out_modrm(s, 0x85 \| rexw, arg1, arg1);
486	} else {
487	if (rexw)
488	tgen_arithi64(s, ARITH_CMP, arg1, arg2);
489	else
490	tgen_arithi32(s, ARITH_CMP, arg1, arg2);
491	}
492	} else {
493	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3) \| rexw, arg2, arg1);
494	}
495	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
496	}
497
498	#ifdef VBOX
499	DECLINLINE(void) tcg_out_pushq(TCGContext *s, tcg_target_long val)
500	{
501	tcg_out8(s, 0x68); /* push imm32, subs 8 from rsp */
502	tcg_out32(s, val); /* imm32 */
503	if ((val >> 32) != 0)
504	{
505	tcg_out8(s, 0xc7); /* mov imm32, 4(%rsp) */
506	tcg_out8(s, 0x44);
507	tcg_out8(s, 0x24);
508	tcg_out8(s, 0x04);
509	tcg_out32(s, ((uint64_t)val) >> 32); /* imm32 */
510	}
511	}
512
513	DECLINLINE(void) tcg_out_long_call(TCGContext *s, tcg_target_long dst)
514	{
515	intptr_t disp = dst - (tcg_target_long)s->code_ptr - 5;
516	/* can do normal call */
517	if (disp < 2LL * _1G && disp > -2LL * _1G)
518	{
519	tcg_out8(s, 0xe8); /* call disp32 */
520	tcg_out32(s, disp); /* disp32 */
521	}
522	else
523	{
524	#if 0
525	/* Somewhat tricky, but allows long jump not touching registers */
526	int off = 5 /* push imm32 / + 5 / push imm32 / + 1 / ret */;
527	if ((((uint64_t)s->code_ptr) + 32) >> 32)
528	off += 8;
529	if (dst >> 32)
530	off += 8;
531	/* return address */
532	tcg_out_pushq(s, (tcg_target_long)s->code_ptr+off);
533	/* destination */
534	tcg_out_pushq(s, dst);
535	tcg_out8(s, 0xc3); /* ret, used as call */
536	#else
537	tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
538	tcg_out8(s, 0xff); /* call %eax /
539	tcg_out8(s, 0xd0);
540	#endif
541	}
542	}
543
544	DECLINLINE(void) tcg_out_long_jmp(TCGContext *s, tcg_target_long dst)
545	{
546	intptr_t disp;
547
548	disp = dst - (tcg_target_long)s->code_ptr - 2;
549	/* can do short relative jump */
550	if (disp < 0x7f && disp > -0x7f)
551	{
552	tcg_out8(s, 0xeb); /* short jmp */
553	tcg_out8(s, (int8_t)disp);
554	return;
555	}
556
557	disp = dst - (tcg_target_long)s->code_ptr - 5;
558	if (disp < 2LL * _1G && disp > -2LL * _1G)
559	{
560	tcg_out8(s, 0xe9); /* jmp */
561	tcg_out32(s, (int32_t)disp);
562	return;
563	}
564	#if 0
565	tcg_out_pushq(s, dst);
566	tcg_out8(s, 0xc3); /* ret */
567	#else
568	tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
569	tcg_out8(s, 0xff); /* jmp %eax /
570	tcg_out8(s, 0xe0);
571	#endif
572	}
573	#endif
574
575	#if defined(CONFIG_SOFTMMU)
576
577	#include "../../softmmu_defs.h"
578
579	static void *qemu_ld_helpers[4] = {
580	__ldb_mmu,
581	__ldw_mmu,
582	__ldl_mmu,
583	__ldq_mmu,
584	};
585
586	static void *qemu_st_helpers[4] = {
587	__stb_mmu,
588	__stw_mmu,
589	__stl_mmu,
590	__stq_mmu,
591	};
592	#endif
593
594	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
595	static void *vbox_ld_helpers[] = {
596	__ldub_vbox_phys,
597	__lduw_vbox_phys,
598	__ldul_vbox_phys,
599	__ldq_vbox_phys,
600	__ldb_vbox_phys,
601	__ldw_vbox_phys,
602	__ldl_vbox_phys,
603	__ldq_vbox_phys,
604	};
605
606	static void *vbox_st_helpers[] = {
607	__stb_vbox_phys,
608	__stw_vbox_phys,
609	__stl_vbox_phys,
610	__stq_vbox_phys
611	};
612
613	static void tcg_out_vbox_phys_read(TCGContext *s, int index, int addr_reg, int data_reg) {
614	if (addr_reg != TCG_REG_RDI)
615	/* mov addr_reg, %rdi */
616	tcg_out_modrm(s, 0x8b \| P_REXW, TCG_REG_RDI, addr_reg);
617
618	tcg_out_long_call(s, (tcg_target_long)vbox_ld_helpers[index]);
619	/* mov %rax, data_reg*/
620	tcg_out_modrm(s, 0x8b \| P_REXW, data_reg, TCG_REG_RAX);
621	}
622
623	static void tcg_out_vbox_phys_write(TCGContext *s, int index, int addr_reg, int val_reg) {
624	if (addr_reg != TCG_REG_RDI)
625	/* mov addr_reg, %rdi */
626	tcg_out_modrm(s, 0x8b \| P_REXW, TCG_REG_RDI, addr_reg);
627	if (val_reg != TCG_REG_RSI)
628	/* mov addr_reg, %rsi */
629	tcg_out_modrm(s, 0x8b \| P_REXW, TCG_REG_RSI, val_reg);
630	tcg_out_long_call(s, (tcg_target_long)vbox_st_helpers[index]);
631	}
632
633	#endif
634
635	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
636	int opc)
637	{
638	int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
639	#if defined(CONFIG_SOFTMMU)
640	uint8_t label1_ptr, label2_ptr;
641	#endif
642
643	data_reg = *args++;
644	addr_reg = *args++;
645	mem_index = *args;
646	s_bits = opc & 3;
647
648	r0 = TCG_REG_RDI;
649	r1 = TCG_REG_RSI;
650
651	#if TARGET_LONG_BITS == 32
652	rexw = 0;
653	#else
654	rexw = P_REXW;
655	#endif
656	#if defined(CONFIG_SOFTMMU)
657	/* mov */
658	tcg_out_modrm(s, 0x8b \| rexw, r1, addr_reg);
659
660	/* mov */
661	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
662
663	tcg_out_modrm(s, 0xc1 \| rexw, 5, r1); /* shr $x, r1 */
664	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
665
666	tcg_out_modrm(s, 0x81 \| rexw, 4, r0); /* andl $x, r0 */
667	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
668
669	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
670	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
671
672	/* lea offset(r1, env), r1 */
673	tcg_out_modrm_offset2(s, 0x8d \| P_REXW, r1, r1, TCG_AREG0, 0,
674	offsetof(CPUState, tlb_table[mem_index][0].addr_read));
675
676	/* cmp 0(r1), r0 */
677	tcg_out_modrm_offset(s, 0x3b \| rexw, r0, r1, 0);
678
679	/* mov */
680	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
681
682	/* je label1 */
683	tcg_out8(s, 0x70 + JCC_JE);
684	label1_ptr = s->code_ptr;
685	s->code_ptr++;
686
687	/* XXX: move that code at the end of the TB */
688	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
689	#ifndef VBOX
690	tcg_out8(s, 0xe8);
691	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
692	(tcg_target_long)s->code_ptr - 4);
693	#else
694	tcg_out_long_call(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
695	#endif
696
697	switch(opc) {
698	case 0 \| 4:
699	/* movsbq */
700	tcg_out_modrm(s, 0xbe \| P_EXT \| P_REXW, data_reg, TCG_REG_RAX);
701	break;
702	case 1 \| 4:
703	/* movswq */
704	tcg_out_modrm(s, 0xbf \| P_EXT \| P_REXW, data_reg, TCG_REG_RAX);
705	break;
706	case 2 \| 4:
707	/* movslq */
708	tcg_out_modrm(s, 0x63 \| P_REXW, data_reg, TCG_REG_RAX);
709	break;
710	case 0:
711	case 1:
712	case 2:
713	default:
714	/* movl */
715	tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
716	break;
717	case 3:
718	tcg_out_mov(s, data_reg, TCG_REG_RAX);
719	break;
720	}
721
722	/* jmp label2 */
723	tcg_out8(s, 0xeb);
724	label2_ptr = s->code_ptr;
725	s->code_ptr++;
726
727	/* label1: */
728	*label1_ptr = s->code_ptr - label1_ptr - 1;
729
730	/* add x(r1), r0 */
731	tcg_out_modrm_offset(s, 0x03 \| P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
732	offsetof(CPUTLBEntry, addr_read));
733	#else
734	r0 = addr_reg;
735	#endif
736
737	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
738
739	#ifdef TARGET_WORDS_BIGENDIAN
740	bswap = 1;
741	#else
742	bswap = 0;
743	#endif
744
745	switch(opc) {
746	case 0:
747	/* movzbl */
748	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
749	break;
750	case 0 \| 4:
751	/* movsbX */
752	tcg_out_modrm_offset(s, 0xbe \| P_EXT \| rexw, data_reg, r0, 0);
753	break;
754	case 1:
755	/* movzwl */
756	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
757	if (bswap) {
758	/* rolw $8, data_reg */
759	tcg_out8(s, 0x66);
760	tcg_out_modrm(s, 0xc1, 0, data_reg);
761	tcg_out8(s, 8);
762	}
763	break;
764	case 1 \| 4:
765	if (bswap) {
766	/* movzwl */
767	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
768	/* rolw $8, data_reg */
769	tcg_out8(s, 0x66);
770	tcg_out_modrm(s, 0xc1, 0, data_reg);
771	tcg_out8(s, 8);
772
773	/* movswX data_reg, data_reg */
774	tcg_out_modrm(s, 0xbf \| P_EXT \| rexw, data_reg, data_reg);
775	} else {
776	/* movswX */
777	tcg_out_modrm_offset(s, 0xbf \| P_EXT \| rexw, data_reg, r0, 0);
778	}
779	break;
780	case 2:
781	/* movl (r0), data_reg */
782	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
783	if (bswap) {
784	/* bswap */
785	tcg_out_opc(s, (0xc8 + (data_reg & 7)) \| P_EXT, 0, data_reg, 0);
786	}
787	break;
788	case 2 \| 4:
789	if (bswap) {
790	/* movl (r0), data_reg */
791	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
792	/* bswap */
793	tcg_out_opc(s, (0xc8 + (data_reg & 7)) \| P_EXT, 0, data_reg, 0);
794	/* movslq */
795	tcg_out_modrm(s, 0x63 \| P_REXW, data_reg, data_reg);
796	} else {
797	/* movslq */
798	tcg_out_modrm_offset(s, 0x63 \| P_REXW, data_reg, r0, 0);
799	}
800	break;
801	case 3:
802	/* movq (r0), data_reg */
803	tcg_out_modrm_offset(s, 0x8b \| P_REXW, data_reg, r0, 0);
804	if (bswap) {
805	/* bswap */
806	tcg_out_opc(s, (0xc8 + (data_reg & 7)) \| P_EXT \| P_REXW, 0, data_reg, 0);
807	}
808	break;
809	default:
810	tcg_abort();
811	}
812	#else /* VBOX */
813	tcg_out_vbox_phys_read(s, opc, r0, data_reg);
814	#endif /* VBOX */
815
816	#if defined(CONFIG_SOFTMMU)
817	/* label2: */
818	*label2_ptr = s->code_ptr - label2_ptr - 1;
819	#endif
820	}
821
822	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
823	int opc)
824	{
825	int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
826	#if defined(CONFIG_SOFTMMU)
827	uint8_t label1_ptr, label2_ptr;
828	#endif
829
830	data_reg = *args++;
831	addr_reg = *args++;
832	mem_index = *args;
833
834	s_bits = opc;
835
836	r0 = TCG_REG_RDI;
837	r1 = TCG_REG_RSI;
838
839	#if TARGET_LONG_BITS == 32
840	rexw = 0;
841	#else
842	rexw = P_REXW;
843	#endif
844	#if defined(CONFIG_SOFTMMU)
845	/* mov */
846	tcg_out_modrm(s, 0x8b \| rexw, r1, addr_reg);
847
848	/* mov */
849	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
850
851	tcg_out_modrm(s, 0xc1 \| rexw, 5, r1); /* shr $x, r1 */
852	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
853
854	tcg_out_modrm(s, 0x81 \| rexw, 4, r0); /* andl $x, r0 */
855	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
856
857	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
858	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
859
860	/* lea offset(r1, env), r1 */
861	tcg_out_modrm_offset2(s, 0x8d \| P_REXW, r1, r1, TCG_AREG0, 0,
862	offsetof(CPUState, tlb_table[mem_index][0].addr_write));
863
864	/* cmp 0(r1), r0 */
865	tcg_out_modrm_offset(s, 0x3b \| rexw, r0, r1, 0);
866
867	/* mov */
868	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
869
870	/* je label1 */
871	tcg_out8(s, 0x70 + JCC_JE);
872	label1_ptr = s->code_ptr;
873	s->code_ptr++;
874
875	/* XXX: move that code at the end of the TB */
876	switch(opc) {
877	case 0:
878	/* movzbl */
879	tcg_out_modrm(s, 0xb6 \| P_EXT \| P_REXB, TCG_REG_RSI, data_reg);
880	break;
881	case 1:
882	/* movzwl */
883	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_RSI, data_reg);
884	break;
885	case 2:
886	/* movl */
887	tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
888	break;
889	default:
890	case 3:
891	tcg_out_mov(s, TCG_REG_RSI, data_reg);
892	break;
893	}
894	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
895	#ifndef VBOX
896	tcg_out8(s, 0xe8);
897	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
898	(tcg_target_long)s->code_ptr - 4);
899	#else
900	tcg_out_long_call(s, (tcg_target_long)qemu_st_helpers[s_bits]);
901	#endif
902
903	/* jmp label2 */
904	tcg_out8(s, 0xeb);
905	label2_ptr = s->code_ptr;
906	s->code_ptr++;
907
908	/* label1: */
909	*label1_ptr = s->code_ptr - label1_ptr - 1;
910
911	/* add x(r1), r0 */
912	tcg_out_modrm_offset(s, 0x03 \| P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
913	offsetof(CPUTLBEntry, addr_write));
914	#else
915	r0 = addr_reg;
916	#endif
917
918	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
919	#ifdef TARGET_WORDS_BIGENDIAN
920	bswap = 1;
921	#else
922	bswap = 0;
923	#endif
924	switch(opc) {
925	case 0:
926	/* movb */
927	tcg_out_modrm_offset(s, 0x88 \| P_REXB, data_reg, r0, 0);
928	break;
929	case 1:
930	if (bswap) {
931	tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
932	tcg_out8(s, 0x66); /* rolw $8, %ecx */
933	tcg_out_modrm(s, 0xc1, 0, r1);
934	tcg_out8(s, 8);
935	data_reg = r1;
936	}
937	/* movw */
938	tcg_out8(s, 0x66);
939	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
940	break;
941	case 2:
942	if (bswap) {
943	tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
944	/* bswap data_reg */
945	tcg_out_opc(s, (0xc8 + r1) \| P_EXT, 0, r1, 0);
946	data_reg = r1;
947	}
948	/* movl */
949	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
950	break;
951	case 3:
952	if (bswap) {
953	tcg_out_mov(s, r1, data_reg);
954	/* bswap data_reg */
955	tcg_out_opc(s, (0xc8 + r1) \| P_EXT \| P_REXW, 0, r1, 0);
956	data_reg = r1;
957	}
958	/* movq */
959	tcg_out_modrm_offset(s, 0x89 \| P_REXW, data_reg, r0, 0);
960	break;
961	default:
962	tcg_abort();
963	}
964	#else /* VBOX */
965	tcg_out_vbox_phys_write(s, opc, r0, data_reg);
966	#endif /* VBOX */
967
968	#if defined(CONFIG_SOFTMMU)
969	/* label2: */
970	*label2_ptr = s->code_ptr - label2_ptr - 1;
971	#endif
972	}
973
974	static inline void tcg_out_op(TCGContext s, int opc, const TCGArg args,
975	const int *const_args)
976	{
977	int c;
978
979	switch(opc) {
980	case INDEX_op_exit_tb:
981	tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
982	#ifndef VBOX
983	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
984	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
985	#else
986	tcg_out_long_jmp(s, (tcg_target_long)tb_ret_addr);
987	#endif
988	break;
989	case INDEX_op_goto_tb:
990	if (s->tb_jmp_offset) {
991	/* direct jump method */
992	tcg_out8(s, 0xe9); /* jmp im */
993	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
994	tcg_out32(s, 0);
995	} else {
996	/* indirect jump method */
997	/* jmp Ev */
998	#ifndef VBOX
999	tcg_out_modrm_offset(s, 0xff, 4, -1,
1000	(tcg_target_long)(s->tb_next +
1001	args[0]));
1002	#else
1003	/* @todo: can we clobber RAX here? */
1004	tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX,
1005	(tcg_target_long)&(s->tb_next[args[0]]));
1006	tcg_out8(s, 0xff); tcg_out8(s, 0x20 \| TCG_REG_RAX); /* jmp (%rax) /
1007	#endif
1008	}
1009	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1010	break;
1011	case INDEX_op_call:
1012	if (const_args[0]) {
1013	#ifndef VBOX
1014	tcg_out8(s, 0xe8);
1015	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1016	#else
1017	tcg_out_long_call(s, args[0]);
1018	#endif
1019	} else {
1020	tcg_out_modrm(s, 0xff, 2, args[0]);
1021	}
1022	break;
1023	case INDEX_op_jmp:
1024	if (const_args[0]) {
1025	tcg_out8(s, 0xe9);
1026	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1027	} else {
1028	tcg_out_modrm(s, 0xff, 4, args[0]);
1029	}
1030	break;
1031	case INDEX_op_br:
1032	tcg_out_jxx(s, JCC_JMP, args[0]);
1033	break;
1034	case INDEX_op_movi_i32:
1035	tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1036	break;
1037	case INDEX_op_movi_i64:
1038	tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1039	break;
1040	case INDEX_op_ld8u_i32:
1041	case INDEX_op_ld8u_i64:
1042	/* movzbl */
1043	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1044	break;
1045	case INDEX_op_ld8s_i32:
1046	/* movsbl */
1047	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1048	break;
1049	case INDEX_op_ld8s_i64:
1050	/* movsbq */
1051	tcg_out_modrm_offset(s, 0xbe \| P_EXT \| P_REXW, args[0], args[1], args[2]);
1052	break;
1053	case INDEX_op_ld16u_i32:
1054	case INDEX_op_ld16u_i64:
1055	/* movzwl */
1056	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1057	break;
1058	case INDEX_op_ld16s_i32:
1059	/* movswl */
1060	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1061	break;
1062	case INDEX_op_ld16s_i64:
1063	/* movswq */
1064	tcg_out_modrm_offset(s, 0xbf \| P_EXT \| P_REXW, args[0], args[1], args[2]);
1065	break;
1066	case INDEX_op_ld_i32:
1067	case INDEX_op_ld32u_i64:
1068	/* movl */
1069	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1070	break;
1071	case INDEX_op_ld32s_i64:
1072	/* movslq */
1073	tcg_out_modrm_offset(s, 0x63 \| P_REXW, args[0], args[1], args[2]);
1074	break;
1075	case INDEX_op_ld_i64:
1076	/* movq */
1077	tcg_out_modrm_offset(s, 0x8b \| P_REXW, args[0], args[1], args[2]);
1078	break;
1079
1080	case INDEX_op_st8_i32:
1081	case INDEX_op_st8_i64:
1082	/* movb */
1083	tcg_out_modrm_offset(s, 0x88 \| P_REXB, args[0], args[1], args[2]);
1084	break;
1085	case INDEX_op_st16_i32:
1086	case INDEX_op_st16_i64:
1087	/* movw */
1088	tcg_out8(s, 0x66);
1089	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1090	break;
1091	case INDEX_op_st_i32:
1092	case INDEX_op_st32_i64:
1093	/* movl */
1094	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1095	break;
1096	case INDEX_op_st_i64:
1097	/* movq */
1098	tcg_out_modrm_offset(s, 0x89 \| P_REXW, args[0], args[1], args[2]);
1099	break;
1100
1101	case INDEX_op_sub_i32:
1102	c = ARITH_SUB;
1103	goto gen_arith32;
1104	case INDEX_op_and_i32:
1105	c = ARITH_AND;
1106	goto gen_arith32;
1107	case INDEX_op_or_i32:
1108	c = ARITH_OR;
1109	goto gen_arith32;
1110	case INDEX_op_xor_i32:
1111	c = ARITH_XOR;
1112	goto gen_arith32;
1113	case INDEX_op_add_i32:
1114	c = ARITH_ADD;
1115	gen_arith32:
1116	if (const_args[2]) {
1117	tgen_arithi32(s, c, args[0], args[2]);
1118	} else {
1119	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1120	}
1121	break;
1122
1123	case INDEX_op_sub_i64:
1124	c = ARITH_SUB;
1125	goto gen_arith64;
1126	case INDEX_op_and_i64:
1127	c = ARITH_AND;
1128	goto gen_arith64;
1129	case INDEX_op_or_i64:
1130	c = ARITH_OR;
1131	goto gen_arith64;
1132	case INDEX_op_xor_i64:
1133	c = ARITH_XOR;
1134	goto gen_arith64;
1135	case INDEX_op_add_i64:
1136	c = ARITH_ADD;
1137	gen_arith64:
1138	if (const_args[2]) {
1139	tgen_arithi64(s, c, args[0], args[2]);
1140	} else {
1141	tcg_out_modrm(s, 0x01 \| (c << 3) \| P_REXW, args[2], args[0]);
1142	}
1143	break;
1144
1145	case INDEX_op_mul_i32:
1146	if (const_args[2]) {
1147	int32_t val;
1148	val = args[2];
1149	if (val == (int8_t)val) {
1150	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1151	tcg_out8(s, val);
1152	} else {
1153	tcg_out_modrm(s, 0x69, args[0], args[0]);
1154	tcg_out32(s, val);
1155	}
1156	} else {
1157	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1158	}
1159	break;
1160	case INDEX_op_mul_i64:
1161	if (const_args[2]) {
1162	int32_t val;
1163	val = args[2];
1164	if (val == (int8_t)val) {
1165	tcg_out_modrm(s, 0x6b \| P_REXW, args[0], args[0]);
1166	tcg_out8(s, val);
1167	} else {
1168	tcg_out_modrm(s, 0x69 \| P_REXW, args[0], args[0]);
1169	tcg_out32(s, val);
1170	}
1171	} else {
1172	tcg_out_modrm(s, 0xaf \| P_EXT \| P_REXW, args[0], args[2]);
1173	}
1174	break;
1175	case INDEX_op_div2_i32:
1176	tcg_out_modrm(s, 0xf7, 7, args[4]);
1177	break;
1178	case INDEX_op_divu2_i32:
1179	tcg_out_modrm(s, 0xf7, 6, args[4]);
1180	break;
1181	case INDEX_op_div2_i64:
1182	tcg_out_modrm(s, 0xf7 \| P_REXW, 7, args[4]);
1183	break;
1184	case INDEX_op_divu2_i64:
1185	tcg_out_modrm(s, 0xf7 \| P_REXW, 6, args[4]);
1186	break;
1187
1188	case INDEX_op_shl_i32:
1189	c = SHIFT_SHL;
1190	gen_shift32:
1191	if (const_args[2]) {
1192	if (args[2] == 1) {
1193	tcg_out_modrm(s, 0xd1, c, args[0]);
1194	} else {
1195	tcg_out_modrm(s, 0xc1, c, args[0]);
1196	tcg_out8(s, args[2]);
1197	}
1198	} else {
1199	tcg_out_modrm(s, 0xd3, c, args[0]);
1200	}
1201	break;
1202	case INDEX_op_shr_i32:
1203	c = SHIFT_SHR;
1204	goto gen_shift32;
1205	case INDEX_op_sar_i32:
1206	c = SHIFT_SAR;
1207	goto gen_shift32;
1208
1209	case INDEX_op_shl_i64:
1210	c = SHIFT_SHL;
1211	gen_shift64:
1212	if (const_args[2]) {
1213	if (args[2] == 1) {
1214	tcg_out_modrm(s, 0xd1 \| P_REXW, c, args[0]);
1215	} else {
1216	tcg_out_modrm(s, 0xc1 \| P_REXW, c, args[0]);
1217	tcg_out8(s, args[2]);
1218	}
1219	} else {
1220	tcg_out_modrm(s, 0xd3 \| P_REXW, c, args[0]);
1221	}
1222	break;
1223	case INDEX_op_shr_i64:
1224	c = SHIFT_SHR;
1225	goto gen_shift64;
1226	case INDEX_op_sar_i64:
1227	c = SHIFT_SAR;
1228	goto gen_shift64;
1229
1230	case INDEX_op_brcond_i32:
1231	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1232	args[3], 0);
1233	break;
1234	case INDEX_op_brcond_i64:
1235	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1236	args[3], P_REXW);
1237	break;
1238
1239	case INDEX_op_bswap_i32:
1240	tcg_out_opc(s, (0xc8 + (args[0] & 7)) \| P_EXT, 0, args[0], 0);
1241	break;
1242	case INDEX_op_bswap_i64:
1243	tcg_out_opc(s, (0xc8 + (args[0] & 7)) \| P_EXT \| P_REXW, 0, args[0], 0);
1244	break;
1245
1246	case INDEX_op_neg_i32:
1247	tcg_out_modrm(s, 0xf7, 3, args[0]);
1248	break;
1249	case INDEX_op_neg_i64:
1250	tcg_out_modrm(s, 0xf7 \| P_REXW, 3, args[0]);
1251	break;
1252
1253	case INDEX_op_ext8s_i32:
1254	tcg_out_modrm(s, 0xbe \| P_EXT \| P_REXB, args[0], args[1]);
1255	break;
1256	case INDEX_op_ext16s_i32:
1257	tcg_out_modrm(s, 0xbf \| P_EXT, args[0], args[1]);
1258	break;
1259	case INDEX_op_ext8s_i64:
1260	tcg_out_modrm(s, 0xbe \| P_EXT \| P_REXW, args[0], args[1]);
1261	break;
1262	case INDEX_op_ext16s_i64:
1263	tcg_out_modrm(s, 0xbf \| P_EXT \| P_REXW, args[0], args[1]);
1264	break;
1265	case INDEX_op_ext32s_i64:
1266	tcg_out_modrm(s, 0x63 \| P_REXW, args[0], args[1]);
1267	break;
1268
1269	case INDEX_op_qemu_ld8u:
1270	tcg_out_qemu_ld(s, args, 0);
1271	break;
1272	case INDEX_op_qemu_ld8s:
1273	tcg_out_qemu_ld(s, args, 0 \| 4);
1274	break;
1275	case INDEX_op_qemu_ld16u:
1276	tcg_out_qemu_ld(s, args, 1);
1277	break;
1278	case INDEX_op_qemu_ld16s:
1279	tcg_out_qemu_ld(s, args, 1 \| 4);
1280	break;
1281	case INDEX_op_qemu_ld32u:
1282	tcg_out_qemu_ld(s, args, 2);
1283	break;
1284	case INDEX_op_qemu_ld32s:
1285	tcg_out_qemu_ld(s, args, 2 \| 4);
1286	break;
1287	case INDEX_op_qemu_ld64:
1288	tcg_out_qemu_ld(s, args, 3);
1289	break;
1290
1291	case INDEX_op_qemu_st8:
1292	tcg_out_qemu_st(s, args, 0);
1293	break;
1294	case INDEX_op_qemu_st16:
1295	tcg_out_qemu_st(s, args, 1);
1296	break;
1297	case INDEX_op_qemu_st32:
1298	tcg_out_qemu_st(s, args, 2);
1299	break;
1300	case INDEX_op_qemu_st64:
1301	tcg_out_qemu_st(s, args, 3);
1302	break;
1303
1304	default:
1305	tcg_abort();
1306	}
1307	}
1308
1309	static int tcg_target_callee_save_regs[] = {
1310	TCG_REG_RBP,
1311	TCG_REG_RBX,
1312	TCG_REG_R12,
1313	TCG_REG_R13,
1314	/* TCG_REG_R14, / / currently used for the global env, so no
1315	need to save */
1316	TCG_REG_R15,
1317	};
1318
1319	/* Generate global QEMU prologue and epilogue code */
1320	void tcg_target_qemu_prologue(TCGContext *s)
1321	{
1322	int i, frame_size, push_size, stack_addend;
1323
1324	/* TB prologue */
1325	/* save all callee saved registers */
1326	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1327	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1328
1329	}
1330	/* reserve some stack space */
1331	push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1332	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1333	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1334	~(TCG_TARGET_STACK_ALIGN - 1);
1335	stack_addend = frame_size - push_size;
1336	tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1337
1338	tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp %rdi /
1339
1340	/* TB epilogue */
1341	tb_ret_addr = s->code_ptr;
1342	tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1343	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1344	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1345	}
1346	tcg_out8(s, 0xc3); /* ret */
1347	}
1348
1349	static const TCGTargetOpDef x86_64_op_defs[] = {
1350	{ INDEX_op_exit_tb, { } },
1351	{ INDEX_op_goto_tb, { } },
1352	{ INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1353	{ INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1354	{ INDEX_op_br, { } },
1355
1356	{ INDEX_op_mov_i32, { "r", "r" } },
1357	{ INDEX_op_movi_i32, { "r" } },
1358	{ INDEX_op_ld8u_i32, { "r", "r" } },
1359	{ INDEX_op_ld8s_i32, { "r", "r" } },
1360	{ INDEX_op_ld16u_i32, { "r", "r" } },
1361	{ INDEX_op_ld16s_i32, { "r", "r" } },
1362	{ INDEX_op_ld_i32, { "r", "r" } },
1363	{ INDEX_op_st8_i32, { "r", "r" } },
1364	{ INDEX_op_st16_i32, { "r", "r" } },
1365	{ INDEX_op_st_i32, { "r", "r" } },
1366
1367	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1368	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1369	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1370	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1371	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1372	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1373	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1374	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1375
1376	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1377	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1378	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1379
1380	{ INDEX_op_brcond_i32, { "r", "ri" } },
1381
1382	{ INDEX_op_mov_i64, { "r", "r" } },
1383	{ INDEX_op_movi_i64, { "r" } },
1384	{ INDEX_op_ld8u_i64, { "r", "r" } },
1385	{ INDEX_op_ld8s_i64, { "r", "r" } },
1386	{ INDEX_op_ld16u_i64, { "r", "r" } },
1387	{ INDEX_op_ld16s_i64, { "r", "r" } },
1388	{ INDEX_op_ld32u_i64, { "r", "r" } },
1389	{ INDEX_op_ld32s_i64, { "r", "r" } },
1390	{ INDEX_op_ld_i64, { "r", "r" } },
1391	{ INDEX_op_st8_i64, { "r", "r" } },
1392	{ INDEX_op_st16_i64, { "r", "r" } },
1393	{ INDEX_op_st32_i64, { "r", "r" } },
1394	{ INDEX_op_st_i64, { "r", "r" } },
1395
1396	{ INDEX_op_add_i64, { "r", "0", "re" } },
1397	{ INDEX_op_mul_i64, { "r", "0", "re" } },
1398	{ INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1399	{ INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1400	{ INDEX_op_sub_i64, { "r", "0", "re" } },
1401	{ INDEX_op_and_i64, { "r", "0", "reZ" } },
1402	{ INDEX_op_or_i64, { "r", "0", "re" } },
1403	{ INDEX_op_xor_i64, { "r", "0", "re" } },
1404
1405	{ INDEX_op_shl_i64, { "r", "0", "ci" } },
1406	{ INDEX_op_shr_i64, { "r", "0", "ci" } },
1407	{ INDEX_op_sar_i64, { "r", "0", "ci" } },
1408
1409	{ INDEX_op_brcond_i64, { "r", "re" } },
1410
1411	{ INDEX_op_bswap_i32, { "r", "0" } },
1412	{ INDEX_op_bswap_i64, { "r", "0" } },
1413
1414	{ INDEX_op_neg_i32, { "r", "0" } },
1415	{ INDEX_op_neg_i64, { "r", "0" } },
1416
1417	{ INDEX_op_ext8s_i32, { "r", "r"} },
1418	{ INDEX_op_ext16s_i32, { "r", "r"} },
1419	{ INDEX_op_ext8s_i64, { "r", "r"} },
1420	{ INDEX_op_ext16s_i64, { "r", "r"} },
1421	{ INDEX_op_ext32s_i64, { "r", "r"} },
1422
1423	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1424	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1425	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1426	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1427	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1428	{ INDEX_op_qemu_ld32s, { "r", "L" } },
1429	{ INDEX_op_qemu_ld64, { "r", "L" } },
1430
1431	{ INDEX_op_qemu_st8, { "L", "L" } },
1432	{ INDEX_op_qemu_st16, { "L", "L" } },
1433	{ INDEX_op_qemu_st32, { "L", "L" } },
1434	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1435
1436	{ -1 },
1437	};
1438
1439	void tcg_target_init(TCGContext *s)
1440	{
1441	/* fail safe */
1442	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1443	tcg_abort();
1444
1445	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1446	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1447	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1448	(1 << TCG_REG_RDI) \|
1449	(1 << TCG_REG_RSI) \|
1450	(1 << TCG_REG_RDX) \|
1451	(1 << TCG_REG_RCX) \|
1452	(1 << TCG_REG_R8) \|
1453	(1 << TCG_REG_R9) \|
1454	(1 << TCG_REG_RAX) \|
1455	(1 << TCG_REG_R10) \|
1456	(1 << TCG_REG_R11));
1457
1458	tcg_regset_clear(s->reserved_regs);
1459	tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1460
1461	tcg_add_target_add_op_defs(x86_64_op_defs);
1462	}

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source: vbox/trunk/src/recompiler/tcg/x86_64/tcg-target.c@ 33366

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