tcg-target.c@ 36125

Last change on this file since 36125 was 36125, checked in by vboxsync, 14 years ago
recompiler: Removing traces of attempts at making the recompiler compile with the microsoft compiler. (untested)
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1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24
25	#ifndef NDEBUG
26	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27	"%rax",
28	"%rcx",
29	"%rdx",
30	"%rbx",
31	"%rsp",
32	"%rbp",
33	"%rsi",
34	"%rdi",
35	"%r8",
36	"%r9",
37	"%r10",
38	"%r11",
39	"%r12",
40	"%r13",
41	"%r14",
42	"%r15",
43	};
44	#endif
45
46	static const int tcg_target_reg_alloc_order[] = {
47	TCG_REG_RDI,
48	TCG_REG_RSI,
49	TCG_REG_RDX,
50	TCG_REG_RCX,
51	TCG_REG_R8,
52	TCG_REG_R9,
53	TCG_REG_RAX,
54	TCG_REG_R10,
55	TCG_REG_R11,
56
57	TCG_REG_RBP,
58	TCG_REG_RBX,
59	TCG_REG_R12,
60	TCG_REG_R13,
61	TCG_REG_R14,
62	TCG_REG_R15,
63	};
64
65	static const int tcg_target_call_iarg_regs[6] = {
66	TCG_REG_RDI,
67	TCG_REG_RSI,
68	TCG_REG_RDX,
69	TCG_REG_RCX,
70	TCG_REG_R8,
71	TCG_REG_R9,
72	};
73
74	static const int tcg_target_call_oarg_regs[2] = {
75	TCG_REG_RAX,
76	TCG_REG_RDX
77	};
78
79	static uint8_t *tb_ret_addr;
80
81	static void patch_reloc(uint8_t *code_ptr, int type,
82	tcg_target_long value, tcg_target_long addend)
83	{
84	value += addend;
85	switch(type) {
86	case R_X86_64_32:
87	if (value != (uint32_t)value)
88	tcg_abort();
89	(uint32_t )code_ptr = value;
90	break;
91	case R_X86_64_32S:
92	if (value != (int32_t)value)
93	tcg_abort();
94	(uint32_t )code_ptr = value;
95	break;
96	case R_386_PC32:
97	value -= (long)code_ptr;
98	if (value != (int32_t)value)
99	tcg_abort();
100	(uint32_t )code_ptr = value;
101	break;
102	default:
103	tcg_abort();
104	}
105	}
106
107	/* maximum number of register used for input function arguments */
108	static inline int tcg_target_get_call_iarg_regs_count(int flags)
109	{
110	return 6;
111	}
112
113	/* parse target specific constraints */
114	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
115	{
116	const char *ct_str;
117
118	ct_str = *pct_str;
119	switch(ct_str[0]) {
120	case 'a':
121	ct->ct \|= TCG_CT_REG;
122	tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
123	break;
124	case 'b':
125	ct->ct \|= TCG_CT_REG;
126	tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
127	break;
128	case 'c':
129	ct->ct \|= TCG_CT_REG;
130	tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
131	break;
132	case 'd':
133	ct->ct \|= TCG_CT_REG;
134	tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
135	break;
136	case 'S':
137	ct->ct \|= TCG_CT_REG;
138	tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
139	break;
140	case 'D':
141	ct->ct \|= TCG_CT_REG;
142	tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
143	break;
144	case 'q':
145	ct->ct \|= TCG_CT_REG;
146	tcg_regset_set32(ct->u.regs, 0, 0xf);
147	break;
148	case 'r':
149	ct->ct \|= TCG_CT_REG;
150	tcg_regset_set32(ct->u.regs, 0, 0xffff);
151	break;
152	case 'L': /* qemu_ld/st constraint */
153	ct->ct \|= TCG_CT_REG;
154	tcg_regset_set32(ct->u.regs, 0, 0xffff);
155	tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
156	tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
157	break;
158	case 'e':
159	ct->ct \|= TCG_CT_CONST_S32;
160	break;
161	case 'Z':
162	ct->ct \|= TCG_CT_CONST_U32;
163	break;
164	default:
165	return -1;
166	}
167	ct_str++;
168	*pct_str = ct_str;
169	return 0;
170	}
171
172	/* test if a constant matches the constraint */
173	static inline int tcg_target_const_match(tcg_target_long val,
174	const TCGArgConstraint *arg_ct)
175	{
176	int ct;
177	ct = arg_ct->ct;
178	if (ct & TCG_CT_CONST)
179	return 1;
180	else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
181	return 1;
182	else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
183	return 1;
184	else
185	return 0;
186	}
187
188	#define ARITH_ADD 0
189	#define ARITH_OR 1
190	#define ARITH_ADC 2
191	#define ARITH_SBB 3
192	#define ARITH_AND 4
193	#define ARITH_SUB 5
194	#define ARITH_XOR 6
195	#define ARITH_CMP 7
196
197	#define SHIFT_SHL 4
198	#define SHIFT_SHR 5
199	#define SHIFT_SAR 7
200
201	#define JCC_JMP (-1)
202	#define JCC_JO 0x0
203	#define JCC_JNO 0x1
204	#define JCC_JB 0x2
205	#define JCC_JAE 0x3
206	#define JCC_JE 0x4
207	#define JCC_JNE 0x5
208	#define JCC_JBE 0x6
209	#define JCC_JA 0x7
210	#define JCC_JS 0x8
211	#define JCC_JNS 0x9
212	#define JCC_JP 0xa
213	#define JCC_JNP 0xb
214	#define JCC_JL 0xc
215	#define JCC_JGE 0xd
216	#define JCC_JLE 0xe
217	#define JCC_JG 0xf
218
219	#define P_EXT 0x100 /* 0x0f opcode prefix */
220	#define P_REXW 0x200 /* set rex.w = 1 */
221	#define P_REXB 0x400 /* force rex use for byte registers */
222
223	static const uint8_t tcg_cond_to_jcc[10] = {
224	[TCG_COND_EQ] = JCC_JE,
225	[TCG_COND_NE] = JCC_JNE,
226	[TCG_COND_LT] = JCC_JL,
227	[TCG_COND_GE] = JCC_JGE,
228	[TCG_COND_LE] = JCC_JLE,
229	[TCG_COND_GT] = JCC_JG,
230	[TCG_COND_LTU] = JCC_JB,
231	[TCG_COND_GEU] = JCC_JAE,
232	[TCG_COND_LEU] = JCC_JBE,
233	[TCG_COND_GTU] = JCC_JA,
234	};
235
236	static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
237	{
238	int rex;
239	rex = ((opc >> 6) & 0x8) \| ((r >> 1) & 0x4) \|
240	((x >> 2) & 2) \| ((rm >> 3) & 1);
241	if (rex \|\| (opc & P_REXB)) {
242	tcg_out8(s, rex \| 0x40);
243	}
244	if (opc & P_EXT)
245	tcg_out8(s, 0x0f);
246	tcg_out8(s, opc);
247	}
248
249	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
250	{
251	tcg_out_opc(s, opc, r, rm, 0);
252	tcg_out8(s, 0xc0 \| ((r & 7) << 3) \| (rm & 7));
253	}
254
255	static inline void tcg_out_push(TCGContext *s, int reg)
256	{
257	tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
258	}
259
260	static inline void tcg_out_pop(TCGContext *s, int reg)
261	{
262	tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
263	}
264
265
266	/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
267	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
268	tcg_target_long offset)
269	{
270	if (rm < 0) {
271	tcg_target_long val;
272	tcg_out_opc(s, opc, r, 0, 0);
273	val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
274	if (val == (int32_t)val) {
275	/* eip relative */
276	tcg_out8(s, 0x05 \| ((r & 7) << 3));
277	tcg_out32(s, val);
278	} else if (offset == (int32_t)offset) {
279	tcg_out8(s, 0x04 \| ((r & 7) << 3));
280	tcg_out8(s, 0x25); /* sib */
281	tcg_out32(s, offset);
282	} else {
283	tcg_abort();
284	}
285	} else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
286	tcg_out_opc(s, opc, r, rm, 0);
287	if ((rm & 7) == TCG_REG_RSP) {
288	tcg_out8(s, 0x04 \| ((r & 7) << 3));
289	tcg_out8(s, 0x24);
290	} else {
291	tcg_out8(s, 0x00 \| ((r & 7) << 3) \| (rm & 7));
292	}
293	} else if ((int8_t)offset == offset) {
294	tcg_out_opc(s, opc, r, rm, 0);
295	if ((rm & 7) == TCG_REG_RSP) {
296	tcg_out8(s, 0x44 \| ((r & 7) << 3));
297	tcg_out8(s, 0x24);
298	} else {
299	tcg_out8(s, 0x40 \| ((r & 7) << 3) \| (rm & 7));
300	}
301	tcg_out8(s, offset);
302	} else {
303	tcg_out_opc(s, opc, r, rm, 0);
304	if ((rm & 7) == TCG_REG_RSP) {
305	tcg_out8(s, 0x84 \| ((r & 7) << 3));
306	tcg_out8(s, 0x24);
307	} else {
308	tcg_out8(s, 0x80 \| ((r & 7) << 3) \| (rm & 7));
309	}
310	tcg_out32(s, offset);
311	}
312	}
313
314	#if defined(CONFIG_SOFTMMU)
315	/* XXX: incomplete. index must be different from ESP */
316	static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
317	int index, int shift,
318	tcg_target_long offset)
319	{
320	int mod;
321	if (rm == -1)
322	tcg_abort();
323	if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
324	mod = 0;
325	} else if (offset == (int8_t)offset) {
326	mod = 0x40;
327	} else if (offset == (int32_t)offset) {
328	mod = 0x80;
329	} else {
330	tcg_abort();
331	}
332	if (index == -1) {
333	tcg_out_opc(s, opc, r, rm, 0);
334	if ((rm & 7) == TCG_REG_RSP) {
335	tcg_out8(s, mod \| ((r & 7) << 3) \| 0x04);
336	tcg_out8(s, 0x04 \| (rm & 7));
337	} else {
338	tcg_out8(s, mod \| ((r & 7) << 3) \| (rm & 7));
339	}
340	} else {
341	tcg_out_opc(s, opc, r, rm, index);
342	tcg_out8(s, mod \| ((r & 7) << 3) \| 0x04);
343	tcg_out8(s, (shift << 6) \| ((index & 7) << 3) \| (rm & 7));
344	}
345	if (mod == 0x40) {
346	tcg_out8(s, offset);
347	} else if (mod == 0x80) {
348	tcg_out32(s, offset);
349	}
350	}
351	#endif
352
353	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
354	{
355	tcg_out_modrm(s, 0x8b \| P_REXW, ret, arg);
356	}
357
358	static inline void tcg_out_movi(TCGContext *s, TCGType type,
359	int ret, tcg_target_long arg)
360	{
361	if (arg == 0) {
362	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
363	} else if (arg == (uint32_t)arg \|\| type == TCG_TYPE_I32) {
364	tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
365	tcg_out32(s, arg);
366	} else if (arg == (int32_t)arg) {
367	tcg_out_modrm(s, 0xc7 \| P_REXW, 0, ret);
368	tcg_out32(s, arg);
369	} else {
370	tcg_out_opc(s, (0xb8 + (ret & 7)) \| P_REXW, 0, ret, 0);
371	tcg_out32(s, arg);
372	tcg_out32(s, arg >> 32);
373	}
374	}
375
376	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
377	int arg1, tcg_target_long arg2)
378	{
379	if (type == TCG_TYPE_I32)
380	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
381	else
382	tcg_out_modrm_offset(s, 0x8b \| P_REXW, ret, arg1, arg2); /* movq */
383	}
384
385	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
386	int arg1, tcg_target_long arg2)
387	{
388	if (type == TCG_TYPE_I32)
389	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
390	else
391	tcg_out_modrm_offset(s, 0x89 \| P_REXW, arg, arg1, arg2); /* movq */
392	}
393
394	static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
395	{
396	if (val == (int8_t)val) {
397	tcg_out_modrm(s, 0x83, c, r0);
398	tcg_out8(s, val);
399	} else if (c == ARITH_AND && val == 0xffu) {
400	/* movzbl */
401	tcg_out_modrm(s, 0xb6 \| P_EXT \| P_REXB, r0, r0);
402	} else if (c == ARITH_AND && val == 0xffffu) {
403	/* movzwl */
404	tcg_out_modrm(s, 0xb7 \| P_EXT, r0, r0);
405	} else {
406	tcg_out_modrm(s, 0x81, c, r0);
407	tcg_out32(s, val);
408	}
409	}
410
411	static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
412	{
413	if (val == (int8_t)val) {
414	tcg_out_modrm(s, 0x83 \| P_REXW, c, r0);
415	tcg_out8(s, val);
416	} else if (c == ARITH_AND && val == 0xffu) {
417	/* movzbl */
418	tcg_out_modrm(s, 0xb6 \| P_EXT \| P_REXW, r0, r0);
419	} else if (c == ARITH_AND && val == 0xffffu) {
420	/* movzwl */
421	tcg_out_modrm(s, 0xb7 \| P_EXT \| P_REXW, r0, r0);
422	} else if (c == ARITH_AND && val == 0xffffffffu) {
423	/* 32-bit mov zero extends */
424	tcg_out_modrm(s, 0x8b, r0, r0);
425	} else if (val == (int32_t)val) {
426	tcg_out_modrm(s, 0x81 \| P_REXW, c, r0);
427	tcg_out32(s, val);
428	} else if (c == ARITH_AND && val == (uint32_t)val) {
429	tcg_out_modrm(s, 0x81, c, r0);
430	tcg_out32(s, val);
431	} else {
432	tcg_abort();
433	}
434	}
435
436	static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
437	{
438	if (val != 0)
439	tgen_arithi64(s, ARITH_ADD, reg, val);
440	}
441
442	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
443	{
444	int32_t val, val1;
445	TCGLabel *l = &s->labels[label_index];
446
447	if (l->has_value) {
448	val = l->u.value - (tcg_target_long)s->code_ptr;
449	val1 = val - 2;
450	if ((int8_t)val1 == val1) {
451	if (opc == -1)
452	tcg_out8(s, 0xeb);
453	else
454	tcg_out8(s, 0x70 + opc);
455	tcg_out8(s, val1);
456	} else {
457	if (opc == -1) {
458	tcg_out8(s, 0xe9);
459	tcg_out32(s, val - 5);
460	} else {
461	tcg_out8(s, 0x0f);
462	tcg_out8(s, 0x80 + opc);
463	tcg_out32(s, val - 6);
464	}
465	}
466	} else {
467	if (opc == -1) {
468	tcg_out8(s, 0xe9);
469	} else {
470	tcg_out8(s, 0x0f);
471	tcg_out8(s, 0x80 + opc);
472	}
473	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
474	s->code_ptr += 4;
475	}
476	}
477
478	static void tcg_out_brcond(TCGContext *s, int cond,
479	TCGArg arg1, TCGArg arg2, int const_arg2,
480	int label_index, int rexw)
481	{
482	if (const_arg2) {
483	if (arg2 == 0) {
484	/* test r, r */
485	tcg_out_modrm(s, 0x85 \| rexw, arg1, arg1);
486	} else {
487	if (rexw)
488	tgen_arithi64(s, ARITH_CMP, arg1, arg2);
489	else
490	tgen_arithi32(s, ARITH_CMP, arg1, arg2);
491	}
492	} else {
493	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3) \| rexw, arg2, arg1);
494	}
495	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
496	}
497
498	#ifdef VBOX
499
500	DECLINLINE(void) tcg_out_pushq(TCGContext *s, tcg_target_long val)
501	{
502	tcg_out8(s, 0x68); /* push imm32, subs 8 from rsp */
503	tcg_out32(s, val); /* imm32 */
504	if ((val >> 32) != 0)
505	{
506	tcg_out8(s, 0xc7); /* mov imm32, 4(%rsp) */
507	tcg_out8(s, 0x44);
508	tcg_out8(s, 0x24);
509	tcg_out8(s, 0x04);
510	tcg_out32(s, ((uint64_t)val) >> 32); /* imm32 */
511	}
512	}
513
514	DECLINLINE(void) tcg_out_long_call(TCGContext *s, tcg_target_long dst)
515	{
516	intptr_t disp = dst - (tcg_target_long)s->code_ptr - 5;
517	/* can do normal call */
518	if (disp < 2LL * _1G && disp > -2LL * _1G)
519	{
520	tcg_out8(s, 0xe8); /* call disp32 */
521	tcg_out32(s, disp); /* disp32 */
522	}
523	else
524	{
525	# if 0
526	/* Somewhat tricky, but allows long jump not touching registers */
527	int off = 5 /* push imm32 / + 5 / push imm32 / + 1 / ret */;
528	if ((((uint64_t)s->code_ptr) + 32) >> 32)
529	off += 8;
530	if (dst >> 32)
531	off += 8;
532	/* return address */
533	tcg_out_pushq(s, (tcg_target_long)s->code_ptr+off);
534	/* destination */
535	tcg_out_pushq(s, dst);
536	tcg_out8(s, 0xc3); /* ret, used as call */
537	# else
538	tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
539	tcg_out8(s, 0xff); /* call %eax /
540	tcg_out8(s, 0xd0);
541	# endif
542	}
543	}
544
545	DECLINLINE(void) tcg_out_long_jmp(TCGContext *s, tcg_target_long dst)
546	{
547	intptr_t disp;
548
549	disp = dst - (tcg_target_long)s->code_ptr - 2;
550	/* can do short relative jump */
551	if (disp < 0x7f && disp > -0x7f)
552	{
553	tcg_out8(s, 0xeb); /* short jmp */
554	tcg_out8(s, (int8_t)disp);
555	return;
556	}
557
558	disp = dst - (tcg_target_long)s->code_ptr - 5;
559	if (disp < 2LL * _1G && disp > -2LL * _1G)
560	{
561	tcg_out8(s, 0xe9); /* jmp */
562	tcg_out32(s, (int32_t)disp);
563	return;
564	}
565	# if 0
566	tcg_out_pushq(s, dst);
567	tcg_out8(s, 0xc3); /* ret */
568	# else
569	tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
570	tcg_out8(s, 0xff); /* jmp %eax /
571	tcg_out8(s, 0xe0);
572	# endif
573	}
574
575	#endif /* VBOX */
576
577	#if defined(CONFIG_SOFTMMU)
578
579	#include "../../softmmu_defs.h"
580
581	static void *qemu_ld_helpers[4] = {
582	__ldb_mmu,
583	__ldw_mmu,
584	__ldl_mmu,
585	__ldq_mmu,
586	};
587
588	static void *qemu_st_helpers[4] = {
589	__stb_mmu,
590	__stw_mmu,
591	__stl_mmu,
592	__stq_mmu,
593	};
594	#endif
595
596	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
597	static void *vbox_ld_helpers[] = {
598	__ldub_vbox_phys,
599	__lduw_vbox_phys,
600	__ldul_vbox_phys,
601	__ldq_vbox_phys,
602	__ldb_vbox_phys,
603	__ldw_vbox_phys,
604	__ldl_vbox_phys,
605	__ldq_vbox_phys,
606	};
607
608	static void *vbox_st_helpers[] = {
609	__stb_vbox_phys,
610	__stw_vbox_phys,
611	__stl_vbox_phys,
612	__stq_vbox_phys
613	};
614
615	static void tcg_out_vbox_phys_read(TCGContext *s, int index, int addr_reg, int data_reg) {
616	if (addr_reg != TCG_REG_RDI)
617	/* mov addr_reg, %rdi */
618	tcg_out_modrm(s, 0x8b \| P_REXW, TCG_REG_RDI, addr_reg);
619
620	tcg_out_long_call(s, (tcg_target_long)vbox_ld_helpers[index]);
621	/* mov %rax, data_reg*/
622	tcg_out_modrm(s, 0x8b \| P_REXW, data_reg, TCG_REG_RAX);
623	}
624
625	static void tcg_out_vbox_phys_write(TCGContext *s, int index, int addr_reg, int val_reg) {
626	if (addr_reg != TCG_REG_RDI)
627	/* mov addr_reg, %rdi */
628	tcg_out_modrm(s, 0x8b \| P_REXW, TCG_REG_RDI, addr_reg);
629	if (val_reg != TCG_REG_RSI)
630	/* mov addr_reg, %rsi */
631	tcg_out_modrm(s, 0x8b \| P_REXW, TCG_REG_RSI, val_reg);
632	tcg_out_long_call(s, (tcg_target_long)vbox_st_helpers[index]);
633	}
634
635	#endif
636
637	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
638	int opc)
639	{
640	int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
641	#if defined(CONFIG_SOFTMMU)
642	uint8_t label1_ptr, label2_ptr;
643	#endif
644
645	data_reg = *args++;
646	addr_reg = *args++;
647	mem_index = *args;
648	s_bits = opc & 3;
649
650	r0 = TCG_REG_RDI;
651	r1 = TCG_REG_RSI;
652
653	#if TARGET_LONG_BITS == 32
654	rexw = 0;
655	#else
656	rexw = P_REXW;
657	#endif
658	#if defined(CONFIG_SOFTMMU)
659	/* mov */
660	tcg_out_modrm(s, 0x8b \| rexw, r1, addr_reg);
661
662	/* mov */
663	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
664
665	tcg_out_modrm(s, 0xc1 \| rexw, 5, r1); /* shr $x, r1 */
666	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
667
668	tcg_out_modrm(s, 0x81 \| rexw, 4, r0); /* andl $x, r0 */
669	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
670
671	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
672	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
673
674	/* lea offset(r1, env), r1 */
675	tcg_out_modrm_offset2(s, 0x8d \| P_REXW, r1, r1, TCG_AREG0, 0,
676	offsetof(CPUState, tlb_table[mem_index][0].addr_read));
677
678	/* cmp 0(r1), r0 */
679	tcg_out_modrm_offset(s, 0x3b \| rexw, r0, r1, 0);
680
681	/* mov */
682	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
683
684	/* je label1 */
685	tcg_out8(s, 0x70 + JCC_JE);
686	label1_ptr = s->code_ptr;
687	s->code_ptr++;
688
689	/* XXX: move that code at the end of the TB */
690	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
691	#ifndef VBOX
692	tcg_out8(s, 0xe8);
693	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
694	(tcg_target_long)s->code_ptr - 4);
695	#else
696	tcg_out_long_call(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
697	#endif
698
699	switch(opc) {
700	case 0 \| 4:
701	/* movsbq */
702	tcg_out_modrm(s, 0xbe \| P_EXT \| P_REXW, data_reg, TCG_REG_RAX);
703	break;
704	case 1 \| 4:
705	/* movswq */
706	tcg_out_modrm(s, 0xbf \| P_EXT \| P_REXW, data_reg, TCG_REG_RAX);
707	break;
708	case 2 \| 4:
709	/* movslq */
710	tcg_out_modrm(s, 0x63 \| P_REXW, data_reg, TCG_REG_RAX);
711	break;
712	case 0:
713	case 1:
714	case 2:
715	default:
716	/* movl */
717	tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
718	break;
719	case 3:
720	tcg_out_mov(s, data_reg, TCG_REG_RAX);
721	break;
722	}
723
724	/* jmp label2 */
725	tcg_out8(s, 0xeb);
726	label2_ptr = s->code_ptr;
727	s->code_ptr++;
728
729	/* label1: */
730	*label1_ptr = s->code_ptr - label1_ptr - 1;
731
732	/* add x(r1), r0 */
733	tcg_out_modrm_offset(s, 0x03 \| P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
734	offsetof(CPUTLBEntry, addr_read));
735	#else
736	r0 = addr_reg;
737	#endif
738
739	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
740
741	#ifdef TARGET_WORDS_BIGENDIAN
742	bswap = 1;
743	#else
744	bswap = 0;
745	#endif
746
747	switch(opc) {
748	case 0:
749	/* movzbl */
750	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
751	break;
752	case 0 \| 4:
753	/* movsbX */
754	tcg_out_modrm_offset(s, 0xbe \| P_EXT \| rexw, data_reg, r0, 0);
755	break;
756	case 1:
757	/* movzwl */
758	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
759	if (bswap) {
760	/* rolw $8, data_reg */
761	tcg_out8(s, 0x66);
762	tcg_out_modrm(s, 0xc1, 0, data_reg);
763	tcg_out8(s, 8);
764	}
765	break;
766	case 1 \| 4:
767	if (bswap) {
768	/* movzwl */
769	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
770	/* rolw $8, data_reg */
771	tcg_out8(s, 0x66);
772	tcg_out_modrm(s, 0xc1, 0, data_reg);
773	tcg_out8(s, 8);
774
775	/* movswX data_reg, data_reg */
776	tcg_out_modrm(s, 0xbf \| P_EXT \| rexw, data_reg, data_reg);
777	} else {
778	/* movswX */
779	tcg_out_modrm_offset(s, 0xbf \| P_EXT \| rexw, data_reg, r0, 0);
780	}
781	break;
782	case 2:
783	/* movl (r0), data_reg */
784	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
785	if (bswap) {
786	/* bswap */
787	tcg_out_opc(s, (0xc8 + (data_reg & 7)) \| P_EXT, 0, data_reg, 0);
788	}
789	break;
790	case 2 \| 4:
791	if (bswap) {
792	/* movl (r0), data_reg */
793	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
794	/* bswap */
795	tcg_out_opc(s, (0xc8 + (data_reg & 7)) \| P_EXT, 0, data_reg, 0);
796	/* movslq */
797	tcg_out_modrm(s, 0x63 \| P_REXW, data_reg, data_reg);
798	} else {
799	/* movslq */
800	tcg_out_modrm_offset(s, 0x63 \| P_REXW, data_reg, r0, 0);
801	}
802	break;
803	case 3:
804	/* movq (r0), data_reg */
805	tcg_out_modrm_offset(s, 0x8b \| P_REXW, data_reg, r0, 0);
806	if (bswap) {
807	/* bswap */
808	tcg_out_opc(s, (0xc8 + (data_reg & 7)) \| P_EXT \| P_REXW, 0, data_reg, 0);
809	}
810	break;
811	default:
812	tcg_abort();
813	}
814	#else /* VBOX */
815	tcg_out_vbox_phys_read(s, opc, r0, data_reg);
816	#endif /* VBOX */
817
818	#if defined(CONFIG_SOFTMMU)
819	/* label2: */
820	*label2_ptr = s->code_ptr - label2_ptr - 1;
821	#endif
822	}
823
824	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
825	int opc)
826	{
827	int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
828	#if defined(CONFIG_SOFTMMU)
829	uint8_t label1_ptr, label2_ptr;
830	#endif
831
832	data_reg = *args++;
833	addr_reg = *args++;
834	mem_index = *args;
835
836	s_bits = opc;
837
838	r0 = TCG_REG_RDI;
839	r1 = TCG_REG_RSI;
840
841	#if TARGET_LONG_BITS == 32
842	rexw = 0;
843	#else
844	rexw = P_REXW;
845	#endif
846	#if defined(CONFIG_SOFTMMU)
847	/* mov */
848	tcg_out_modrm(s, 0x8b \| rexw, r1, addr_reg);
849
850	/* mov */
851	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
852
853	tcg_out_modrm(s, 0xc1 \| rexw, 5, r1); /* shr $x, r1 */
854	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
855
856	tcg_out_modrm(s, 0x81 \| rexw, 4, r0); /* andl $x, r0 */
857	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
858
859	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
860	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
861
862	/* lea offset(r1, env), r1 */
863	tcg_out_modrm_offset2(s, 0x8d \| P_REXW, r1, r1, TCG_AREG0, 0,
864	offsetof(CPUState, tlb_table[mem_index][0].addr_write));
865
866	/* cmp 0(r1), r0 */
867	tcg_out_modrm_offset(s, 0x3b \| rexw, r0, r1, 0);
868
869	/* mov */
870	tcg_out_modrm(s, 0x8b \| rexw, r0, addr_reg);
871
872	/* je label1 */
873	tcg_out8(s, 0x70 + JCC_JE);
874	label1_ptr = s->code_ptr;
875	s->code_ptr++;
876
877	/* XXX: move that code at the end of the TB */
878	switch(opc) {
879	case 0:
880	/* movzbl */
881	tcg_out_modrm(s, 0xb6 \| P_EXT \| P_REXB, TCG_REG_RSI, data_reg);
882	break;
883	case 1:
884	/* movzwl */
885	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_RSI, data_reg);
886	break;
887	case 2:
888	/* movl */
889	tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
890	break;
891	default:
892	case 3:
893	tcg_out_mov(s, TCG_REG_RSI, data_reg);
894	break;
895	}
896	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
897	#ifndef VBOX
898	tcg_out8(s, 0xe8);
899	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
900	(tcg_target_long)s->code_ptr - 4);
901	#else
902	tcg_out_long_call(s, (tcg_target_long)qemu_st_helpers[s_bits]);
903	#endif
904
905	/* jmp label2 */
906	tcg_out8(s, 0xeb);
907	label2_ptr = s->code_ptr;
908	s->code_ptr++;
909
910	/* label1: */
911	*label1_ptr = s->code_ptr - label1_ptr - 1;
912
913	/* add x(r1), r0 */
914	tcg_out_modrm_offset(s, 0x03 \| P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
915	offsetof(CPUTLBEntry, addr_write));
916	#else
917	r0 = addr_reg;
918	#endif
919
920	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
921	#ifdef TARGET_WORDS_BIGENDIAN
922	bswap = 1;
923	#else
924	bswap = 0;
925	#endif
926	switch(opc) {
927	case 0:
928	/* movb */
929	tcg_out_modrm_offset(s, 0x88 \| P_REXB, data_reg, r0, 0);
930	break;
931	case 1:
932	if (bswap) {
933	tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
934	tcg_out8(s, 0x66); /* rolw $8, %ecx */
935	tcg_out_modrm(s, 0xc1, 0, r1);
936	tcg_out8(s, 8);
937	data_reg = r1;
938	}
939	/* movw */
940	tcg_out8(s, 0x66);
941	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
942	break;
943	case 2:
944	if (bswap) {
945	tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
946	/* bswap data_reg */
947	tcg_out_opc(s, (0xc8 + r1) \| P_EXT, 0, r1, 0);
948	data_reg = r1;
949	}
950	/* movl */
951	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
952	break;
953	case 3:
954	if (bswap) {
955	tcg_out_mov(s, r1, data_reg);
956	/* bswap data_reg */
957	tcg_out_opc(s, (0xc8 + r1) \| P_EXT \| P_REXW, 0, r1, 0);
958	data_reg = r1;
959	}
960	/* movq */
961	tcg_out_modrm_offset(s, 0x89 \| P_REXW, data_reg, r0, 0);
962	break;
963	default:
964	tcg_abort();
965	}
966	#else /* VBOX */
967	tcg_out_vbox_phys_write(s, opc, r0, data_reg);
968	#endif /* VBOX */
969
970	#if defined(CONFIG_SOFTMMU)
971	/* label2: */
972	*label2_ptr = s->code_ptr - label2_ptr - 1;
973	#endif
974	}
975
976	static inline void tcg_out_op(TCGContext s, int opc, const TCGArg args,
977	const int *const_args)
978	{
979	int c;
980
981	switch(opc) {
982	case INDEX_op_exit_tb:
983	tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
984	#ifndef VBOX
985	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
986	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
987	#else
988	tcg_out_long_jmp(s, (tcg_target_long)tb_ret_addr);
989	#endif
990	break;
991	case INDEX_op_goto_tb:
992	if (s->tb_jmp_offset) {
993	/* direct jump method */
994	tcg_out8(s, 0xe9); /* jmp im */
995	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
996	tcg_out32(s, 0);
997	} else {
998	/* indirect jump method */
999	/* jmp Ev */
1000	#ifndef VBOX
1001	tcg_out_modrm_offset(s, 0xff, 4, -1,
1002	(tcg_target_long)(s->tb_next +
1003	args[0]));
1004	#else
1005	/* @todo: can we clobber RAX here? */
1006	tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX,
1007	(tcg_target_long)&(s->tb_next[args[0]]));
1008	tcg_out8(s, 0xff); tcg_out8(s, 0x20 \| TCG_REG_RAX); /* jmp (%rax) /
1009	#endif
1010	}
1011	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1012	break;
1013	case INDEX_op_call:
1014	if (const_args[0]) {
1015	#ifndef VBOX
1016	tcg_out8(s, 0xe8);
1017	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1018	#else
1019	tcg_out_long_call(s, args[0]);
1020	#endif
1021	} else {
1022	tcg_out_modrm(s, 0xff, 2, args[0]);
1023	}
1024	break;
1025	case INDEX_op_jmp:
1026	if (const_args[0]) {
1027	tcg_out8(s, 0xe9);
1028	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1029	} else {
1030	tcg_out_modrm(s, 0xff, 4, args[0]);
1031	}
1032	break;
1033	case INDEX_op_br:
1034	tcg_out_jxx(s, JCC_JMP, args[0]);
1035	break;
1036	case INDEX_op_movi_i32:
1037	tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1038	break;
1039	case INDEX_op_movi_i64:
1040	tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1041	break;
1042	case INDEX_op_ld8u_i32:
1043	case INDEX_op_ld8u_i64:
1044	/* movzbl */
1045	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1046	break;
1047	case INDEX_op_ld8s_i32:
1048	/* movsbl */
1049	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1050	break;
1051	case INDEX_op_ld8s_i64:
1052	/* movsbq */
1053	tcg_out_modrm_offset(s, 0xbe \| P_EXT \| P_REXW, args[0], args[1], args[2]);
1054	break;
1055	case INDEX_op_ld16u_i32:
1056	case INDEX_op_ld16u_i64:
1057	/* movzwl */
1058	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1059	break;
1060	case INDEX_op_ld16s_i32:
1061	/* movswl */
1062	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1063	break;
1064	case INDEX_op_ld16s_i64:
1065	/* movswq */
1066	tcg_out_modrm_offset(s, 0xbf \| P_EXT \| P_REXW, args[0], args[1], args[2]);
1067	break;
1068	case INDEX_op_ld_i32:
1069	case INDEX_op_ld32u_i64:
1070	/* movl */
1071	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1072	break;
1073	case INDEX_op_ld32s_i64:
1074	/* movslq */
1075	tcg_out_modrm_offset(s, 0x63 \| P_REXW, args[0], args[1], args[2]);
1076	break;
1077	case INDEX_op_ld_i64:
1078	/* movq */
1079	tcg_out_modrm_offset(s, 0x8b \| P_REXW, args[0], args[1], args[2]);
1080	break;
1081
1082	case INDEX_op_st8_i32:
1083	case INDEX_op_st8_i64:
1084	/* movb */
1085	tcg_out_modrm_offset(s, 0x88 \| P_REXB, args[0], args[1], args[2]);
1086	break;
1087	case INDEX_op_st16_i32:
1088	case INDEX_op_st16_i64:
1089	/* movw */
1090	tcg_out8(s, 0x66);
1091	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1092	break;
1093	case INDEX_op_st_i32:
1094	case INDEX_op_st32_i64:
1095	/* movl */
1096	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1097	break;
1098	case INDEX_op_st_i64:
1099	/* movq */
1100	tcg_out_modrm_offset(s, 0x89 \| P_REXW, args[0], args[1], args[2]);
1101	break;
1102
1103	case INDEX_op_sub_i32:
1104	c = ARITH_SUB;
1105	goto gen_arith32;
1106	case INDEX_op_and_i32:
1107	c = ARITH_AND;
1108	goto gen_arith32;
1109	case INDEX_op_or_i32:
1110	c = ARITH_OR;
1111	goto gen_arith32;
1112	case INDEX_op_xor_i32:
1113	c = ARITH_XOR;
1114	goto gen_arith32;
1115	case INDEX_op_add_i32:
1116	c = ARITH_ADD;
1117	gen_arith32:
1118	if (const_args[2]) {
1119	tgen_arithi32(s, c, args[0], args[2]);
1120	} else {
1121	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1122	}
1123	break;
1124
1125	case INDEX_op_sub_i64:
1126	c = ARITH_SUB;
1127	goto gen_arith64;
1128	case INDEX_op_and_i64:
1129	c = ARITH_AND;
1130	goto gen_arith64;
1131	case INDEX_op_or_i64:
1132	c = ARITH_OR;
1133	goto gen_arith64;
1134	case INDEX_op_xor_i64:
1135	c = ARITH_XOR;
1136	goto gen_arith64;
1137	case INDEX_op_add_i64:
1138	c = ARITH_ADD;
1139	gen_arith64:
1140	if (const_args[2]) {
1141	tgen_arithi64(s, c, args[0], args[2]);
1142	} else {
1143	tcg_out_modrm(s, 0x01 \| (c << 3) \| P_REXW, args[2], args[0]);
1144	}
1145	break;
1146
1147	case INDEX_op_mul_i32:
1148	if (const_args[2]) {
1149	int32_t val;
1150	val = args[2];
1151	if (val == (int8_t)val) {
1152	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1153	tcg_out8(s, val);
1154	} else {
1155	tcg_out_modrm(s, 0x69, args[0], args[0]);
1156	tcg_out32(s, val);
1157	}
1158	} else {
1159	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1160	}
1161	break;
1162	case INDEX_op_mul_i64:
1163	if (const_args[2]) {
1164	int32_t val;
1165	val = args[2];
1166	if (val == (int8_t)val) {
1167	tcg_out_modrm(s, 0x6b \| P_REXW, args[0], args[0]);
1168	tcg_out8(s, val);
1169	} else {
1170	tcg_out_modrm(s, 0x69 \| P_REXW, args[0], args[0]);
1171	tcg_out32(s, val);
1172	}
1173	} else {
1174	tcg_out_modrm(s, 0xaf \| P_EXT \| P_REXW, args[0], args[2]);
1175	}
1176	break;
1177	case INDEX_op_div2_i32:
1178	tcg_out_modrm(s, 0xf7, 7, args[4]);
1179	break;
1180	case INDEX_op_divu2_i32:
1181	tcg_out_modrm(s, 0xf7, 6, args[4]);
1182	break;
1183	case INDEX_op_div2_i64:
1184	tcg_out_modrm(s, 0xf7 \| P_REXW, 7, args[4]);
1185	break;
1186	case INDEX_op_divu2_i64:
1187	tcg_out_modrm(s, 0xf7 \| P_REXW, 6, args[4]);
1188	break;
1189
1190	case INDEX_op_shl_i32:
1191	c = SHIFT_SHL;
1192	gen_shift32:
1193	if (const_args[2]) {
1194	if (args[2] == 1) {
1195	tcg_out_modrm(s, 0xd1, c, args[0]);
1196	} else {
1197	tcg_out_modrm(s, 0xc1, c, args[0]);
1198	tcg_out8(s, args[2]);
1199	}
1200	} else {
1201	tcg_out_modrm(s, 0xd3, c, args[0]);
1202	}
1203	break;
1204	case INDEX_op_shr_i32:
1205	c = SHIFT_SHR;
1206	goto gen_shift32;
1207	case INDEX_op_sar_i32:
1208	c = SHIFT_SAR;
1209	goto gen_shift32;
1210
1211	case INDEX_op_shl_i64:
1212	c = SHIFT_SHL;
1213	gen_shift64:
1214	if (const_args[2]) {
1215	if (args[2] == 1) {
1216	tcg_out_modrm(s, 0xd1 \| P_REXW, c, args[0]);
1217	} else {
1218	tcg_out_modrm(s, 0xc1 \| P_REXW, c, args[0]);
1219	tcg_out8(s, args[2]);
1220	}
1221	} else {
1222	tcg_out_modrm(s, 0xd3 \| P_REXW, c, args[0]);
1223	}
1224	break;
1225	case INDEX_op_shr_i64:
1226	c = SHIFT_SHR;
1227	goto gen_shift64;
1228	case INDEX_op_sar_i64:
1229	c = SHIFT_SAR;
1230	goto gen_shift64;
1231
1232	case INDEX_op_brcond_i32:
1233	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1234	args[3], 0);
1235	break;
1236	case INDEX_op_brcond_i64:
1237	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1238	args[3], P_REXW);
1239	break;
1240
1241	case INDEX_op_bswap_i32:
1242	tcg_out_opc(s, (0xc8 + (args[0] & 7)) \| P_EXT, 0, args[0], 0);
1243	break;
1244	case INDEX_op_bswap_i64:
1245	tcg_out_opc(s, (0xc8 + (args[0] & 7)) \| P_EXT \| P_REXW, 0, args[0], 0);
1246	break;
1247
1248	case INDEX_op_neg_i32:
1249	tcg_out_modrm(s, 0xf7, 3, args[0]);
1250	break;
1251	case INDEX_op_neg_i64:
1252	tcg_out_modrm(s, 0xf7 \| P_REXW, 3, args[0]);
1253	break;
1254
1255	case INDEX_op_ext8s_i32:
1256	tcg_out_modrm(s, 0xbe \| P_EXT \| P_REXB, args[0], args[1]);
1257	break;
1258	case INDEX_op_ext16s_i32:
1259	tcg_out_modrm(s, 0xbf \| P_EXT, args[0], args[1]);
1260	break;
1261	case INDEX_op_ext8s_i64:
1262	tcg_out_modrm(s, 0xbe \| P_EXT \| P_REXW, args[0], args[1]);
1263	break;
1264	case INDEX_op_ext16s_i64:
1265	tcg_out_modrm(s, 0xbf \| P_EXT \| P_REXW, args[0], args[1]);
1266	break;
1267	case INDEX_op_ext32s_i64:
1268	tcg_out_modrm(s, 0x63 \| P_REXW, args[0], args[1]);
1269	break;
1270
1271	case INDEX_op_qemu_ld8u:
1272	tcg_out_qemu_ld(s, args, 0);
1273	break;
1274	case INDEX_op_qemu_ld8s:
1275	tcg_out_qemu_ld(s, args, 0 \| 4);
1276	break;
1277	case INDEX_op_qemu_ld16u:
1278	tcg_out_qemu_ld(s, args, 1);
1279	break;
1280	case INDEX_op_qemu_ld16s:
1281	tcg_out_qemu_ld(s, args, 1 \| 4);
1282	break;
1283	case INDEX_op_qemu_ld32u:
1284	tcg_out_qemu_ld(s, args, 2);
1285	break;
1286	case INDEX_op_qemu_ld32s:
1287	tcg_out_qemu_ld(s, args, 2 \| 4);
1288	break;
1289	case INDEX_op_qemu_ld64:
1290	tcg_out_qemu_ld(s, args, 3);
1291	break;
1292
1293	case INDEX_op_qemu_st8:
1294	tcg_out_qemu_st(s, args, 0);
1295	break;
1296	case INDEX_op_qemu_st16:
1297	tcg_out_qemu_st(s, args, 1);
1298	break;
1299	case INDEX_op_qemu_st32:
1300	tcg_out_qemu_st(s, args, 2);
1301	break;
1302	case INDEX_op_qemu_st64:
1303	tcg_out_qemu_st(s, args, 3);
1304	break;
1305
1306	default:
1307	tcg_abort();
1308	}
1309	}
1310
1311	static int tcg_target_callee_save_regs[] = {
1312	TCG_REG_RBP,
1313	TCG_REG_RBX,
1314	TCG_REG_R12,
1315	TCG_REG_R13,
1316	/* TCG_REG_R14, / / currently used for the global env, so no
1317	need to save */
1318	TCG_REG_R15,
1319	};
1320
1321	/* Generate global QEMU prologue and epilogue code */
1322	void tcg_target_qemu_prologue(TCGContext *s)
1323	{
1324	int i, frame_size, push_size, stack_addend;
1325
1326	/* TB prologue */
1327	/* save all callee saved registers */
1328	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1329	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1330
1331	}
1332	/* reserve some stack space */
1333	push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1334	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1335	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1336	~(TCG_TARGET_STACK_ALIGN - 1);
1337	stack_addend = frame_size - push_size;
1338	tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1339
1340	tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp %rdi /
1341
1342	/* TB epilogue */
1343	tb_ret_addr = s->code_ptr;
1344	tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1345	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1346	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1347	}
1348	tcg_out8(s, 0xc3); /* ret */
1349	}
1350
1351	static const TCGTargetOpDef x86_64_op_defs[] = {
1352	{ INDEX_op_exit_tb, { } },
1353	{ INDEX_op_goto_tb, { } },
1354	{ INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1355	{ INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1356	{ INDEX_op_br, { } },
1357
1358	{ INDEX_op_mov_i32, { "r", "r" } },
1359	{ INDEX_op_movi_i32, { "r" } },
1360	{ INDEX_op_ld8u_i32, { "r", "r" } },
1361	{ INDEX_op_ld8s_i32, { "r", "r" } },
1362	{ INDEX_op_ld16u_i32, { "r", "r" } },
1363	{ INDEX_op_ld16s_i32, { "r", "r" } },
1364	{ INDEX_op_ld_i32, { "r", "r" } },
1365	{ INDEX_op_st8_i32, { "r", "r" } },
1366	{ INDEX_op_st16_i32, { "r", "r" } },
1367	{ INDEX_op_st_i32, { "r", "r" } },
1368
1369	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1370	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1371	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1372	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1373	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1374	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1375	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1376	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1377
1378	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1379	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1380	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1381
1382	{ INDEX_op_brcond_i32, { "r", "ri" } },
1383
1384	{ INDEX_op_mov_i64, { "r", "r" } },
1385	{ INDEX_op_movi_i64, { "r" } },
1386	{ INDEX_op_ld8u_i64, { "r", "r" } },
1387	{ INDEX_op_ld8s_i64, { "r", "r" } },
1388	{ INDEX_op_ld16u_i64, { "r", "r" } },
1389	{ INDEX_op_ld16s_i64, { "r", "r" } },
1390	{ INDEX_op_ld32u_i64, { "r", "r" } },
1391	{ INDEX_op_ld32s_i64, { "r", "r" } },
1392	{ INDEX_op_ld_i64, { "r", "r" } },
1393	{ INDEX_op_st8_i64, { "r", "r" } },
1394	{ INDEX_op_st16_i64, { "r", "r" } },
1395	{ INDEX_op_st32_i64, { "r", "r" } },
1396	{ INDEX_op_st_i64, { "r", "r" } },
1397
1398	{ INDEX_op_add_i64, { "r", "0", "re" } },
1399	{ INDEX_op_mul_i64, { "r", "0", "re" } },
1400	{ INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1401	{ INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1402	{ INDEX_op_sub_i64, { "r", "0", "re" } },
1403	{ INDEX_op_and_i64, { "r", "0", "reZ" } },
1404	{ INDEX_op_or_i64, { "r", "0", "re" } },
1405	{ INDEX_op_xor_i64, { "r", "0", "re" } },
1406
1407	{ INDEX_op_shl_i64, { "r", "0", "ci" } },
1408	{ INDEX_op_shr_i64, { "r", "0", "ci" } },
1409	{ INDEX_op_sar_i64, { "r", "0", "ci" } },
1410
1411	{ INDEX_op_brcond_i64, { "r", "re" } },
1412
1413	{ INDEX_op_bswap_i32, { "r", "0" } },
1414	{ INDEX_op_bswap_i64, { "r", "0" } },
1415
1416	{ INDEX_op_neg_i32, { "r", "0" } },
1417	{ INDEX_op_neg_i64, { "r", "0" } },
1418
1419	{ INDEX_op_ext8s_i32, { "r", "r"} },
1420	{ INDEX_op_ext16s_i32, { "r", "r"} },
1421	{ INDEX_op_ext8s_i64, { "r", "r"} },
1422	{ INDEX_op_ext16s_i64, { "r", "r"} },
1423	{ INDEX_op_ext32s_i64, { "r", "r"} },
1424
1425	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1426	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1427	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1428	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1429	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1430	{ INDEX_op_qemu_ld32s, { "r", "L" } },
1431	{ INDEX_op_qemu_ld64, { "r", "L" } },
1432
1433	{ INDEX_op_qemu_st8, { "L", "L" } },
1434	{ INDEX_op_qemu_st16, { "L", "L" } },
1435	{ INDEX_op_qemu_st32, { "L", "L" } },
1436	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1437
1438	{ -1 },
1439	};
1440
1441	void tcg_target_init(TCGContext *s)
1442	{
1443	/* fail safe */
1444	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1445	tcg_abort();
1446
1447	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1448	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1449	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1450	(1 << TCG_REG_RDI) \|
1451	(1 << TCG_REG_RSI) \|
1452	(1 << TCG_REG_RDX) \|
1453	(1 << TCG_REG_RCX) \|
1454	(1 << TCG_REG_R8) \|
1455	(1 << TCG_REG_R9) \|
1456	(1 << TCG_REG_RAX) \|
1457	(1 << TCG_REG_R10) \|
1458	(1 << TCG_REG_R11));
1459
1460	tcg_regset_clear(s->reserved_regs);
1461	tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1462
1463	tcg_add_target_add_op_defs(x86_64_op_defs);
1464	}

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source: vbox/trunk/src/recompiler/tcg/x86_64/tcg-target.c@ 36125

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