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source: vbox/trunk/src/recompiler/tcg/x86_64/tcg-target.c@ 36140

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1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#ifndef NDEBUG
26static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27 "%rax",
28 "%rcx",
29 "%rdx",
30 "%rbx",
31 "%rsp",
32 "%rbp",
33 "%rsi",
34 "%rdi",
35 "%r8",
36 "%r9",
37 "%r10",
38 "%r11",
39 "%r12",
40 "%r13",
41 "%r14",
42 "%r15",
43};
44#endif
45
46static const int tcg_target_reg_alloc_order[] = {
47 TCG_REG_RDI,
48 TCG_REG_RSI,
49 TCG_REG_RDX,
50 TCG_REG_RCX,
51 TCG_REG_R8,
52 TCG_REG_R9,
53 TCG_REG_RAX,
54 TCG_REG_R10,
55 TCG_REG_R11,
56
57 TCG_REG_RBP,
58 TCG_REG_RBX,
59 TCG_REG_R12,
60 TCG_REG_R13,
61 TCG_REG_R14,
62 TCG_REG_R15,
63};
64
65static const int tcg_target_call_iarg_regs[6] = {
66 TCG_REG_RDI,
67 TCG_REG_RSI,
68 TCG_REG_RDX,
69 TCG_REG_RCX,
70 TCG_REG_R8,
71 TCG_REG_R9,
72};
73
74static const int tcg_target_call_oarg_regs[2] = {
75 TCG_REG_RAX,
76 TCG_REG_RDX
77};
78
79static uint8_t *tb_ret_addr;
80
81static void patch_reloc(uint8_t *code_ptr, int type,
82 tcg_target_long value, tcg_target_long addend)
83{
84 value += addend;
85 switch(type) {
86 case R_X86_64_32:
87 if (value != (uint32_t)value)
88 tcg_abort();
89 *(uint32_t *)code_ptr = value;
90 break;
91 case R_X86_64_32S:
92 if (value != (int32_t)value)
93 tcg_abort();
94 *(uint32_t *)code_ptr = value;
95 break;
96 case R_386_PC32:
97 value -= (long)code_ptr;
98 if (value != (int32_t)value)
99 tcg_abort();
100 *(uint32_t *)code_ptr = value;
101 break;
102 default:
103 tcg_abort();
104 }
105}
106
107/* maximum number of register used for input function arguments */
108static inline int tcg_target_get_call_iarg_regs_count(int flags)
109{
110 return 6;
111}
112
113/* parse target specific constraints */
114static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
115{
116 const char *ct_str;
117
118 ct_str = *pct_str;
119 switch(ct_str[0]) {
120 case 'a':
121 ct->ct |= TCG_CT_REG;
122 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
123 break;
124 case 'b':
125 ct->ct |= TCG_CT_REG;
126 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
127 break;
128 case 'c':
129 ct->ct |= TCG_CT_REG;
130 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
131 break;
132 case 'd':
133 ct->ct |= TCG_CT_REG;
134 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
135 break;
136 case 'S':
137 ct->ct |= TCG_CT_REG;
138 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
139 break;
140 case 'D':
141 ct->ct |= TCG_CT_REG;
142 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
143 break;
144 case 'q':
145 ct->ct |= TCG_CT_REG;
146 tcg_regset_set32(ct->u.regs, 0, 0xf);
147 break;
148 case 'r':
149 ct->ct |= TCG_CT_REG;
150 tcg_regset_set32(ct->u.regs, 0, 0xffff);
151 break;
152 case 'L': /* qemu_ld/st constraint */
153 ct->ct |= TCG_CT_REG;
154 tcg_regset_set32(ct->u.regs, 0, 0xffff);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
157 break;
158 case 'e':
159 ct->ct |= TCG_CT_CONST_S32;
160 break;
161 case 'Z':
162 ct->ct |= TCG_CT_CONST_U32;
163 break;
164 default:
165 return -1;
166 }
167 ct_str++;
168 *pct_str = ct_str;
169 return 0;
170}
171
172/* test if a constant matches the constraint */
173static inline int tcg_target_const_match(tcg_target_long val,
174 const TCGArgConstraint *arg_ct)
175{
176 int ct;
177 ct = arg_ct->ct;
178 if (ct & TCG_CT_CONST)
179 return 1;
180 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
181 return 1;
182 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
183 return 1;
184 else
185 return 0;
186}
187
188#define ARITH_ADD 0
189#define ARITH_OR 1
190#define ARITH_ADC 2
191#define ARITH_SBB 3
192#define ARITH_AND 4
193#define ARITH_SUB 5
194#define ARITH_XOR 6
195#define ARITH_CMP 7
196
197#define SHIFT_SHL 4
198#define SHIFT_SHR 5
199#define SHIFT_SAR 7
200
201#define JCC_JMP (-1)
202#define JCC_JO 0x0
203#define JCC_JNO 0x1
204#define JCC_JB 0x2
205#define JCC_JAE 0x3
206#define JCC_JE 0x4
207#define JCC_JNE 0x5
208#define JCC_JBE 0x6
209#define JCC_JA 0x7
210#define JCC_JS 0x8
211#define JCC_JNS 0x9
212#define JCC_JP 0xa
213#define JCC_JNP 0xb
214#define JCC_JL 0xc
215#define JCC_JGE 0xd
216#define JCC_JLE 0xe
217#define JCC_JG 0xf
218
219#define P_EXT 0x100 /* 0x0f opcode prefix */
220#define P_REXW 0x200 /* set rex.w = 1 */
221#define P_REXB 0x400 /* force rex use for byte registers */
222
223static const uint8_t tcg_cond_to_jcc[10] = {
224 [TCG_COND_EQ] = JCC_JE,
225 [TCG_COND_NE] = JCC_JNE,
226 [TCG_COND_LT] = JCC_JL,
227 [TCG_COND_GE] = JCC_JGE,
228 [TCG_COND_LE] = JCC_JLE,
229 [TCG_COND_GT] = JCC_JG,
230 [TCG_COND_LTU] = JCC_JB,
231 [TCG_COND_GEU] = JCC_JAE,
232 [TCG_COND_LEU] = JCC_JBE,
233 [TCG_COND_GTU] = JCC_JA,
234};
235
236static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
237{
238 int rex;
239 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
240 ((x >> 2) & 2) | ((rm >> 3) & 1);
241 if (rex || (opc & P_REXB)) {
242 tcg_out8(s, rex | 0x40);
243 }
244 if (opc & P_EXT)
245 tcg_out8(s, 0x0f);
246 tcg_out8(s, opc);
247}
248
249static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
250{
251 tcg_out_opc(s, opc, r, rm, 0);
252 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
253}
254
255/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
256static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
257 tcg_target_long offset)
258{
259 if (rm < 0) {
260 tcg_target_long val;
261 tcg_out_opc(s, opc, r, 0, 0);
262 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
263 if (val == (int32_t)val) {
264 /* eip relative */
265 tcg_out8(s, 0x05 | ((r & 7) << 3));
266 tcg_out32(s, val);
267 } else if (offset == (int32_t)offset) {
268 tcg_out8(s, 0x04 | ((r & 7) << 3));
269 tcg_out8(s, 0x25); /* sib */
270 tcg_out32(s, offset);
271 } else {
272 tcg_abort();
273 }
274 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
275 tcg_out_opc(s, opc, r, rm, 0);
276 if ((rm & 7) == TCG_REG_RSP) {
277 tcg_out8(s, 0x04 | ((r & 7) << 3));
278 tcg_out8(s, 0x24);
279 } else {
280 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
281 }
282 } else if ((int8_t)offset == offset) {
283 tcg_out_opc(s, opc, r, rm, 0);
284 if ((rm & 7) == TCG_REG_RSP) {
285 tcg_out8(s, 0x44 | ((r & 7) << 3));
286 tcg_out8(s, 0x24);
287 } else {
288 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
289 }
290 tcg_out8(s, offset);
291 } else {
292 tcg_out_opc(s, opc, r, rm, 0);
293 if ((rm & 7) == TCG_REG_RSP) {
294 tcg_out8(s, 0x84 | ((r & 7) << 3));
295 tcg_out8(s, 0x24);
296 } else {
297 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
298 }
299 tcg_out32(s, offset);
300 }
301}
302
303#if defined(CONFIG_SOFTMMU)
304/* XXX: incomplete. index must be different from ESP */
305static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
306 int index, int shift,
307 tcg_target_long offset)
308{
309 int mod;
310 if (rm == -1)
311 tcg_abort();
312 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
313 mod = 0;
314 } else if (offset == (int8_t)offset) {
315 mod = 0x40;
316 } else if (offset == (int32_t)offset) {
317 mod = 0x80;
318 } else {
319 tcg_abort();
320 }
321 if (index == -1) {
322 tcg_out_opc(s, opc, r, rm, 0);
323 if ((rm & 7) == TCG_REG_RSP) {
324 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
325 tcg_out8(s, 0x04 | (rm & 7));
326 } else {
327 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
328 }
329 } else {
330 tcg_out_opc(s, opc, r, rm, index);
331 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
332 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
333 }
334 if (mod == 0x40) {
335 tcg_out8(s, offset);
336 } else if (mod == 0x80) {
337 tcg_out32(s, offset);
338 }
339}
340#endif
341
342static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
343{
344 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
345}
346
347static inline void tcg_out_movi(TCGContext *s, TCGType type,
348 int ret, tcg_target_long arg)
349{
350 if (arg == 0) {
351 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
352 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
353 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
354 tcg_out32(s, arg);
355 } else if (arg == (int32_t)arg) {
356 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
357 tcg_out32(s, arg);
358 } else {
359 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
360 tcg_out32(s, arg);
361 tcg_out32(s, arg >> 32);
362 }
363}
364
365static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
366 int arg1, tcg_target_long arg2)
367{
368 if (type == TCG_TYPE_I32)
369 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
370 else
371 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
372}
373
374static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
375 int arg1, tcg_target_long arg2)
376{
377 if (type == TCG_TYPE_I32)
378 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
379 else
380 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
381}
382
383static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
384{
385 if (val == (int8_t)val) {
386 tcg_out_modrm(s, 0x83, c, r0);
387 tcg_out8(s, val);
388 } else if (c == ARITH_AND && val == 0xffu) {
389 /* movzbl */
390 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
391 } else if (c == ARITH_AND && val == 0xffffu) {
392 /* movzwl */
393 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
394 } else {
395 tcg_out_modrm(s, 0x81, c, r0);
396 tcg_out32(s, val);
397 }
398}
399
400static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
401{
402 if (val == (int8_t)val) {
403 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
404 tcg_out8(s, val);
405 } else if (c == ARITH_AND && val == 0xffu) {
406 /* movzbl */
407 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
408 } else if (c == ARITH_AND && val == 0xffffu) {
409 /* movzwl */
410 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
411 } else if (c == ARITH_AND && val == 0xffffffffu) {
412 /* 32-bit mov zero extends */
413 tcg_out_modrm(s, 0x8b, r0, r0);
414 } else if (val == (int32_t)val) {
415 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
416 tcg_out32(s, val);
417 } else if (c == ARITH_AND && val == (uint32_t)val) {
418 tcg_out_modrm(s, 0x81, c, r0);
419 tcg_out32(s, val);
420 } else {
421 tcg_abort();
422 }
423}
424
425static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
426{
427 if (val != 0)
428 tgen_arithi64(s, ARITH_ADD, reg, val);
429}
430
431static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
432{
433 int32_t val, val1;
434 TCGLabel *l = &s->labels[label_index];
435
436 if (l->has_value) {
437 val = l->u.value - (tcg_target_long)s->code_ptr;
438 val1 = val - 2;
439 if ((int8_t)val1 == val1) {
440 if (opc == -1)
441 tcg_out8(s, 0xeb);
442 else
443 tcg_out8(s, 0x70 + opc);
444 tcg_out8(s, val1);
445 } else {
446 if (opc == -1) {
447 tcg_out8(s, 0xe9);
448 tcg_out32(s, val - 5);
449 } else {
450 tcg_out8(s, 0x0f);
451 tcg_out8(s, 0x80 + opc);
452 tcg_out32(s, val - 6);
453 }
454 }
455 } else {
456 if (opc == -1) {
457 tcg_out8(s, 0xe9);
458 } else {
459 tcg_out8(s, 0x0f);
460 tcg_out8(s, 0x80 + opc);
461 }
462 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
463 s->code_ptr += 4;
464 }
465}
466
467static void tcg_out_brcond(TCGContext *s, int cond,
468 TCGArg arg1, TCGArg arg2, int const_arg2,
469 int label_index, int rexw)
470{
471 if (const_arg2) {
472 if (arg2 == 0) {
473 /* test r, r */
474 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
475 } else {
476 if (rexw)
477 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
478 else
479 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
480 }
481 } else {
482 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
483 }
484 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
485}
486
487#ifdef VBOX
488
489DECLINLINE(void) tcg_out_pushq(TCGContext *s, tcg_target_long val)
490{
491 tcg_out8(s, 0x68); /* push imm32, subs 8 from rsp */
492 tcg_out32(s, val); /* imm32 */
493 if ((val >> 32) != 0)
494 {
495 tcg_out8(s, 0xc7); /* mov imm32, 4(%rsp) */
496 tcg_out8(s, 0x44);
497 tcg_out8(s, 0x24);
498 tcg_out8(s, 0x04);
499 tcg_out32(s, ((uint64_t)val) >> 32); /* imm32 */
500 }
501}
502
503DECLINLINE(void) tcg_out_long_call(TCGContext *s, tcg_target_long dst)
504{
505 intptr_t disp = dst - (tcg_target_long)s->code_ptr - 5;
506 /* can do normal call */
507 if (disp < 2LL * _1G && disp > -2LL * _1G)
508 {
509 tcg_out8(s, 0xe8); /* call disp32 */
510 tcg_out32(s, disp); /* disp32 */
511 }
512 else
513 {
514# if 0
515 /* Somewhat tricky, but allows long jump not touching registers */
516 int off = 5 /* push imm32 */ + 5 /* push imm32 */ + 1 /* ret */;
517 if ((((uint64_t)s->code_ptr) + 32) >> 32)
518 off += 8;
519 if (dst >> 32)
520 off += 8;
521 /* return address */
522 tcg_out_pushq(s, (tcg_target_long)s->code_ptr+off);
523 /* destination */
524 tcg_out_pushq(s, dst);
525 tcg_out8(s, 0xc3); /* ret, used as call */
526# else
527 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
528 tcg_out8(s, 0xff); /* call *%eax */
529 tcg_out8(s, 0xd0);
530# endif
531 }
532}
533
534DECLINLINE(void) tcg_out_long_jmp(TCGContext *s, tcg_target_long dst)
535{
536 intptr_t disp;
537
538 disp = dst - (tcg_target_long)s->code_ptr - 2;
539 /* can do short relative jump */
540 if (disp < 0x7f && disp > -0x7f)
541 {
542 tcg_out8(s, 0xeb); /* short jmp */
543 tcg_out8(s, (int8_t)disp);
544 return;
545 }
546
547 disp = dst - (tcg_target_long)s->code_ptr - 5;
548 if (disp < 2LL * _1G && disp > -2LL * _1G)
549 {
550 tcg_out8(s, 0xe9); /* jmp */
551 tcg_out32(s, (int32_t)disp);
552 return;
553 }
554# if 0
555 tcg_out_pushq(s, dst);
556 tcg_out8(s, 0xc3); /* ret */
557# else
558 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX, dst);
559 tcg_out8(s, 0xff); /* jmp *%eax */
560 tcg_out8(s, 0xe0);
561# endif
562}
563
564#endif /* VBOX */
565
566#if defined(CONFIG_SOFTMMU)
567
568#include "../../softmmu_defs.h"
569
570static void *qemu_ld_helpers[4] = {
571 __ldb_mmu,
572 __ldw_mmu,
573 __ldl_mmu,
574 __ldq_mmu,
575};
576
577static void *qemu_st_helpers[4] = {
578 __stb_mmu,
579 __stw_mmu,
580 __stl_mmu,
581 __stq_mmu,
582};
583#endif
584
585#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
586static void *vbox_ld_helpers[] = {
587 __ldub_vbox_phys,
588 __lduw_vbox_phys,
589 __ldul_vbox_phys,
590 __ldq_vbox_phys,
591 __ldb_vbox_phys,
592 __ldw_vbox_phys,
593 __ldl_vbox_phys,
594 __ldq_vbox_phys,
595};
596
597static void *vbox_st_helpers[] = {
598 __stb_vbox_phys,
599 __stw_vbox_phys,
600 __stl_vbox_phys,
601 __stq_vbox_phys
602};
603
604static void tcg_out_vbox_phys_read(TCGContext *s, int index, int addr_reg, int data_reg) {
605 if (addr_reg != TCG_REG_RDI)
606 /* mov addr_reg, %rdi */
607 tcg_out_modrm(s, 0x8b | P_REXW, TCG_REG_RDI, addr_reg);
608
609 tcg_out_long_call(s, (tcg_target_long)vbox_ld_helpers[index]);
610 /* mov %rax, data_reg*/
611 tcg_out_modrm(s, 0x8b | P_REXW, data_reg, TCG_REG_RAX);
612}
613
614static void tcg_out_vbox_phys_write(TCGContext *s, int index, int addr_reg, int val_reg) {
615 if (addr_reg != TCG_REG_RDI)
616 /* mov addr_reg, %rdi */
617 tcg_out_modrm(s, 0x8b | P_REXW, TCG_REG_RDI, addr_reg);
618 if (val_reg != TCG_REG_RSI)
619 /* mov addr_reg, %rsi */
620 tcg_out_modrm(s, 0x8b | P_REXW, TCG_REG_RSI, val_reg);
621 tcg_out_long_call(s, (tcg_target_long)vbox_st_helpers[index]);
622}
623
624#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
625
626static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
627 int opc)
628{
629 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
630#if defined(CONFIG_SOFTMMU)
631 uint8_t *label1_ptr, *label2_ptr;
632#endif
633
634 data_reg = *args++;
635 addr_reg = *args++;
636 mem_index = *args;
637 s_bits = opc & 3;
638
639 r0 = TCG_REG_RDI;
640 r1 = TCG_REG_RSI;
641
642#if TARGET_LONG_BITS == 32
643 rexw = 0;
644#else
645 rexw = P_REXW;
646#endif
647#if defined(CONFIG_SOFTMMU)
648 /* mov */
649 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
650
651 /* mov */
652 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
653
654 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
655 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
656
657 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
658 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
659
660 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
661 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
662
663 /* lea offset(r1, env), r1 */
664 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
665 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
666
667 /* cmp 0(r1), r0 */
668 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
669
670 /* mov */
671 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
672
673 /* je label1 */
674 tcg_out8(s, 0x70 + JCC_JE);
675 label1_ptr = s->code_ptr;
676 s->code_ptr++;
677
678 /* XXX: move that code at the end of the TB */
679 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
680#ifndef VBOX
681 tcg_out8(s, 0xe8);
682 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
683 (tcg_target_long)s->code_ptr - 4);
684#else
685 tcg_out_long_call(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
686#endif
687
688 switch(opc) {
689 case 0 | 4:
690 /* movsbq */
691 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
692 break;
693 case 1 | 4:
694 /* movswq */
695 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
696 break;
697 case 2 | 4:
698 /* movslq */
699 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
700 break;
701 case 0:
702 case 1:
703 case 2:
704 default:
705 /* movl */
706 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
707 break;
708 case 3:
709 tcg_out_mov(s, data_reg, TCG_REG_RAX);
710 break;
711 }
712
713 /* jmp label2 */
714 tcg_out8(s, 0xeb);
715 label2_ptr = s->code_ptr;
716 s->code_ptr++;
717
718 /* label1: */
719 *label1_ptr = s->code_ptr - label1_ptr - 1;
720
721 /* add x(r1), r0 */
722 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
723 offsetof(CPUTLBEntry, addr_read));
724#else
725 r0 = addr_reg;
726#endif
727
728#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
729
730#ifdef TARGET_WORDS_BIGENDIAN
731 bswap = 1;
732#else
733 bswap = 0;
734#endif
735
736 switch(opc) {
737 case 0:
738 /* movzbl */
739 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
740 break;
741 case 0 | 4:
742 /* movsbX */
743 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
744 break;
745 case 1:
746 /* movzwl */
747 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
748 if (bswap) {
749 /* rolw $8, data_reg */
750 tcg_out8(s, 0x66);
751 tcg_out_modrm(s, 0xc1, 0, data_reg);
752 tcg_out8(s, 8);
753 }
754 break;
755 case 1 | 4:
756 if (bswap) {
757 /* movzwl */
758 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
759 /* rolw $8, data_reg */
760 tcg_out8(s, 0x66);
761 tcg_out_modrm(s, 0xc1, 0, data_reg);
762 tcg_out8(s, 8);
763
764 /* movswX data_reg, data_reg */
765 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
766 } else {
767 /* movswX */
768 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
769 }
770 break;
771 case 2:
772 /* movl (r0), data_reg */
773 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
774 if (bswap) {
775 /* bswap */
776 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
777 }
778 break;
779 case 2 | 4:
780 if (bswap) {
781 /* movl (r0), data_reg */
782 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
783 /* bswap */
784 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
785 /* movslq */
786 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
787 } else {
788 /* movslq */
789 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
790 }
791 break;
792 case 3:
793 /* movq (r0), data_reg */
794 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
795 if (bswap) {
796 /* bswap */
797 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
798 }
799 break;
800 default:
801 tcg_abort();
802 }
803#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
804 tcg_out_vbox_phys_read(s, opc, r0, data_reg);
805#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
806
807#if defined(CONFIG_SOFTMMU)
808 /* label2: */
809 *label2_ptr = s->code_ptr - label2_ptr - 1;
810#endif
811}
812
813static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
814 int opc)
815{
816 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
817#if defined(CONFIG_SOFTMMU)
818 uint8_t *label1_ptr, *label2_ptr;
819#endif
820
821 data_reg = *args++;
822 addr_reg = *args++;
823 mem_index = *args;
824
825 s_bits = opc;
826
827 r0 = TCG_REG_RDI;
828 r1 = TCG_REG_RSI;
829
830#if TARGET_LONG_BITS == 32
831 rexw = 0;
832#else
833 rexw = P_REXW;
834#endif
835#if defined(CONFIG_SOFTMMU)
836 /* mov */
837 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
838
839 /* mov */
840 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
841
842 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
843 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
844
845 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
846 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
847
848 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
849 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
850
851 /* lea offset(r1, env), r1 */
852 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
853 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
854
855 /* cmp 0(r1), r0 */
856 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
857
858 /* mov */
859 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
860
861 /* je label1 */
862 tcg_out8(s, 0x70 + JCC_JE);
863 label1_ptr = s->code_ptr;
864 s->code_ptr++;
865
866 /* XXX: move that code at the end of the TB */
867 switch(opc) {
868 case 0:
869 /* movzbl */
870 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
871 break;
872 case 1:
873 /* movzwl */
874 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
875 break;
876 case 2:
877 /* movl */
878 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
879 break;
880 default:
881 case 3:
882 tcg_out_mov(s, TCG_REG_RSI, data_reg);
883 break;
884 }
885 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
886#ifndef VBOX
887 tcg_out8(s, 0xe8);
888 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
889 (tcg_target_long)s->code_ptr - 4);
890#else
891 tcg_out_long_call(s, (tcg_target_long)qemu_st_helpers[s_bits]);
892#endif
893
894 /* jmp label2 */
895 tcg_out8(s, 0xeb);
896 label2_ptr = s->code_ptr;
897 s->code_ptr++;
898
899 /* label1: */
900 *label1_ptr = s->code_ptr - label1_ptr - 1;
901
902 /* add x(r1), r0 */
903 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
904 offsetof(CPUTLBEntry, addr_write));
905#else
906 r0 = addr_reg;
907#endif
908
909#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
910#ifdef TARGET_WORDS_BIGENDIAN
911 bswap = 1;
912#else
913 bswap = 0;
914#endif
915 switch(opc) {
916 case 0:
917 /* movb */
918 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
919 break;
920 case 1:
921 if (bswap) {
922 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
923 tcg_out8(s, 0x66); /* rolw $8, %ecx */
924 tcg_out_modrm(s, 0xc1, 0, r1);
925 tcg_out8(s, 8);
926 data_reg = r1;
927 }
928 /* movw */
929 tcg_out8(s, 0x66);
930 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
931 break;
932 case 2:
933 if (bswap) {
934 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
935 /* bswap data_reg */
936 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
937 data_reg = r1;
938 }
939 /* movl */
940 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
941 break;
942 case 3:
943 if (bswap) {
944 tcg_out_mov(s, r1, data_reg);
945 /* bswap data_reg */
946 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
947 data_reg = r1;
948 }
949 /* movq */
950 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
951 break;
952 default:
953 tcg_abort();
954 }
955#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
956 tcg_out_vbox_phys_write(s, opc, r0, data_reg);
957#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
958
959#if defined(CONFIG_SOFTMMU)
960 /* label2: */
961 *label2_ptr = s->code_ptr - label2_ptr - 1;
962#endif
963}
964
965static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
966 const int *const_args)
967{
968 int c;
969
970 switch(opc) {
971 case INDEX_op_exit_tb:
972 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
973#ifndef VBOX
974 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
975 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
976#else
977 tcg_out_long_jmp(s, (tcg_target_long)tb_ret_addr);
978#endif
979 break;
980 case INDEX_op_goto_tb:
981 if (s->tb_jmp_offset) {
982 /* direct jump method */
983 tcg_out8(s, 0xe9); /* jmp im */
984 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
985 tcg_out32(s, 0);
986 } else {
987 /* indirect jump method */
988 /* jmp Ev */
989#ifndef VBOX
990 tcg_out_modrm_offset(s, 0xff, 4, -1,
991 (tcg_target_long)(s->tb_next +
992 args[0]));
993#else
994 /** @todo: can we clobber RAX here? */
995 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RAX,
996 (tcg_target_long)&(s->tb_next[args[0]]));
997 tcg_out8(s, 0xff); tcg_out8(s, 0x20 | TCG_REG_RAX); /* jmp *(%rax) */
998#endif
999 }
1000 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1001 break;
1002 case INDEX_op_call:
1003 if (const_args[0]) {
1004#ifndef VBOX
1005 tcg_out8(s, 0xe8);
1006 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1007#else
1008 tcg_out_long_call(s, args[0]);
1009#endif
1010 } else {
1011 tcg_out_modrm(s, 0xff, 2, args[0]);
1012 }
1013 break;
1014 case INDEX_op_jmp:
1015 if (const_args[0]) {
1016 tcg_out8(s, 0xe9);
1017 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1018 } else {
1019 tcg_out_modrm(s, 0xff, 4, args[0]);
1020 }
1021 break;
1022 case INDEX_op_br:
1023 tcg_out_jxx(s, JCC_JMP, args[0]);
1024 break;
1025 case INDEX_op_movi_i32:
1026 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1027 break;
1028 case INDEX_op_movi_i64:
1029 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1030 break;
1031 case INDEX_op_ld8u_i32:
1032 case INDEX_op_ld8u_i64:
1033 /* movzbl */
1034 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
1035 break;
1036 case INDEX_op_ld8s_i32:
1037 /* movsbl */
1038 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
1039 break;
1040 case INDEX_op_ld8s_i64:
1041 /* movsbq */
1042 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
1043 break;
1044 case INDEX_op_ld16u_i32:
1045 case INDEX_op_ld16u_i64:
1046 /* movzwl */
1047 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
1048 break;
1049 case INDEX_op_ld16s_i32:
1050 /* movswl */
1051 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
1052 break;
1053 case INDEX_op_ld16s_i64:
1054 /* movswq */
1055 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
1056 break;
1057 case INDEX_op_ld_i32:
1058 case INDEX_op_ld32u_i64:
1059 /* movl */
1060 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1061 break;
1062 case INDEX_op_ld32s_i64:
1063 /* movslq */
1064 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
1065 break;
1066 case INDEX_op_ld_i64:
1067 /* movq */
1068 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
1069 break;
1070
1071 case INDEX_op_st8_i32:
1072 case INDEX_op_st8_i64:
1073 /* movb */
1074 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
1075 break;
1076 case INDEX_op_st16_i32:
1077 case INDEX_op_st16_i64:
1078 /* movw */
1079 tcg_out8(s, 0x66);
1080 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1081 break;
1082 case INDEX_op_st_i32:
1083 case INDEX_op_st32_i64:
1084 /* movl */
1085 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1086 break;
1087 case INDEX_op_st_i64:
1088 /* movq */
1089 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
1090 break;
1091
1092 case INDEX_op_sub_i32:
1093 c = ARITH_SUB;
1094 goto gen_arith32;
1095 case INDEX_op_and_i32:
1096 c = ARITH_AND;
1097 goto gen_arith32;
1098 case INDEX_op_or_i32:
1099 c = ARITH_OR;
1100 goto gen_arith32;
1101 case INDEX_op_xor_i32:
1102 c = ARITH_XOR;
1103 goto gen_arith32;
1104 case INDEX_op_add_i32:
1105 c = ARITH_ADD;
1106 gen_arith32:
1107 if (const_args[2]) {
1108 tgen_arithi32(s, c, args[0], args[2]);
1109 } else {
1110 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
1111 }
1112 break;
1113
1114 case INDEX_op_sub_i64:
1115 c = ARITH_SUB;
1116 goto gen_arith64;
1117 case INDEX_op_and_i64:
1118 c = ARITH_AND;
1119 goto gen_arith64;
1120 case INDEX_op_or_i64:
1121 c = ARITH_OR;
1122 goto gen_arith64;
1123 case INDEX_op_xor_i64:
1124 c = ARITH_XOR;
1125 goto gen_arith64;
1126 case INDEX_op_add_i64:
1127 c = ARITH_ADD;
1128 gen_arith64:
1129 if (const_args[2]) {
1130 tgen_arithi64(s, c, args[0], args[2]);
1131 } else {
1132 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
1133 }
1134 break;
1135
1136 case INDEX_op_mul_i32:
1137 if (const_args[2]) {
1138 int32_t val;
1139 val = args[2];
1140 if (val == (int8_t)val) {
1141 tcg_out_modrm(s, 0x6b, args[0], args[0]);
1142 tcg_out8(s, val);
1143 } else {
1144 tcg_out_modrm(s, 0x69, args[0], args[0]);
1145 tcg_out32(s, val);
1146 }
1147 } else {
1148 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1149 }
1150 break;
1151 case INDEX_op_mul_i64:
1152 if (const_args[2]) {
1153 int32_t val;
1154 val = args[2];
1155 if (val == (int8_t)val) {
1156 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1157 tcg_out8(s, val);
1158 } else {
1159 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1160 tcg_out32(s, val);
1161 }
1162 } else {
1163 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1164 }
1165 break;
1166 case INDEX_op_div2_i32:
1167 tcg_out_modrm(s, 0xf7, 7, args[4]);
1168 break;
1169 case INDEX_op_divu2_i32:
1170 tcg_out_modrm(s, 0xf7, 6, args[4]);
1171 break;
1172 case INDEX_op_div2_i64:
1173 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1174 break;
1175 case INDEX_op_divu2_i64:
1176 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1177 break;
1178
1179 case INDEX_op_shl_i32:
1180 c = SHIFT_SHL;
1181 gen_shift32:
1182 if (const_args[2]) {
1183 if (args[2] == 1) {
1184 tcg_out_modrm(s, 0xd1, c, args[0]);
1185 } else {
1186 tcg_out_modrm(s, 0xc1, c, args[0]);
1187 tcg_out8(s, args[2]);
1188 }
1189 } else {
1190 tcg_out_modrm(s, 0xd3, c, args[0]);
1191 }
1192 break;
1193 case INDEX_op_shr_i32:
1194 c = SHIFT_SHR;
1195 goto gen_shift32;
1196 case INDEX_op_sar_i32:
1197 c = SHIFT_SAR;
1198 goto gen_shift32;
1199
1200 case INDEX_op_shl_i64:
1201 c = SHIFT_SHL;
1202 gen_shift64:
1203 if (const_args[2]) {
1204 if (args[2] == 1) {
1205 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1206 } else {
1207 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1208 tcg_out8(s, args[2]);
1209 }
1210 } else {
1211 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1212 }
1213 break;
1214 case INDEX_op_shr_i64:
1215 c = SHIFT_SHR;
1216 goto gen_shift64;
1217 case INDEX_op_sar_i64:
1218 c = SHIFT_SAR;
1219 goto gen_shift64;
1220
1221 case INDEX_op_brcond_i32:
1222 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1223 args[3], 0);
1224 break;
1225 case INDEX_op_brcond_i64:
1226 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1227 args[3], P_REXW);
1228 break;
1229
1230 case INDEX_op_bswap_i32:
1231 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1232 break;
1233 case INDEX_op_bswap_i64:
1234 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1235 break;
1236
1237 case INDEX_op_neg_i32:
1238 tcg_out_modrm(s, 0xf7, 3, args[0]);
1239 break;
1240 case INDEX_op_neg_i64:
1241 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1242 break;
1243
1244 case INDEX_op_ext8s_i32:
1245 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1246 break;
1247 case INDEX_op_ext16s_i32:
1248 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1249 break;
1250 case INDEX_op_ext8s_i64:
1251 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1252 break;
1253 case INDEX_op_ext16s_i64:
1254 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1255 break;
1256 case INDEX_op_ext32s_i64:
1257 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1258 break;
1259
1260 case INDEX_op_qemu_ld8u:
1261 tcg_out_qemu_ld(s, args, 0);
1262 break;
1263 case INDEX_op_qemu_ld8s:
1264 tcg_out_qemu_ld(s, args, 0 | 4);
1265 break;
1266 case INDEX_op_qemu_ld16u:
1267 tcg_out_qemu_ld(s, args, 1);
1268 break;
1269 case INDEX_op_qemu_ld16s:
1270 tcg_out_qemu_ld(s, args, 1 | 4);
1271 break;
1272 case INDEX_op_qemu_ld32u:
1273 tcg_out_qemu_ld(s, args, 2);
1274 break;
1275 case INDEX_op_qemu_ld32s:
1276 tcg_out_qemu_ld(s, args, 2 | 4);
1277 break;
1278 case INDEX_op_qemu_ld64:
1279 tcg_out_qemu_ld(s, args, 3);
1280 break;
1281
1282 case INDEX_op_qemu_st8:
1283 tcg_out_qemu_st(s, args, 0);
1284 break;
1285 case INDEX_op_qemu_st16:
1286 tcg_out_qemu_st(s, args, 1);
1287 break;
1288 case INDEX_op_qemu_st32:
1289 tcg_out_qemu_st(s, args, 2);
1290 break;
1291 case INDEX_op_qemu_st64:
1292 tcg_out_qemu_st(s, args, 3);
1293 break;
1294
1295 default:
1296 tcg_abort();
1297 }
1298}
1299
1300static int tcg_target_callee_save_regs[] = {
1301 TCG_REG_RBP,
1302 TCG_REG_RBX,
1303 TCG_REG_R12,
1304 TCG_REG_R13,
1305 /* TCG_REG_R14, */ /* currently used for the global env, so no
1306 need to save */
1307 TCG_REG_R15,
1308};
1309
1310static inline void tcg_out_push(TCGContext *s, int reg)
1311{
1312 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1313}
1314
1315static inline void tcg_out_pop(TCGContext *s, int reg)
1316{
1317 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1318}
1319
1320/* Generate global QEMU prologue and epilogue code */
1321void tcg_target_qemu_prologue(TCGContext *s)
1322{
1323 int i, frame_size, push_size, stack_addend;
1324
1325 /* TB prologue */
1326 /* save all callee saved registers */
1327 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1328 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1329
1330 }
1331 /* reserve some stack space */
1332 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1333 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1334 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1335 ~(TCG_TARGET_STACK_ALIGN - 1);
1336 stack_addend = frame_size - push_size;
1337 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1338
1339 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1340
1341 /* TB epilogue */
1342 tb_ret_addr = s->code_ptr;
1343 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1344 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1345 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1346 }
1347 tcg_out8(s, 0xc3); /* ret */
1348}
1349
1350static const TCGTargetOpDef x86_64_op_defs[] = {
1351 { INDEX_op_exit_tb, { } },
1352 { INDEX_op_goto_tb, { } },
1353 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1354 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1355 { INDEX_op_br, { } },
1356
1357 { INDEX_op_mov_i32, { "r", "r" } },
1358 { INDEX_op_movi_i32, { "r" } },
1359 { INDEX_op_ld8u_i32, { "r", "r" } },
1360 { INDEX_op_ld8s_i32, { "r", "r" } },
1361 { INDEX_op_ld16u_i32, { "r", "r" } },
1362 { INDEX_op_ld16s_i32, { "r", "r" } },
1363 { INDEX_op_ld_i32, { "r", "r" } },
1364 { INDEX_op_st8_i32, { "r", "r" } },
1365 { INDEX_op_st16_i32, { "r", "r" } },
1366 { INDEX_op_st_i32, { "r", "r" } },
1367
1368 { INDEX_op_add_i32, { "r", "0", "ri" } },
1369 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1370 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1371 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1372 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1373 { INDEX_op_and_i32, { "r", "0", "ri" } },
1374 { INDEX_op_or_i32, { "r", "0", "ri" } },
1375 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1376
1377 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1378 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1379 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1380
1381 { INDEX_op_brcond_i32, { "r", "ri" } },
1382
1383 { INDEX_op_mov_i64, { "r", "r" } },
1384 { INDEX_op_movi_i64, { "r" } },
1385 { INDEX_op_ld8u_i64, { "r", "r" } },
1386 { INDEX_op_ld8s_i64, { "r", "r" } },
1387 { INDEX_op_ld16u_i64, { "r", "r" } },
1388 { INDEX_op_ld16s_i64, { "r", "r" } },
1389 { INDEX_op_ld32u_i64, { "r", "r" } },
1390 { INDEX_op_ld32s_i64, { "r", "r" } },
1391 { INDEX_op_ld_i64, { "r", "r" } },
1392 { INDEX_op_st8_i64, { "r", "r" } },
1393 { INDEX_op_st16_i64, { "r", "r" } },
1394 { INDEX_op_st32_i64, { "r", "r" } },
1395 { INDEX_op_st_i64, { "r", "r" } },
1396
1397 { INDEX_op_add_i64, { "r", "0", "re" } },
1398 { INDEX_op_mul_i64, { "r", "0", "re" } },
1399 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1400 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1401 { INDEX_op_sub_i64, { "r", "0", "re" } },
1402 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1403 { INDEX_op_or_i64, { "r", "0", "re" } },
1404 { INDEX_op_xor_i64, { "r", "0", "re" } },
1405
1406 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1407 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1408 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1409
1410 { INDEX_op_brcond_i64, { "r", "re" } },
1411
1412 { INDEX_op_bswap_i32, { "r", "0" } },
1413 { INDEX_op_bswap_i64, { "r", "0" } },
1414
1415 { INDEX_op_neg_i32, { "r", "0" } },
1416 { INDEX_op_neg_i64, { "r", "0" } },
1417
1418 { INDEX_op_ext8s_i32, { "r", "r"} },
1419 { INDEX_op_ext16s_i32, { "r", "r"} },
1420 { INDEX_op_ext8s_i64, { "r", "r"} },
1421 { INDEX_op_ext16s_i64, { "r", "r"} },
1422 { INDEX_op_ext32s_i64, { "r", "r"} },
1423
1424 { INDEX_op_qemu_ld8u, { "r", "L" } },
1425 { INDEX_op_qemu_ld8s, { "r", "L" } },
1426 { INDEX_op_qemu_ld16u, { "r", "L" } },
1427 { INDEX_op_qemu_ld16s, { "r", "L" } },
1428 { INDEX_op_qemu_ld32u, { "r", "L" } },
1429 { INDEX_op_qemu_ld32s, { "r", "L" } },
1430 { INDEX_op_qemu_ld64, { "r", "L" } },
1431
1432 { INDEX_op_qemu_st8, { "L", "L" } },
1433 { INDEX_op_qemu_st16, { "L", "L" } },
1434 { INDEX_op_qemu_st32, { "L", "L" } },
1435 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1436
1437 { -1 },
1438};
1439
1440void tcg_target_init(TCGContext *s)
1441{
1442 /* fail safe */
1443 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1444 tcg_abort();
1445
1446 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1447 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1448 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1449 (1 << TCG_REG_RDI) |
1450 (1 << TCG_REG_RSI) |
1451 (1 << TCG_REG_RDX) |
1452 (1 << TCG_REG_RCX) |
1453 (1 << TCG_REG_R8) |
1454 (1 << TCG_REG_R9) |
1455 (1 << TCG_REG_RAX) |
1456 (1 << TCG_REG_R10) |
1457 (1 << TCG_REG_R11));
1458
1459 tcg_regset_clear(s->reserved_regs);
1460 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1461
1462 tcg_add_target_add_op_defs(x86_64_op_defs);
1463}
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