VirtualBox

source: vbox/trunk/src/recompiler_new/cpu-all.h@ 17556

Last change on this file since 17556 was 17420, checked in by vboxsync, 16 years ago

REM: fix problem in REM codegen buffer size initialization, leading to very small (1M) code buffer. Now use 8M always.
  • Property svn:eol-style set to native
File size: 36.5 KB
Line 
1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#ifndef CPU_ALL_H
30#define CPU_ALL_H
31
32#ifdef VBOX
33# ifndef LOG_GROUP
34# define LOG_GROUP LOG_GROUP_REM
35# endif
36# include <VBox/log.h>
37# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
38#endif
39
40#if defined(__arm__) || defined(__sparc__)
41#define WORDS_ALIGNED
42#endif
43
44/* some important defines:
45 *
46 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
47 * memory accesses.
48 *
49 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
50 * otherwise little endian.
51 *
52 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
53 *
54 * TARGET_WORDS_BIGENDIAN : same for target cpu
55 */
56
57#include "bswap.h"
58
59#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
60#define BSWAP_NEEDED
61#endif
62
63#ifdef BSWAP_NEEDED
64
65static inline uint16_t tswap16(uint16_t s)
66{
67 return bswap16(s);
68}
69
70static inline uint32_t tswap32(uint32_t s)
71{
72 return bswap32(s);
73}
74
75static inline uint64_t tswap64(uint64_t s)
76{
77 return bswap64(s);
78}
79
80static inline void tswap16s(uint16_t *s)
81{
82 *s = bswap16(*s);
83}
84
85static inline void tswap32s(uint32_t *s)
86{
87 *s = bswap32(*s);
88}
89
90static inline void tswap64s(uint64_t *s)
91{
92 *s = bswap64(*s);
93}
94
95#else
96
97#ifndef VBOX
98static inline uint16_t tswap16(uint16_t s)
99#else
100DECLINLINE(uint16_t) tswap16(uint16_t s)
101#endif
102{
103 return s;
104}
105
106#ifndef VBOX
107static inline uint32_t tswap32(uint32_t s)
108#else
109DECLINLINE(uint32_t) tswap32(uint32_t s)
110#endif
111{
112 return s;
113}
114
115#ifndef VBOX
116static inline uint64_t tswap64(uint64_t s)
117#else
118DECLINLINE(uint64_t) tswap64(uint64_t s)
119#endif
120{
121 return s;
122}
123
124#ifndef VBOX
125static inline void tswap16s(uint16_t *s)
126#else
127DECLINLINE(void) tswap16s(uint16_t *s)
128#endif
129{
130}
131
132#ifndef VBOX
133static inline void tswap32s(uint32_t *s)
134#else
135DECLINLINE(void) tswap32s(uint32_t *s)
136#endif
137{
138}
139
140#ifndef VBOX
141static inline void tswap64s(uint64_t *s)
142#else
143DECLINLINE(void) tswap64s(uint64_t *s)
144#endif
145{
146}
147
148#endif
149
150#if TARGET_LONG_SIZE == 4
151#define tswapl(s) tswap32(s)
152#define tswapls(s) tswap32s((uint32_t *)(s))
153#define bswaptls(s) bswap32s(s)
154#else
155#define tswapl(s) tswap64(s)
156#define tswapls(s) tswap64s((uint64_t *)(s))
157#define bswaptls(s) bswap64s(s)
158#endif
159
160typedef union {
161 float32 f;
162 uint32_t l;
163} CPU_FloatU;
164
165/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
166 endian ! */
167typedef union {
168 float64 d;
169#if defined(WORDS_BIGENDIAN) \
170 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
171 struct {
172 uint32_t upper;
173 uint32_t lower;
174 } l;
175#else
176 struct {
177 uint32_t lower;
178 uint32_t upper;
179 } l;
180#endif
181 uint64_t ll;
182} CPU_DoubleU;
183
184#ifdef TARGET_SPARC
185typedef union {
186 float128 q;
187#if defined(WORDS_BIGENDIAN) \
188 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
189 struct {
190 uint32_t upmost;
191 uint32_t upper;
192 uint32_t lower;
193 uint32_t lowest;
194 } l;
195 struct {
196 uint64_t upper;
197 uint64_t lower;
198 } ll;
199#else
200 struct {
201 uint32_t lowest;
202 uint32_t lower;
203 uint32_t upper;
204 uint32_t upmost;
205 } l;
206 struct {
207 uint64_t lower;
208 uint64_t upper;
209 } ll;
210#endif
211} CPU_QuadU;
212#endif
213
214/* CPU memory access without any memory or io remapping */
215
216/*
217 * the generic syntax for the memory accesses is:
218 *
219 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
220 *
221 * store: st{type}{size}{endian}_{access_type}(ptr, val)
222 *
223 * type is:
224 * (empty): integer access
225 * f : float access
226 *
227 * sign is:
228 * (empty): for floats or 32 bit size
229 * u : unsigned
230 * s : signed
231 *
232 * size is:
233 * b: 8 bits
234 * w: 16 bits
235 * l: 32 bits
236 * q: 64 bits
237 *
238 * endian is:
239 * (empty): target cpu endianness or 8 bit access
240 * r : reversed target cpu endianness (not implemented yet)
241 * be : big endian (not implemented yet)
242 * le : little endian (not implemented yet)
243 *
244 * access_type is:
245 * raw : host memory access
246 * user : user mode access using soft MMU
247 * kernel : kernel mode access using soft MMU
248 */
249
250#ifdef VBOX
251void remAbort(int rc, const char *pszTip) __attribute__((__noreturn__));
252
253#ifndef VBOX_WITH_NEW_PHYS_CODE
254void remR3GrowDynRange(unsigned long physaddr);
255#endif
256
257void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb);
258RTCCUINTREG remR3PhysReadU8(RTGCPHYS SrcGCPhys);
259RTCCINTREG remR3PhysReadS8(RTGCPHYS SrcGCPhys);
260RTCCUINTREG remR3PhysReadU16(RTGCPHYS SrcGCPhys);
261RTCCINTREG remR3PhysReadS16(RTGCPHYS SrcGCPhys);
262RTCCUINTREG remR3PhysReadU32(RTGCPHYS SrcGCPhys);
263RTCCINTREG remR3PhysReadS32(RTGCPHYS SrcGCPhys);
264uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys);
265int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys);
266void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb);
267void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val);
268void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val);
269void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val);
270void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val);
271
272#ifndef REM_PHYS_ADDR_IN_TLB
273void *remR3TlbGCPhys2Ptr(CPUState *env1, target_ulong physAddr, int fWritable);
274#endif
275
276#endif /* VBOX */
277
278#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
279
280DECLINLINE(uint8_t) ldub_p(void *ptr)
281{
282 VBOX_CHECK_ADDR(ptr);
283 return remR3PhysReadU8((uintptr_t)ptr);
284}
285
286DECLINLINE(int8_t) ldsb_p(void *ptr)
287{
288 VBOX_CHECK_ADDR(ptr);
289 return remR3PhysReadS8((uintptr_t)ptr);
290}
291
292DECLINLINE(void) stb_p(void *ptr, int v)
293{
294 VBOX_CHECK_ADDR(ptr);
295 remR3PhysWriteU8((uintptr_t)ptr, v);
296}
297
298DECLINLINE(uint32_t) lduw_le_p(void *ptr)
299{
300 VBOX_CHECK_ADDR(ptr);
301 return remR3PhysReadU16((uintptr_t)ptr);
302}
303
304DECLINLINE(int32_t) ldsw_le_p(void *ptr)
305{
306 VBOX_CHECK_ADDR(ptr);
307 return remR3PhysReadS16((uintptr_t)ptr);
308}
309
310DECLINLINE(void) stw_le_p(void *ptr, int v)
311{
312 VBOX_CHECK_ADDR(ptr);
313 remR3PhysWriteU16((uintptr_t)ptr, v);
314}
315
316DECLINLINE(uint32_t) ldl_le_p(void *ptr)
317{
318 VBOX_CHECK_ADDR(ptr);
319 return remR3PhysReadU32((uintptr_t)ptr);
320}
321
322DECLINLINE(void) stl_le_p(void *ptr, int v)
323{
324 VBOX_CHECK_ADDR(ptr);
325 remR3PhysWriteU32((uintptr_t)ptr, v);
326}
327
328DECLINLINE(void) stq_le_p(void *ptr, uint64_t v)
329{
330 VBOX_CHECK_ADDR(ptr);
331 remR3PhysWriteU64((uintptr_t)ptr, v);
332}
333
334DECLINLINE(uint64_t) ldq_le_p(void *ptr)
335{
336 VBOX_CHECK_ADDR(ptr);
337 return remR3PhysReadU64((uintptr_t)ptr);
338}
339
340#undef VBOX_CHECK_ADDR
341
342/* float access */
343
344DECLINLINE(float32) ldfl_le_p(void *ptr)
345{
346 union {
347 float32 f;
348 uint32_t i;
349 } u;
350 u.i = ldl_le_p(ptr);
351 return u.f;
352}
353
354DECLINLINE(void) stfl_le_p(void *ptr, float32 v)
355{
356 union {
357 float32 f;
358 uint32_t i;
359 } u;
360 u.f = v;
361 stl_le_p(ptr, u.i);
362}
363
364DECLINLINE(float64) ldfq_le_p(void *ptr)
365{
366 CPU_DoubleU u;
367 u.l.lower = ldl_le_p(ptr);
368 u.l.upper = ldl_le_p((uint8_t*)ptr + 4);
369 return u.d;
370}
371
372DECLINLINE(void) stfq_le_p(void *ptr, float64 v)
373{
374 CPU_DoubleU u;
375 u.d = v;
376 stl_le_p(ptr, u.l.lower);
377 stl_le_p((uint8_t*)ptr + 4, u.l.upper);
378}
379
380#else /* !(VBOX && REM_PHYS_ADDR_IN_TLB) */
381
382static inline int ldub_p(void *ptr)
383{
384 return *(uint8_t *)ptr;
385}
386
387static inline int ldsb_p(void *ptr)
388{
389 return *(int8_t *)ptr;
390}
391
392static inline void stb_p(void *ptr, int v)
393{
394 *(uint8_t *)ptr = v;
395}
396
397/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
398 kernel handles unaligned load/stores may give better results, but
399 it is a system wide setting : bad */
400#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
401
402/* conservative code for little endian unaligned accesses */
403static inline int lduw_le_p(void *ptr)
404{
405#ifdef __powerpc__
406 int val;
407 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
408 return val;
409#else
410 uint8_t *p = ptr;
411 return p[0] | (p[1] << 8);
412#endif
413}
414
415static inline int ldsw_le_p(void *ptr)
416{
417#ifdef __powerpc__
418 int val;
419 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
420 return (int16_t)val;
421#else
422 uint8_t *p = ptr;
423 return (int16_t)(p[0] | (p[1] << 8));
424#endif
425}
426
427static inline int ldl_le_p(void *ptr)
428{
429#ifdef __powerpc__
430 int val;
431 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
432 return val;
433#else
434 uint8_t *p = ptr;
435 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
436#endif
437}
438
439static inline uint64_t ldq_le_p(void *ptr)
440{
441 uint8_t *p = ptr;
442 uint32_t v1, v2;
443 v1 = ldl_le_p(p);
444 v2 = ldl_le_p(p + 4);
445 return v1 | ((uint64_t)v2 << 32);
446}
447
448static inline void stw_le_p(void *ptr, int v)
449{
450#ifdef __powerpc__
451 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
452#else
453 uint8_t *p = ptr;
454 p[0] = v;
455 p[1] = v >> 8;
456#endif
457}
458
459static inline void stl_le_p(void *ptr, int v)
460{
461#ifdef __powerpc__
462 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
463#else
464 uint8_t *p = ptr;
465 p[0] = v;
466 p[1] = v >> 8;
467 p[2] = v >> 16;
468 p[3] = v >> 24;
469#endif
470}
471
472static inline void stq_le_p(void *ptr, uint64_t v)
473{
474 uint8_t *p = ptr;
475 stl_le_p(p, (uint32_t)v);
476 stl_le_p(p + 4, v >> 32);
477}
478
479/* float access */
480
481static inline float32 ldfl_le_p(void *ptr)
482{
483 union {
484 float32 f;
485 uint32_t i;
486 } u;
487 u.i = ldl_le_p(ptr);
488 return u.f;
489}
490
491static inline void stfl_le_p(void *ptr, float32 v)
492{
493 union {
494 float32 f;
495 uint32_t i;
496 } u;
497 u.f = v;
498 stl_le_p(ptr, u.i);
499}
500
501static inline float64 ldfq_le_p(void *ptr)
502{
503 CPU_DoubleU u;
504 u.l.lower = ldl_le_p(ptr);
505 u.l.upper = ldl_le_p(ptr + 4);
506 return u.d;
507}
508
509static inline void stfq_le_p(void *ptr, float64 v)
510{
511 CPU_DoubleU u;
512 u.d = v;
513 stl_le_p(ptr, u.l.lower);
514 stl_le_p(ptr + 4, u.l.upper);
515}
516
517#else
518
519static inline int lduw_le_p(void *ptr)
520{
521 return *(uint16_t *)ptr;
522}
523
524static inline int ldsw_le_p(void *ptr)
525{
526 return *(int16_t *)ptr;
527}
528
529static inline int ldl_le_p(void *ptr)
530{
531 return *(uint32_t *)ptr;
532}
533
534static inline uint64_t ldq_le_p(void *ptr)
535{
536 return *(uint64_t *)ptr;
537}
538
539static inline void stw_le_p(void *ptr, int v)
540{
541 *(uint16_t *)ptr = v;
542}
543
544static inline void stl_le_p(void *ptr, int v)
545{
546 *(uint32_t *)ptr = v;
547}
548
549static inline void stq_le_p(void *ptr, uint64_t v)
550{
551 *(uint64_t *)ptr = v;
552}
553
554/* float access */
555
556static inline float32 ldfl_le_p(void *ptr)
557{
558 return *(float32 *)ptr;
559}
560
561static inline float64 ldfq_le_p(void *ptr)
562{
563 return *(float64 *)ptr;
564}
565
566static inline void stfl_le_p(void *ptr, float32 v)
567{
568 *(float32 *)ptr = v;
569}
570
571static inline void stfq_le_p(void *ptr, float64 v)
572{
573 *(float64 *)ptr = v;
574}
575#endif
576#endif /* !VBOX */
577
578#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
579
580#ifndef VBOX
581static inline int lduw_be_p(void *ptr)
582{
583#if defined(__i386__)
584 int val;
585 asm volatile ("movzwl %1, %0\n"
586 "xchgb %b0, %h0\n"
587 : "=q" (val)
588 : "m" (*(uint16_t *)ptr));
589 return val;
590#else
591 uint8_t *b = (uint8_t *) ptr;
592 return ((b[0] << 8) | b[1]);
593#endif
594}
595#else /* VBOX */
596DECLINLINE(int) lduw_be_p(void *ptr)
597{
598#if defined(__i386__) && !defined(_MSC_VER)
599 int val;
600 asm volatile ("movzwl %1, %0\n"
601 "xchgb %b0, %h0\n"
602 : "=q" (val)
603 : "m" (*(uint16_t *)ptr));
604 return val;
605#else
606 uint8_t *b = (uint8_t *) ptr;
607 return ((b[0] << 8) | b[1]);
608#endif
609}
610#endif
611
612#ifndef VBOX
613static inline int ldsw_be_p(void *ptr)
614{
615#if defined(__i386__)
616 int val;
617 asm volatile ("movzwl %1, %0\n"
618 "xchgb %b0, %h0\n"
619 : "=q" (val)
620 : "m" (*(uint16_t *)ptr));
621 return (int16_t)val;
622#else
623 uint8_t *b = (uint8_t *) ptr;
624 return (int16_t)((b[0] << 8) | b[1]);
625#endif
626}
627#else
628DECLINLINE(int) ldsw_be_p(void *ptr)
629{
630#if defined(__i386__) && !defined(_MSC_VER)
631 int val;
632 asm volatile ("movzwl %1, %0\n"
633 "xchgb %b0, %h0\n"
634 : "=q" (val)
635 : "m" (*(uint16_t *)ptr));
636 return (int16_t)val;
637#else
638 uint8_t *b = (uint8_t *) ptr;
639 return (int16_t)((b[0] << 8) | b[1]);
640#endif
641}
642#endif
643
644#ifndef VBOX
645static inline int ldl_be_p(void *ptr)
646{
647#if defined(__i386__) || defined(__x86_64__)
648 int val;
649 asm volatile ("movl %1, %0\n"
650 "bswap %0\n"
651 : "=r" (val)
652 : "m" (*(uint32_t *)ptr));
653 return val;
654#else
655 uint8_t *b = (uint8_t *) ptr;
656 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
657#endif
658}
659#else
660DECLINLINE(int) ldl_be_p(void *ptr)
661{
662#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
663 int val;
664 asm volatile ("movl %1, %0\n"
665 "bswap %0\n"
666 : "=r" (val)
667 : "m" (*(uint32_t *)ptr));
668 return val;
669#else
670 uint8_t *b = (uint8_t *) ptr;
671 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
672#endif
673}
674#endif
675
676#ifndef VBOX
677static inline uint64_t ldq_be_p(void *ptr)
678#else
679DECLINLINE(uint64_t) ldq_be_p(void *ptr)
680#endif
681{
682 uint32_t a,b;
683 a = ldl_be_p(ptr);
684 b = ldl_be_p((uint8_t*)ptr+4);
685 return (((uint64_t)a<<32)|b);
686}
687
688#ifndef VBOX
689static inline void stw_be_p(void *ptr, int v)
690{
691#if defined(__i386__)
692 asm volatile ("xchgb %b0, %h0\n"
693 "movw %w0, %1\n"
694 : "=q" (v)
695 : "m" (*(uint16_t *)ptr), "0" (v));
696#else
697 uint8_t *d = (uint8_t *) ptr;
698 d[0] = v >> 8;
699 d[1] = v;
700#endif
701}
702#else
703DECLINLINE(void) stw_be_p(void *ptr, int v)
704{
705#if defined(__i386__) && !defined(_MSC_VER)
706 asm volatile ("xchgb %b0, %h0\n"
707 "movw %w0, %1\n"
708 : "=q" (v)
709 : "m" (*(uint16_t *)ptr), "0" (v));
710#else
711 uint8_t *d = (uint8_t *) ptr;
712 d[0] = v >> 8;
713 d[1] = v;
714#endif
715}
716
717#endif /* VBOX */
718
719#ifndef VBOX
720static inline void stl_be_p(void *ptr, int v)
721{
722#if defined(__i386__) || defined(__x86_64__)
723 asm volatile ("bswap %0\n"
724 "movl %0, %1\n"
725 : "=r" (v)
726 : "m" (*(uint32_t *)ptr), "0" (v));
727#else
728 uint8_t *d = (uint8_t *) ptr;
729 d[0] = v >> 24;
730 d[1] = v >> 16;
731 d[2] = v >> 8;
732 d[3] = v;
733#endif
734}
735#else
736DECLINLINE(void) stl_be_p(void *ptr, int v)
737{
738#if !defined(_MSC_VER) && (defined(__i386__) || defined(__x86_64__))
739 asm volatile ("bswap %0\n"
740 "movl %0, %1\n"
741 : "=r" (v)
742 : "m" (*(uint32_t *)ptr), "0" (v));
743#else
744 uint8_t *d = (uint8_t *) ptr;
745 d[0] = v >> 24;
746 d[1] = v >> 16;
747 d[2] = v >> 8;
748 d[3] = v;
749#endif
750}
751#endif /* VBOX */
752
753#ifndef VBOX
754static inline void stq_be_p(void *ptr, uint64_t v)
755#else
756DECLINLINE(void) stq_be_p(void *ptr, uint64_t v)
757#endif
758{
759 stl_be_p(ptr, v >> 32);
760 stl_be_p((uint8_t*)ptr + 4, v);
761}
762
763/* float access */
764#ifndef VBOX
765static inline float32 ldfl_be_p(void *ptr)
766#else
767DECLINLINE(float32) ldfl_be_p(void *ptr)
768#endif
769{
770 union {
771 float32 f;
772 uint32_t i;
773 } u;
774 u.i = ldl_be_p(ptr);
775 return u.f;
776}
777
778#ifndef VBOX
779static inline void stfl_be_p(void *ptr, float32 v)
780#else
781DECLINLINE(void) stfl_be_p(void *ptr, float32 v)
782#endif
783{
784 union {
785 float32 f;
786 uint32_t i;
787 } u;
788 u.f = v;
789 stl_be_p(ptr, u.i);
790}
791
792#ifndef VBOX
793static inline float64 ldfq_be_p(void *ptr)
794#else
795DECLINLINE(float64) ldfq_be_p(void *ptr)
796#endif
797{
798 CPU_DoubleU u;
799 u.l.upper = ldl_be_p(ptr);
800 u.l.lower = ldl_be_p((uint8_t*)ptr + 4);
801 return u.d;
802}
803
804#ifndef VBOX
805static inline void stfq_be_p(void *ptr, float64 v)
806#else
807DECLINLINE(void) stfq_be_p(void *ptr, float64 v)
808#endif
809{
810 CPU_DoubleU u;
811 u.d = v;
812 stl_be_p(ptr, u.l.upper);
813 stl_be_p((uint8_t*)ptr + 4, u.l.lower);
814}
815
816#else
817
818static inline int lduw_be_p(void *ptr)
819{
820 return *(uint16_t *)ptr;
821}
822
823static inline int ldsw_be_p(void *ptr)
824{
825 return *(int16_t *)ptr;
826}
827
828static inline int ldl_be_p(void *ptr)
829{
830 return *(uint32_t *)ptr;
831}
832
833static inline uint64_t ldq_be_p(void *ptr)
834{
835 return *(uint64_t *)ptr;
836}
837
838static inline void stw_be_p(void *ptr, int v)
839{
840 *(uint16_t *)ptr = v;
841}
842
843static inline void stl_be_p(void *ptr, int v)
844{
845 *(uint32_t *)ptr = v;
846}
847
848static inline void stq_be_p(void *ptr, uint64_t v)
849{
850 *(uint64_t *)ptr = v;
851}
852
853/* float access */
854
855static inline float32 ldfl_be_p(void *ptr)
856{
857 return *(float32 *)ptr;
858}
859
860static inline float64 ldfq_be_p(void *ptr)
861{
862 return *(float64 *)ptr;
863}
864
865static inline void stfl_be_p(void *ptr, float32 v)
866{
867 *(float32 *)ptr = v;
868}
869
870static inline void stfq_be_p(void *ptr, float64 v)
871{
872 *(float64 *)ptr = v;
873}
874
875#endif
876
877/* target CPU memory access functions */
878#if defined(TARGET_WORDS_BIGENDIAN)
879#define lduw_p(p) lduw_be_p(p)
880#define ldsw_p(p) ldsw_be_p(p)
881#define ldl_p(p) ldl_be_p(p)
882#define ldq_p(p) ldq_be_p(p)
883#define ldfl_p(p) ldfl_be_p(p)
884#define ldfq_p(p) ldfq_be_p(p)
885#define stw_p(p, v) stw_be_p(p, v)
886#define stl_p(p, v) stl_be_p(p, v)
887#define stq_p(p, v) stq_be_p(p, v)
888#define stfl_p(p, v) stfl_be_p(p, v)
889#define stfq_p(p, v) stfq_be_p(p, v)
890#else
891#define lduw_p(p) lduw_le_p(p)
892#define ldsw_p(p) ldsw_le_p(p)
893#define ldl_p(p) ldl_le_p(p)
894#define ldq_p(p) ldq_le_p(p)
895#define ldfl_p(p) ldfl_le_p(p)
896#define ldfq_p(p) ldfq_le_p(p)
897#define stw_p(p, v) stw_le_p(p, v)
898#define stl_p(p, v) stl_le_p(p, v)
899#define stq_p(p, v) stq_le_p(p, v)
900#define stfl_p(p, v) stfl_le_p(p, v)
901#define stfq_p(p, v) stfq_le_p(p, v)
902#endif
903
904/* MMU memory access macros */
905
906#if defined(CONFIG_USER_ONLY)
907/* On some host systems the guest address space is reserved on the host.
908 * This allows the guest address space to be offset to a convenient location.
909 */
910//#define GUEST_BASE 0x20000000
911#define GUEST_BASE 0
912
913/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
914#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
915#define h2g(x) ((target_ulong)(x - GUEST_BASE))
916#define saddr(x) g2h(x)
917#define laddr(x) g2h(x)
918
919#else /* !CONFIG_USER_ONLY */
920/* NOTE: we use double casts if pointers and target_ulong have
921 different sizes */
922#define saddr(x) (uint8_t *)(long)(x)
923#define laddr(x) (uint8_t *)(long)(x)
924#endif
925
926#define ldub_raw(p) ldub_p(laddr((p)))
927#define ldsb_raw(p) ldsb_p(laddr((p)))
928#define lduw_raw(p) lduw_p(laddr((p)))
929#define ldsw_raw(p) ldsw_p(laddr((p)))
930#define ldl_raw(p) ldl_p(laddr((p)))
931#define ldq_raw(p) ldq_p(laddr((p)))
932#define ldfl_raw(p) ldfl_p(laddr((p)))
933#define ldfq_raw(p) ldfq_p(laddr((p)))
934#define stb_raw(p, v) stb_p(saddr((p)), v)
935#define stw_raw(p, v) stw_p(saddr((p)), v)
936#define stl_raw(p, v) stl_p(saddr((p)), v)
937#define stq_raw(p, v) stq_p(saddr((p)), v)
938#define stfl_raw(p, v) stfl_p(saddr((p)), v)
939#define stfq_raw(p, v) stfq_p(saddr((p)), v)
940
941
942#if defined(CONFIG_USER_ONLY)
943
944/* if user mode, no other memory access functions */
945#define ldub(p) ldub_raw(p)
946#define ldsb(p) ldsb_raw(p)
947#define lduw(p) lduw_raw(p)
948#define ldsw(p) ldsw_raw(p)
949#define ldl(p) ldl_raw(p)
950#define ldq(p) ldq_raw(p)
951#define ldfl(p) ldfl_raw(p)
952#define ldfq(p) ldfq_raw(p)
953#define stb(p, v) stb_raw(p, v)
954#define stw(p, v) stw_raw(p, v)
955#define stl(p, v) stl_raw(p, v)
956#define stq(p, v) stq_raw(p, v)
957#define stfl(p, v) stfl_raw(p, v)
958#define stfq(p, v) stfq_raw(p, v)
959
960#define ldub_code(p) ldub_raw(p)
961#define ldsb_code(p) ldsb_raw(p)
962#define lduw_code(p) lduw_raw(p)
963#define ldsw_code(p) ldsw_raw(p)
964#define ldl_code(p) ldl_raw(p)
965
966#define ldub_kernel(p) ldub_raw(p)
967#define ldsb_kernel(p) ldsb_raw(p)
968#define lduw_kernel(p) lduw_raw(p)
969#define ldsw_kernel(p) ldsw_raw(p)
970#define ldl_kernel(p) ldl_raw(p)
971#define ldfl_kernel(p) ldfl_raw(p)
972#define ldfq_kernel(p) ldfq_raw(p)
973#define stb_kernel(p, v) stb_raw(p, v)
974#define stw_kernel(p, v) stw_raw(p, v)
975#define stl_kernel(p, v) stl_raw(p, v)
976#define stq_kernel(p, v) stq_raw(p, v)
977#define stfl_kernel(p, v) stfl_raw(p, v)
978#define stfq_kernel(p, vt) stfq_raw(p, v)
979
980#endif /* defined(CONFIG_USER_ONLY) */
981
982/* page related stuff */
983
984#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
985#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
986#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
987
988/* ??? These should be the larger of unsigned long and target_ulong. */
989extern unsigned long qemu_real_host_page_size;
990extern unsigned long qemu_host_page_bits;
991extern unsigned long qemu_host_page_size;
992extern unsigned long qemu_host_page_mask;
993
994#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
995
996/* same as PROT_xxx */
997#define PAGE_READ 0x0001
998#define PAGE_WRITE 0x0002
999#define PAGE_EXEC 0x0004
1000#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
1001#define PAGE_VALID 0x0008
1002/* original state of the write flag (used when tracking self-modifying
1003 code */
1004#define PAGE_WRITE_ORG 0x0010
1005#define PAGE_RESERVED 0x0020
1006
1007void page_dump(FILE *f);
1008int page_get_flags(target_ulong address);
1009void page_set_flags(target_ulong start, target_ulong end, int flags);
1010int page_check_range(target_ulong start, target_ulong len, int flags);
1011void page_unprotect_range(target_ulong data, target_ulong data_size);
1012
1013#define SINGLE_CPU_DEFINES
1014#ifdef SINGLE_CPU_DEFINES
1015
1016#if defined(TARGET_I386)
1017
1018#define CPUState CPUX86State
1019#define cpu_init cpu_x86_init
1020#define cpu_exec cpu_x86_exec
1021#define cpu_gen_code cpu_x86_gen_code
1022#define cpu_signal_handler cpu_x86_signal_handler
1023
1024#elif defined(TARGET_ARM)
1025
1026#define CPUState CPUARMState
1027#define cpu_init cpu_arm_init
1028#define cpu_exec cpu_arm_exec
1029#define cpu_gen_code cpu_arm_gen_code
1030#define cpu_signal_handler cpu_arm_signal_handler
1031
1032#elif defined(TARGET_SPARC)
1033
1034#define CPUState CPUSPARCState
1035#define cpu_init cpu_sparc_init
1036#define cpu_exec cpu_sparc_exec
1037#define cpu_gen_code cpu_sparc_gen_code
1038#define cpu_signal_handler cpu_sparc_signal_handler
1039
1040#elif defined(TARGET_PPC)
1041
1042#define CPUState CPUPPCState
1043#define cpu_init cpu_ppc_init
1044#define cpu_exec cpu_ppc_exec
1045#define cpu_gen_code cpu_ppc_gen_code
1046#define cpu_signal_handler cpu_ppc_signal_handler
1047
1048#elif defined(TARGET_M68K)
1049#define CPUState CPUM68KState
1050#define cpu_init cpu_m68k_init
1051#define cpu_exec cpu_m68k_exec
1052#define cpu_gen_code cpu_m68k_gen_code
1053#define cpu_signal_handler cpu_m68k_signal_handler
1054
1055#elif defined(TARGET_MIPS)
1056#define CPUState CPUMIPSState
1057#define cpu_init cpu_mips_init
1058#define cpu_exec cpu_mips_exec
1059#define cpu_gen_code cpu_mips_gen_code
1060#define cpu_signal_handler cpu_mips_signal_handler
1061
1062#elif defined(TARGET_SH4)
1063#define CPUState CPUSH4State
1064#define cpu_init cpu_sh4_init
1065#define cpu_exec cpu_sh4_exec
1066#define cpu_gen_code cpu_sh4_gen_code
1067#define cpu_signal_handler cpu_sh4_signal_handler
1068
1069#else
1070
1071#error unsupported target CPU
1072
1073#endif
1074
1075#endif /* SINGLE_CPU_DEFINES */
1076
1077void cpu_dump_state(CPUState *env, FILE *f,
1078 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1079 int flags);
1080
1081DECLNORETURN(void) cpu_abort(CPUState *env, const char *fmt, ...);
1082extern CPUState *first_cpu;
1083extern CPUState *cpu_single_env;
1084extern int64_t qemu_icount;
1085extern int use_icount;
1086
1087#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
1088#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
1089#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
1090#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
1091#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
1092#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
1093#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
1094#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
1095#define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
1096#define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
1097
1098#ifdef VBOX
1099/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
1100#define CPU_INTERRUPT_SINGLE_INSTR 0x0400
1101/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
1102#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0800
1103/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
1104#define CPU_INTERRUPT_RC 0x1000
1105/** Exit current TB to process an external interrupt request (also in op.c!!) */
1106#define CPU_INTERRUPT_EXTERNAL_EXIT 0x2000
1107/** Exit current TB to process an external interrupt request (also in op.c!!) */
1108#define CPU_INTERRUPT_EXTERNAL_HARD 0x4000
1109/** Exit current TB to process an external interrupt request (also in op.c!!) */
1110#define CPU_INTERRUPT_EXTERNAL_TIMER 0x8000
1111/** Exit current TB to process an external interrupt request (also in op.c!!) */
1112#define CPU_INTERRUPT_EXTERNAL_DMA 0x10000
1113#endif /* VBOX */
1114void cpu_interrupt(CPUState *s, int mask);
1115void cpu_reset_interrupt(CPUState *env, int mask);
1116
1117int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type);
1118int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
1119void cpu_watchpoint_remove_all(CPUState *env);
1120int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
1121int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
1122void cpu_breakpoint_remove_all(CPUState *env);
1123
1124#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1125#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1126#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1127
1128void cpu_single_step(CPUState *env, int enabled);
1129void cpu_reset(CPUState *s);
1130
1131/* Return the physical page corresponding to a virtual one. Use it
1132 only for debugging because no protection checks are done. Return -1
1133 if no page found. */
1134target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
1135
1136#define CPU_LOG_TB_OUT_ASM (1 << 0)
1137#define CPU_LOG_TB_IN_ASM (1 << 1)
1138#define CPU_LOG_TB_OP (1 << 2)
1139#define CPU_LOG_TB_OP_OPT (1 << 3)
1140#define CPU_LOG_INT (1 << 4)
1141#define CPU_LOG_EXEC (1 << 5)
1142#define CPU_LOG_PCALL (1 << 6)
1143#define CPU_LOG_IOPORT (1 << 7)
1144#define CPU_LOG_TB_CPU (1 << 8)
1145
1146/* define log items */
1147typedef struct CPULogItem {
1148 int mask;
1149 const char *name;
1150 const char *help;
1151} CPULogItem;
1152
1153extern CPULogItem cpu_log_items[];
1154
1155void cpu_set_log(int log_flags);
1156void cpu_set_log_filename(const char *filename);
1157int cpu_str_to_log_mask(const char *str);
1158
1159/* IO ports API */
1160
1161/* NOTE: as these functions may be even used when there is an isa
1162 brige on non x86 targets, we always defined them */
1163#ifndef NO_CPU_IO_DEFS
1164void cpu_outb(CPUState *env, int addr, int val);
1165void cpu_outw(CPUState *env, int addr, int val);
1166void cpu_outl(CPUState *env, int addr, int val);
1167int cpu_inb(CPUState *env, int addr);
1168int cpu_inw(CPUState *env, int addr);
1169int cpu_inl(CPUState *env, int addr);
1170#endif
1171
1172/* address in the RAM (different from a physical address) */
1173#ifdef USE_KQEMU
1174typedef uint32_t ram_addr_t;
1175#else
1176typedef unsigned long ram_addr_t;
1177#endif
1178
1179/* memory API */
1180
1181#ifndef VBOX
1182extern int phys_ram_size;
1183extern int phys_ram_fd;
1184extern int phys_ram_size;
1185#else /* VBOX */
1186extern RTGCPHYS phys_ram_size;
1187/** This is required for bounds checking the phys_ram_dirty accesses. */
1188extern RTGCPHYS phys_ram_dirty_size;
1189#endif /* VBOX */
1190#if !defined(VBOX)
1191extern uint8_t *phys_ram_base;
1192#endif
1193extern uint8_t *phys_ram_dirty;
1194
1195/* physical memory access */
1196
1197/* MMIO pages are identified by a combination of an IO device index and
1198 3 flags. The ROMD code stores the page ram offset in iotlb entry,
1199 so only a limited number of ids are avaiable. */
1200
1201#define IO_MEM_SHIFT 3
1202#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
1203
1204#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
1205#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
1206#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
1207#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
1208#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
1209#define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
1210#endif
1211
1212/* Acts like a ROM when read and like a device when written. */
1213#define IO_MEM_ROMD (1)
1214#define IO_MEM_SUBPAGE (2)
1215#define IO_MEM_SUBWIDTH (4)
1216
1217/* Flags stored in the low bits of the TLB virtual address. These are
1218 defined so that fast path ram access is all zeros. */
1219/* Zero if TLB entry is valid. */
1220#define TLB_INVALID_MASK (1 << 3)
1221/* Set if TLB entry references a clean RAM page. The iotlb entry will
1222 contain the page physical address. */
1223#define TLB_NOTDIRTY (1 << 4)
1224/* Set if TLB entry is an IO callback. */
1225#define TLB_MMIO (1 << 5)
1226
1227typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
1228typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
1229
1230void cpu_register_physical_memory(target_phys_addr_t start_addr,
1231 ram_addr_t size,
1232 ram_addr_t phys_offset);
1233uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
1234ram_addr_t qemu_ram_alloc(ram_addr_t);
1235void qemu_ram_free(ram_addr_t addr);
1236int cpu_register_io_memory(int io_index,
1237 CPUReadMemoryFunc **mem_read,
1238 CPUWriteMemoryFunc **mem_write,
1239 void *opaque);
1240CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
1241CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
1242
1243void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1244 int len, int is_write);
1245#ifndef VBOX
1246static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1247 uint8_t *buf, int len)
1248#else
1249DECLINLINE(void) cpu_physical_memory_read(target_phys_addr_t addr,
1250 uint8_t *buf, int len)
1251#endif
1252{
1253 cpu_physical_memory_rw(addr, buf, len, 0);
1254}
1255#ifndef VBOX
1256static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1257 const uint8_t *buf, int len)
1258#else
1259DECLINLINE(void) cpu_physical_memory_write(target_phys_addr_t addr,
1260 const uint8_t *buf, int len)
1261#endif
1262{
1263 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1264}
1265uint32_t ldub_phys(target_phys_addr_t addr);
1266uint32_t lduw_phys(target_phys_addr_t addr);
1267uint32_t ldl_phys(target_phys_addr_t addr);
1268uint64_t ldq_phys(target_phys_addr_t addr);
1269void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1270void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
1271void stb_phys(target_phys_addr_t addr, uint32_t val);
1272void stw_phys(target_phys_addr_t addr, uint32_t val);
1273void stl_phys(target_phys_addr_t addr, uint32_t val);
1274void stq_phys(target_phys_addr_t addr, uint64_t val);
1275
1276void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1277 const uint8_t *buf, int len);
1278int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1279 uint8_t *buf, int len, int is_write);
1280
1281#define VGA_DIRTY_FLAG 0x01
1282#define CODE_DIRTY_FLAG 0x02
1283#define KQEMU_DIRTY_FLAG 0x04
1284#define MIGRATION_DIRTY_FLAG 0x08
1285
1286/* read dirty bit (return 0 or 1) */
1287#ifndef VBOX
1288static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1289{
1290 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1291}
1292#else
1293DECLINLINE(int) cpu_physical_memory_is_dirty(ram_addr_t addr)
1294{
1295 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1296 {
1297 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1298 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1299 return 0;
1300 }
1301 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1302}
1303#endif
1304
1305#ifndef VBOX
1306static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1307 int dirty_flags)
1308{
1309 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1310}
1311#else
1312DECLINLINE(int) cpu_physical_memory_get_dirty(ram_addr_t addr,
1313 int dirty_flags)
1314{
1315 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1316 {
1317 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1318 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1319 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1320 }
1321 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1322}
1323#endif
1324
1325#ifndef VBOX
1326static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1327{
1328 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1329}
1330#else
1331DECLINLINE(void) cpu_physical_memory_set_dirty(ram_addr_t addr)
1332{
1333 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1334 {
1335 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1336 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1337 return;
1338 }
1339 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1340}
1341#endif
1342
1343void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1344 int dirty_flags);
1345void cpu_tlb_update_dirty(CPUState *env);
1346
1347int cpu_physical_memory_set_dirty_tracking(int enable);
1348
1349int cpu_physical_memory_get_dirty_tracking(void);
1350
1351void dump_exec_info(FILE *f,
1352 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1353
1354/*******************************************/
1355/* host CPU ticks (if available) */
1356
1357#ifdef VBOX
1358
1359DECLINLINE(int64_t) cpu_get_real_ticks(void)
1360{
1361 return ASMReadTSC();
1362}
1363
1364#elif defined(__powerpc__)
1365
1366static inline uint32_t get_tbl(void)
1367{
1368 uint32_t tbl;
1369 asm volatile("mftb %0" : "=r" (tbl));
1370 return tbl;
1371}
1372
1373static inline uint32_t get_tbu(void)
1374{
1375 uint32_t tbl;
1376 asm volatile("mftbu %0" : "=r" (tbl));
1377 return tbl;
1378}
1379
1380static inline int64_t cpu_get_real_ticks(void)
1381{
1382 uint32_t l, h, h1;
1383 /* NOTE: we test if wrapping has occurred */
1384 do {
1385 h = get_tbu();
1386 l = get_tbl();
1387 h1 = get_tbu();
1388 } while (h != h1);
1389 return ((int64_t)h << 32) | l;
1390}
1391
1392#elif defined(__i386__)
1393
1394static inline int64_t cpu_get_real_ticks(void)
1395{
1396 int64_t val;
1397 asm volatile ("rdtsc" : "=A" (val));
1398 return val;
1399}
1400
1401#elif defined(__x86_64__)
1402
1403static inline int64_t cpu_get_real_ticks(void)
1404{
1405 uint32_t low,high;
1406 int64_t val;
1407 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1408 val = high;
1409 val <<= 32;
1410 val |= low;
1411 return val;
1412}
1413
1414#elif defined(__ia64)
1415
1416static inline int64_t cpu_get_real_ticks(void)
1417{
1418 int64_t val;
1419 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1420 return val;
1421}
1422
1423#elif defined(__s390__)
1424
1425static inline int64_t cpu_get_real_ticks(void)
1426{
1427 int64_t val;
1428 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1429 return val;
1430}
1431
1432#elif defined(__sparc_v9__)
1433
1434static inline int64_t cpu_get_real_ticks (void)
1435{
1436#if defined(_LP64)
1437 uint64_t rval;
1438 asm volatile("rd %%tick,%0" : "=r"(rval));
1439 return rval;
1440#else
1441 union {
1442 uint64_t i64;
1443 struct {
1444 uint32_t high;
1445 uint32_t low;
1446 } i32;
1447 } rval;
1448 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1449 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1450 return rval.i64;
1451#endif
1452}
1453#else
1454/* The host CPU doesn't have an easily accessible cycle counter.
1455 Just return a monotonically increasing vlue. This will be totally wrong,
1456 but hopefully better than nothing. */
1457static inline int64_t cpu_get_real_ticks (void)
1458{
1459 static int64_t ticks = 0;
1460 return ticks++;
1461}
1462#endif
1463
1464/* profiling */
1465#ifdef CONFIG_PROFILER
1466static inline int64_t profile_getclock(void)
1467{
1468 return cpu_get_real_ticks();
1469}
1470
1471extern int64_t kqemu_time, kqemu_time_start;
1472extern int64_t qemu_time, qemu_time_start;
1473extern int64_t tlb_flush_time;
1474extern int64_t kqemu_exec_count;
1475extern int64_t dev_time;
1476extern int64_t kqemu_ret_int_count;
1477extern int64_t kqemu_ret_excp_count;
1478extern int64_t kqemu_ret_intr_count;
1479
1480#endif
1481
1482#ifdef VBOX
1483void tb_invalidate_virt(CPUState *env, uint32_t eip);
1484#endif /* VBOX */
1485
1486#endif /* CPU_ALL_H */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette