cpu-defs.h@ 13312

Last change on this file since 13312 was 13230, checked in by vboxsync, 16 years ago
further new recompiler work
Property svn:eol-style set to `native`
File size: 13.5 KB

Line
1	/*
2	* common defines for all CPUs
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/*
22	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
24	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25	* a choice of LGPL license versions is made available with the language indicating
26	* that LGPLv2 or any later version may be used, or where a choice of which version
27	* of the LGPL is applied is otherwise unspecified.
28	*/
29	#ifndef CPU_DEFS_H
30	#define CPU_DEFS_H
31
32	#include "config.h"
33	#include <setjmp.h>
34	#include <inttypes.h>
35	#include "osdep.h"
36
37	#ifndef TARGET_LONG_BITS
38	#error TARGET_LONG_BITS must be defined before including this header
39	#endif
40
41	#ifndef TARGET_PHYS_ADDR_BITS
42	#if TARGET_LONG_BITS >= HOST_LONG_BITS
43	#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
44	#else
45	#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
46	#endif
47	#endif
48
49	#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
50
51	/* target_ulong is the type of a virtual address */
52	#if TARGET_LONG_SIZE == 4
53	typedef int32_t target_long;
54	typedef uint32_t target_ulong;
55	#define TARGET_FMT_lx "%08x"
56	#define TARGET_FMT_ld "%d"
57	#define TARGET_FMT_lu "%u"
58	#elif TARGET_LONG_SIZE == 8
59	typedef int64_t target_long;
60	typedef uint64_t target_ulong;
61	#define TARGET_FMT_lx "%016" PRIx64
62	#define TARGET_FMT_ld "%" PRId64
63	#define TARGET_FMT_lu "%" PRIu64
64	#else
65	#error TARGET_LONG_SIZE undefined
66	#endif
67
68	/* target_phys_addr_t is the type of a physical address (its size can
69	be different from 'target_ulong'). We have sizeof(target_phys_addr)
70	= max(sizeof(unsigned long),
71	sizeof(size_of_target_physical_address)) because we must pass a
72	host pointer to memory operations in some cases */
73
74	#if TARGET_PHYS_ADDR_BITS == 32
75	typedef uint32_t target_phys_addr_t;
76	#define TARGET_FMT_plx "%08x"
77	#elif TARGET_PHYS_ADDR_BITS == 64
78	typedef uint64_t target_phys_addr_t;
79	#define TARGET_FMT_plx "%016" PRIx64
80	#else
81	#error TARGET_PHYS_ADDR_BITS undefined
82	#endif
83
84	#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
85
86	#define EXCP_INTERRUPT 0x10000 /* async interruption */
87	#define EXCP_HLT 0x10001 /* hlt instruction reached */
88	#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
89	#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
90	#if defined(VBOX)
91	#define EXCP_EXECUTE_RAW 0x11024 /* execute raw mode. */
92	#define EXCP_EXECUTE_HWACC 0x11025 /* execute hardware accelerated raw mode. */
93	#define EXCP_SINGLE_INSTR 0x11026 /* executed single instruction. */
94	#define EXCP_RC 0x11027 /* a EM rc was raised (VMR3Reset/Suspend/PowerOff). */
95	#endif /* VBOX */
96	#define MAX_BREAKPOINTS 32
97	#define MAX_WATCHPOINTS 32
98
99	#define TB_JMP_CACHE_BITS 12
100	#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
101
102	/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
103	addresses on the same page. The top bits are the same. This allows
104	TLB invalidation to quickly clear a subset of the hash table. */
105	#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
106	#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
107	#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
108	#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
109
110	#define CPU_TLB_BITS 8
111	#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
112
113	#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
114	#define CPU_TLB_ENTRY_BITS 4
115	#else
116	#define CPU_TLB_ENTRY_BITS 5
117	#endif
118
119	typedef struct CPUTLBEntry {
120	/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
121	bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
122	go directly to ram.
123	bit 3 : indicates that the entry is invalid
124	bit 2..0 : zero
125	*/
126	target_ulong addr_read;
127	target_ulong addr_write;
128	target_ulong addr_code;
129	/* Addend to virtual address to get physical address. IO accesses
130	use the correcponding iotlb value. */
131	#if TARGET_PHYS_ADDR_BITS == 64
132	/* on i386 Linux make sure it is aligned */
133	target_phys_addr_t addend __attribute__((aligned(8)));
134	#else
135	target_phys_addr_t addend;
136	#endif
137	/* padding to get a power of two size */
138	uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
139	(sizeof(target_ulong) * 3 +
140	((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
141	sizeof(target_phys_addr_t))];
142	} CPUTLBEntry;
143
144	#ifdef WORDS_BIGENDIAN
145	typedef struct icount_decr_u16 {
146	uint16_t high;
147	uint16_t low;
148	} icount_decr_u16;
149	#else
150	typedef struct icount_decr_u16 {
151	uint16_t low;
152	uint16_t high;
153	} icount_decr_u16;
154	#endif
155
156
157	#define CPU_TEMP_BUF_NLONGS 128
158	#ifdef VBOX
159	struct TCGContext;
160
161	#define CPU_COMMON \
162	struct TranslationBlock current_tb; / currently executing TB */ \
163	/* soft mmu support */ \
164	/* in order to avoid passing too many arguments to the MMIO \
165	helpers, we store some rarely used information in the CPU \
166	context) */ \
167	unsigned long mem_io_pc; /* host pc at which the memory was \
168	accessed */ \
169	target_ulong mem_io_vaddr; /* target virtual addr at which the \
170	memory was accessed */ \
171	uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
172	uint32_t interrupt_request; \
173	/* The meaning of the MMU modes is defined in the target code. */ \
174	CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
175	target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
176	struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
177	/* buffer for temporaries in the code generator */ \
178	long temp_buf[CPU_TEMP_BUF_NLONGS]; \
179	\
180	int64_t icount_extra; /* Instructions until next timer event. */ \
181	/* Number of cycles left, with interrupt flag in high bit. \
182	This allows a single read-compare-cbranch-write sequence to test \
183	for both decrementer underflow and exceptions. */ \
184	union { \
185	uint32_t u32; \
186	icount_decr_u16 u16; \
187	} icount_decr; \
188	uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
189	\
190	/* from this point: preserved by CPU reset */ \
191	/* ice debug support */ \
192	target_ulong breakpoints[MAX_BREAKPOINTS]; \
193	int nb_breakpoints; \
194	int singlestep_enabled; \
195	\
196	struct { \
197	target_ulong vaddr; \
198	int type; /* PAGE_READ/PAGE_WRITE */ \
199	} watchpoint[MAX_WATCHPOINTS]; \
200	int nb_watchpoints; \
201	int watchpoint_hit; \
202	\
203	/* Core interrupt code */ \
204	jmp_buf jmp_env; \
205	int exception_index; \
206	\
207	int user_mode_only; \
208	\
209	void next_cpu; / next CPU sharing TB cache */ \
210	int cpu_index; /* CPU index (informative) */ \
211	int running; /* Nonzero if cpu is currently running(usermode). */ \
212	/* user data */ \
213	void *opaque; \
214	\
215	const char *cpu_model_str; \
216	/* Codegenerator context */ \
217	struct TCGContext *tcg_context;
218	#else
219
220	#define CPU_COMMON \
221	struct TranslationBlock current_tb; / currently executing TB */ \
222	/* soft mmu support */ \
223	/* in order to avoid passing too many arguments to the MMIO \
224	helpers, we store some rarely used information in the CPU \
225	context) */ \
226	unsigned long mem_io_pc; /* host pc at which the memory was \
227	accessed */ \
228	target_ulong mem_io_vaddr; /* target virtual addr at which the \
229	memory was accessed */ \
230	uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
231	uint32_t interrupt_request; \
232	/* The meaning of the MMU modes is defined in the target code. */ \
233	CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
234	target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
235	struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
236	/* buffer for temporaries in the code generator */ \
237	long temp_buf[CPU_TEMP_BUF_NLONGS]; \
238	\
239	int64_t icount_extra; /* Instructions until next timer event. */ \
240	/* Number of cycles left, with interrupt flag in high bit. \
241	This allows a single read-compare-cbranch-write sequence to test \
242	for both decrementer underflow and exceptions. */ \
243	union { \
244	uint32_t u32; \
245	icount_decr_u16 u16; \
246	} icount_decr; \
247	uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
248	\
249	/* from this point: preserved by CPU reset */ \
250	/* ice debug support */ \
251	target_ulong breakpoints[MAX_BREAKPOINTS]; \
252	int nb_breakpoints; \
253	int singlestep_enabled; \
254	\
255	struct { \
256	target_ulong vaddr; \
257	int type; /* PAGE_READ/PAGE_WRITE */ \
258	} watchpoint[MAX_WATCHPOINTS]; \
259	int nb_watchpoints; \
260	int watchpoint_hit; \
261	\
262	/* Core interrupt code */ \
263	jmp_buf jmp_env; \
264	int exception_index; \
265	\
266	int user_mode_only; \
267	\
268	void next_cpu; / next CPU sharing TB cache */ \
269	int cpu_index; /* CPU index (informative) */ \
270	int running; /* Nonzero if cpu is currently running(usermode). */ \
271	/* user data */ \
272	void *opaque; \
273	\
274	const char *cpu_model_str;
275	#endif
276
277	#endif

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source: vbox/trunk/src/recompiler_new/cpu-defs.h@ 13312

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