VirtualBox

source: vbox/trunk/src/recompiler_new/exec.c@ 16469

Last change on this file since 16469 was 15761, checked in by vboxsync, 16 years ago

REM: implemented fully working VA in TLB, enabled by default, cleanups
  • Property svn:eol-style set to native
File size: 111.7 KB
Line 
1/*
2 * virtual page mapping and translated block handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#include "config.h"
30#ifndef VBOX
31#ifdef _WIN32
32#include <windows.h>
33#else
34#include <sys/types.h>
35#include <sys/mman.h>
36#endif
37#include <stdlib.h>
38#include <stdio.h>
39#include <stdarg.h>
40#include <string.h>
41#include <errno.h>
42#include <unistd.h>
43#include <inttypes.h>
44#else /* VBOX */
45# include <stdlib.h>
46# include <stdio.h>
47# include <iprt/alloc.h>
48# include <iprt/string.h>
49# include <iprt/param.h>
50# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
51#endif /* VBOX */
52
53#include "cpu.h"
54#include "exec-all.h"
55#if defined(CONFIG_USER_ONLY)
56#include <qemu.h>
57#endif
58
59//#define DEBUG_TB_INVALIDATE
60//#define DEBUG_FLUSH
61//#define DEBUG_TLB
62//#define DEBUG_UNASSIGNED
63
64/* make various TB consistency checks */
65//#define DEBUG_TB_CHECK
66//#define DEBUG_TLB_CHECK
67
68#if !defined(CONFIG_USER_ONLY)
69/* TB consistency checks only implemented for usermode emulation. */
70#undef DEBUG_TB_CHECK
71#endif
72
73#define SMC_BITMAP_USE_THRESHOLD 10
74
75#define MMAP_AREA_START 0x00000000
76#define MMAP_AREA_END 0xa8000000
77
78#if defined(TARGET_SPARC64)
79#define TARGET_PHYS_ADDR_SPACE_BITS 41
80#elif defined(TARGET_SPARC)
81#define TARGET_PHYS_ADDR_SPACE_BITS 36
82#elif defined(TARGET_ALPHA)
83#define TARGET_PHYS_ADDR_SPACE_BITS 42
84#define TARGET_VIRT_ADDR_SPACE_BITS 42
85#elif defined(TARGET_PPC64)
86#define TARGET_PHYS_ADDR_SPACE_BITS 42
87#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
88#define TARGET_PHYS_ADDR_SPACE_BITS 42
89#elif defined(TARGET_I386) && !defined(USE_KQEMU)
90#define TARGET_PHYS_ADDR_SPACE_BITS 36
91#else
92/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
93#define TARGET_PHYS_ADDR_SPACE_BITS 32
94#endif
95
96static TranslationBlock *tbs;
97int code_gen_max_blocks;
98TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
99static int nb_tbs;
100/* any access to the tbs or the page table must use this lock */
101spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
102
103#ifndef VBOX
104#if defined(__arm__) || defined(__sparc_v9__)
105/* The prologue must be reachable with a direct jump. ARM and Sparc64
106 have limited branch ranges (possibly also PPC) so place it in a
107 section close to code segment. */
108#define code_gen_section \
109 __attribute__((__section__(".gen_code"))) \
110 __attribute__((aligned (32)))
111#else
112#define code_gen_section \
113 __attribute__((aligned (32)))
114#endif
115uint8_t code_gen_prologue[1024] code_gen_section;
116
117#else /* VBOX */
118extern uint8_t* code_gen_prologue;
119#endif /* VBOX */
120
121static uint8_t *code_gen_buffer;
122static unsigned long code_gen_buffer_size;
123/* threshold to flush the translated code buffer */
124static unsigned long code_gen_buffer_max_size;
125uint8_t *code_gen_ptr;
126
127#ifndef VBOX
128#if !defined(CONFIG_USER_ONLY)
129ram_addr_t phys_ram_size;
130int phys_ram_fd;
131uint8_t *phys_ram_base;
132uint8_t *phys_ram_dirty;
133static int in_migration;
134static ram_addr_t phys_ram_alloc_offset = 0;
135#endif
136#else /* VBOX */
137RTGCPHYS phys_ram_size;
138/* we have memory ranges (the high PC-BIOS mapping) which
139 causes some pages to fall outside the dirty map here. */
140uint32_t phys_ram_dirty_size;
141#endif /* VBOX */
142#if !defined(VBOX)
143uint8_t *phys_ram_base;
144#endif
145uint8_t *phys_ram_dirty;
146
147CPUState *first_cpu;
148/* current CPU in the current thread. It is only valid inside
149 cpu_exec() */
150CPUState *cpu_single_env;
151/* 0 = Do not count executed instructions.
152 1 = Precise instruction counting.
153 2 = Adaptive rate instruction counting. */
154int use_icount = 0;
155/* Current instruction counter. While executing translated code this may
156 include some instructions that have not yet been executed. */
157int64_t qemu_icount;
158
159typedef struct PageDesc {
160 /* list of TBs intersecting this ram page */
161 TranslationBlock *first_tb;
162 /* in order to optimize self modifying code, we count the number
163 of lookups we do to a given page to use a bitmap */
164 unsigned int code_write_count;
165 uint8_t *code_bitmap;
166#if defined(CONFIG_USER_ONLY)
167 unsigned long flags;
168#endif
169} PageDesc;
170
171typedef struct PhysPageDesc {
172 /* offset in host memory of the page + io_index in the low 12 bits */
173 ram_addr_t phys_offset;
174} PhysPageDesc;
175
176#define L2_BITS 10
177#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
178/* XXX: this is a temporary hack for alpha target.
179 * In the future, this is to be replaced by a multi-level table
180 * to actually be able to handle the complete 64 bits address space.
181 */
182#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
183#else
184#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
185#endif
186
187#define L1_SIZE (1 << L1_BITS)
188#define L2_SIZE (1 << L2_BITS)
189
190static void io_mem_init(void);
191
192unsigned long qemu_real_host_page_size;
193unsigned long qemu_host_page_bits;
194unsigned long qemu_host_page_size;
195unsigned long qemu_host_page_mask;
196
197/* XXX: for system emulation, it could just be an array */
198static PageDesc *l1_map[L1_SIZE];
199static PhysPageDesc **l1_phys_map;
200
201#if !defined(CONFIG_USER_ONLY)
202static void io_mem_init(void);
203
204/* io memory support */
205CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
206CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
207void *io_mem_opaque[IO_MEM_NB_ENTRIES];
208static int io_mem_nb;
209static int io_mem_watch;
210#endif
211
212#ifndef VBOX
213/* log support */
214static const char *logfilename = "/tmp/qemu.log";
215#endif /* !VBOX */
216FILE *logfile;
217int loglevel;
218#ifndef VBOX
219static int log_append = 0;
220#endif
221
222/* statistics */
223static int tlb_flush_count;
224static int tb_flush_count;
225#ifndef VBOX
226static int tb_phys_invalidate_count;
227#endif /* !VBOX */
228
229#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
230typedef struct subpage_t {
231 target_phys_addr_t base;
232 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
233 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
234 void *opaque[TARGET_PAGE_SIZE][2][4];
235} subpage_t;
236
237
238#ifndef VBOX
239#ifdef _WIN32
240static void map_exec(void *addr, long size)
241{
242 DWORD old_protect;
243 VirtualProtect(addr, size,
244 PAGE_EXECUTE_READWRITE, &old_protect);
245
246}
247#else
248static void map_exec(void *addr, long size)
249{
250 unsigned long start, end, page_size;
251
252 page_size = getpagesize();
253 start = (unsigned long)addr;
254 start &= ~(page_size - 1);
255
256 end = (unsigned long)addr + size;
257 end += page_size - 1;
258 end &= ~(page_size - 1);
259
260 mprotect((void *)start, end - start,
261 PROT_READ | PROT_WRITE | PROT_EXEC);
262}
263#endif
264#else // VBOX
265static void map_exec(void *addr, long size)
266{
267 RTMemProtect(addr, size,
268 RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
269}
270#endif
271
272static void page_init(void)
273{
274 /* NOTE: we can always suppose that qemu_host_page_size >=
275 TARGET_PAGE_SIZE */
276#ifdef VBOX
277 RTMemProtect(code_gen_buffer, sizeof(code_gen_buffer),
278 RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
279 qemu_real_host_page_size = PAGE_SIZE;
280#else /* !VBOX */
281#ifdef _WIN32
282 {
283 SYSTEM_INFO system_info;
284 DWORD old_protect;
285
286 GetSystemInfo(&system_info);
287 qemu_real_host_page_size = system_info.dwPageSize;
288 }
289#else
290 qemu_real_host_page_size = getpagesize();
291#endif
292#endif /* !VBOX */
293
294 if (qemu_host_page_size == 0)
295 qemu_host_page_size = qemu_real_host_page_size;
296 if (qemu_host_page_size < TARGET_PAGE_SIZE)
297 qemu_host_page_size = TARGET_PAGE_SIZE;
298 qemu_host_page_bits = 0;
299#ifndef VBOX
300 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
301#else
302 while ((1 << qemu_host_page_bits) < (int)qemu_host_page_size)
303#endif
304 qemu_host_page_bits++;
305 qemu_host_page_mask = ~(qemu_host_page_size - 1);
306 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
307 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
308#ifdef VBOX
309 /* We use other means to set reserved bit on our pages */
310#else
311#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
312 {
313 long long startaddr, endaddr;
314 FILE *f;
315 int n;
316
317 mmap_lock();
318 last_brk = (unsigned long)sbrk(0);
319 f = fopen("/proc/self/maps", "r");
320 if (f) {
321 do {
322 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
323 if (n == 2) {
324 startaddr = MIN(startaddr,
325 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
326 endaddr = MIN(endaddr,
327 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
328 page_set_flags(startaddr & TARGET_PAGE_MASK,
329 TARGET_PAGE_ALIGN(endaddr),
330 PAGE_RESERVED);
331 }
332 } while (!feof(f));
333 fclose(f);
334 }
335 mmap_unlock();
336 }
337#endif
338#endif
339}
340
341#ifndef VBOX
342static inline PageDesc **page_l1_map(target_ulong index)
343#else
344DECLINLINE(PageDesc **) page_l1_map(target_ulong index)
345#endif
346{
347#if TARGET_LONG_BITS > 32
348 /* Host memory outside guest VM. For 32-bit targets we have already
349 excluded high addresses. */
350 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
351 return NULL;
352#endif
353 return &l1_map[index >> L2_BITS];
354}
355
356#ifndef VBOX
357static inline PageDesc *page_find_alloc(target_ulong index)
358#else
359DECLINLINE(PageDesc *) page_find_alloc(target_ulong index)
360#endif
361{
362 PageDesc **lp, *p;
363 lp = page_l1_map(index);
364 if (!lp)
365 return NULL;
366
367 p = *lp;
368 if (!p) {
369 /* allocate if not found */
370#if defined(CONFIG_USER_ONLY)
371 unsigned long addr;
372 size_t len = sizeof(PageDesc) * L2_SIZE;
373 /* Don't use qemu_malloc because it may recurse. */
374 p = mmap(0, len, PROT_READ | PROT_WRITE,
375 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
376 *lp = p;
377 addr = h2g(p);
378 if (addr == (target_ulong)addr) {
379 page_set_flags(addr & TARGET_PAGE_MASK,
380 TARGET_PAGE_ALIGN(addr + len),
381 PAGE_RESERVED);
382 }
383#else
384 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
385 *lp = p;
386#endif
387 }
388 return p + (index & (L2_SIZE - 1));
389}
390
391#ifndef VBOX
392static inline PageDesc *page_find(target_ulong index)
393#else
394DECLINLINE(PageDesc *) page_find(target_ulong index)
395#endif
396{
397 PageDesc **lp, *p;
398 lp = page_l1_map(index);
399 if (!lp)
400 return NULL;
401
402 p = *lp;
403 if (!p)
404 return 0;
405 return p + (index & (L2_SIZE - 1));
406}
407
408static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
409{
410 void **lp, **p;
411 PhysPageDesc *pd;
412
413 p = (void **)l1_phys_map;
414#if TARGET_PHYS_ADDR_SPACE_BITS > 32
415
416#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
417#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
418#endif
419 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
420 p = *lp;
421 if (!p) {
422 /* allocate if not found */
423 if (!alloc)
424 return NULL;
425 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
426 memset(p, 0, sizeof(void *) * L1_SIZE);
427 *lp = p;
428 }
429#endif
430 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
431 pd = *lp;
432 if (!pd) {
433 int i;
434 /* allocate if not found */
435 if (!alloc)
436 return NULL;
437 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
438 *lp = pd;
439 for (i = 0; i < L2_SIZE; i++)
440 pd[i].phys_offset = IO_MEM_UNASSIGNED;
441 }
442#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
443 pd = ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
444 if (RT_UNLIKELY((pd->phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING))
445 remR3GrowDynRange(pd->phys_offset & TARGET_PAGE_MASK);
446 return pd;
447#else
448 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
449#endif
450}
451
452#ifndef VBOX
453static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
454#else
455DECLINLINE(PhysPageDesc *) phys_page_find(target_phys_addr_t index)
456#endif
457{
458 return phys_page_find_alloc(index, 0);
459}
460
461#if !defined(CONFIG_USER_ONLY)
462static void tlb_protect_code(ram_addr_t ram_addr);
463static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
464 target_ulong vaddr);
465#define mmap_lock() do { } while(0)
466#define mmap_unlock() do { } while(0)
467#endif
468
469#ifdef VBOX
470/** @todo nike: isn't 32M too much ? */
471#endif
472#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
473
474#if defined(CONFIG_USER_ONLY)
475/* Currently it is not recommanded to allocate big chunks of data in
476 user mode. It will change when a dedicated libc will be used */
477#define USE_STATIC_CODE_GEN_BUFFER
478#endif
479
480/* VBox allocates codegen buffer dynamically */
481#ifndef VBOX
482#ifdef USE_STATIC_CODE_GEN_BUFFER
483static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
484#endif
485#endif
486
487static void code_gen_alloc(unsigned long tb_size)
488{
489#ifdef USE_STATIC_CODE_GEN_BUFFER
490 code_gen_buffer = static_code_gen_buffer;
491 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
492 map_exec(code_gen_buffer, code_gen_buffer_size);
493#else
494 code_gen_buffer_size = tb_size;
495 if (code_gen_buffer_size == 0) {
496#if defined(CONFIG_USER_ONLY)
497 /* in user mode, phys_ram_size is not meaningful */
498 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
499#else
500 /* XXX: needs ajustments */
501 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
502#endif
503 }
504 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
505 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
506 /* The code gen buffer location may have constraints depending on
507 the host cpu and OS */
508#ifdef VBOX
509 code_gen_buffer = RTMemExecAlloc(code_gen_buffer_size);
510
511 if (!code_gen_buffer) {
512 LogRel(("REM: failed allocate codegen buffer %lld\n",
513 code_gen_buffer_size));
514 return;
515 }
516#else //!VBOX
517#if defined(__linux__)
518 {
519 int flags;
520 void *start = NULL;
521
522 flags = MAP_PRIVATE | MAP_ANONYMOUS;
523#if defined(__x86_64__)
524 flags |= MAP_32BIT;
525 /* Cannot map more than that */
526 if (code_gen_buffer_size > (800 * 1024 * 1024))
527 code_gen_buffer_size = (800 * 1024 * 1024);
528#elif defined(__sparc_v9__)
529 // Map the buffer below 2G, so we can use direct calls and branches
530 flags |= MAP_FIXED;
531 start = (void *) 0x60000000UL;
532 if (code_gen_buffer_size > (512 * 1024 * 1024))
533 code_gen_buffer_size = (512 * 1024 * 1024);
534#endif
535 code_gen_buffer = mmap(start, code_gen_buffer_size,
536 PROT_WRITE | PROT_READ | PROT_EXEC,
537 flags, -1, 0);
538 if (code_gen_buffer == MAP_FAILED) {
539 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
540 exit(1);
541 }
542 }
543#elif defined(__FreeBSD__)
544 {
545 int flags;
546 void *addr = NULL;
547 flags = MAP_PRIVATE | MAP_ANONYMOUS;
548#if defined(__x86_64__)
549 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
550 * 0x40000000 is free */
551 flags |= MAP_FIXED;
552 addr = (void *)0x40000000;
553 /* Cannot map more than that */
554 if (code_gen_buffer_size > (800 * 1024 * 1024))
555 code_gen_buffer_size = (800 * 1024 * 1024);
556#endif
557 code_gen_buffer = mmap(addr, code_gen_buffer_size,
558 PROT_WRITE | PROT_READ | PROT_EXEC,
559 flags, -1, 0);
560 if (code_gen_buffer == MAP_FAILED) {
561 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
562 exit(1);
563 }
564 }
565#else
566 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
567 if (!code_gen_buffer) {
568 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
569 exit(1);
570 }
571 map_exec(code_gen_buffer, code_gen_buffer_size);
572#endif
573 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
574#endif /* !VBOX */
575#endif /* !USE_STATIC_CODE_GEN_BUFFER */
576#ifndef VBOX
577 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
578#else
579 map_exec(code_gen_prologue, _1K);
580#endif
581
582 code_gen_buffer_max_size = code_gen_buffer_size -
583 code_gen_max_block_size();
584 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
585 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
586}
587
588/* Must be called before using the QEMU cpus. 'tb_size' is the size
589 (in bytes) allocated to the translation buffer. Zero means default
590 size. */
591void cpu_exec_init_all(unsigned long tb_size)
592{
593 cpu_gen_init();
594 code_gen_alloc(tb_size);
595 code_gen_ptr = code_gen_buffer;
596 page_init();
597#if !defined(CONFIG_USER_ONLY)
598 io_mem_init();
599#endif
600}
601
602#ifndef VBOX
603#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
604
605#define CPU_COMMON_SAVE_VERSION 1
606
607static void cpu_common_save(QEMUFile *f, void *opaque)
608{
609 CPUState *env = opaque;
610
611 qemu_put_be32s(f, &env->halted);
612 qemu_put_be32s(f, &env->interrupt_request);
613}
614
615static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
616{
617 CPUState *env = opaque;
618
619 if (version_id != CPU_COMMON_SAVE_VERSION)
620 return -EINVAL;
621
622 qemu_get_be32s(f, &env->halted);
623 qemu_get_be32s(f, &env->interrupt_request);
624 tlb_flush(env, 1);
625
626 return 0;
627}
628#endif
629#endif //!VBOX
630
631void cpu_exec_init(CPUState *env)
632{
633 CPUState **penv;
634 int cpu_index;
635
636 env->next_cpu = NULL;
637 penv = &first_cpu;
638 cpu_index = 0;
639 while (*penv != NULL) {
640 penv = (CPUState **)&(*penv)->next_cpu;
641 cpu_index++;
642 }
643 env->cpu_index = cpu_index;
644 env->nb_watchpoints = 0;
645 *penv = env;
646#ifndef VBOX
647#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
648 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
649 cpu_common_save, cpu_common_load, env);
650 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
651 cpu_save, cpu_load, env);
652#endif
653#endif // !VBOX
654}
655
656#ifndef VBOX
657static inline void invalidate_page_bitmap(PageDesc *p)
658#else
659DECLINLINE(void) invalidate_page_bitmap(PageDesc *p)
660#endif
661{
662 if (p->code_bitmap) {
663 qemu_free(p->code_bitmap);
664 p->code_bitmap = NULL;
665 }
666 p->code_write_count = 0;
667}
668
669/* set to NULL all the 'first_tb' fields in all PageDescs */
670static void page_flush_tb(void)
671{
672 int i, j;
673 PageDesc *p;
674
675 for(i = 0; i < L1_SIZE; i++) {
676 p = l1_map[i];
677 if (p) {
678 for(j = 0; j < L2_SIZE; j++) {
679 p->first_tb = NULL;
680 invalidate_page_bitmap(p);
681 p++;
682 }
683 }
684 }
685}
686
687/* flush all the translation blocks */
688/* XXX: tb_flush is currently not thread safe */
689void tb_flush(CPUState *env1)
690{
691 CPUState *env;
692#if defined(DEBUG_FLUSH)
693 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
694 (unsigned long)(code_gen_ptr - code_gen_buffer),
695 nb_tbs, nb_tbs > 0 ?
696 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
697#endif
698 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
699 cpu_abort(env1, "Internal error: code buffer overflow\n");
700
701 nb_tbs = 0;
702
703 for(env = first_cpu; env != NULL; env = env->next_cpu) {
704 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
705 }
706
707 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
708 page_flush_tb();
709
710 code_gen_ptr = code_gen_buffer;
711 /* XXX: flush processor icache at this point if cache flush is
712 expensive */
713 tb_flush_count++;
714}
715
716#ifdef DEBUG_TB_CHECK
717static void tb_invalidate_check(target_ulong address)
718{
719 TranslationBlock *tb;
720 int i;
721 address &= TARGET_PAGE_MASK;
722 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
723 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
724 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
725 address >= tb->pc + tb->size)) {
726 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
727 address, (long)tb->pc, tb->size);
728 }
729 }
730 }
731}
732
733/* verify that all the pages have correct rights for code */
734static void tb_page_check(void)
735{
736 TranslationBlock *tb;
737 int i, flags1, flags2;
738
739 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
740 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
741 flags1 = page_get_flags(tb->pc);
742 flags2 = page_get_flags(tb->pc + tb->size - 1);
743 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
744 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
745 (long)tb->pc, tb->size, flags1, flags2);
746 }
747 }
748 }
749}
750
751static void tb_jmp_check(TranslationBlock *tb)
752{
753 TranslationBlock *tb1;
754 unsigned int n1;
755
756 /* suppress any remaining jumps to this TB */
757 tb1 = tb->jmp_first;
758 for(;;) {
759 n1 = (long)tb1 & 3;
760 tb1 = (TranslationBlock *)((long)tb1 & ~3);
761 if (n1 == 2)
762 break;
763 tb1 = tb1->jmp_next[n1];
764 }
765 /* check end of list */
766 if (tb1 != tb) {
767 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
768 }
769}
770#endif // DEBUG_TB_CHECK
771
772/* invalidate one TB */
773#ifndef VBOX
774static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
775 int next_offset)
776#else
777DECLINLINE(void) tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
778 int next_offset)
779#endif
780{
781 TranslationBlock *tb1;
782 for(;;) {
783 tb1 = *ptb;
784 if (tb1 == tb) {
785 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
786 break;
787 }
788 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
789 }
790}
791
792#ifndef VBOX
793static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
794#else
795DECLINLINE(void) tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
796#endif
797{
798 TranslationBlock *tb1;
799 unsigned int n1;
800
801 for(;;) {
802 tb1 = *ptb;
803 n1 = (long)tb1 & 3;
804 tb1 = (TranslationBlock *)((long)tb1 & ~3);
805 if (tb1 == tb) {
806 *ptb = tb1->page_next[n1];
807 break;
808 }
809 ptb = &tb1->page_next[n1];
810 }
811}
812
813#ifndef VBOX
814static inline void tb_jmp_remove(TranslationBlock *tb, int n)
815#else
816DECLINLINE(void) tb_jmp_remove(TranslationBlock *tb, int n)
817#endif
818{
819 TranslationBlock *tb1, **ptb;
820 unsigned int n1;
821
822 ptb = &tb->jmp_next[n];
823 tb1 = *ptb;
824 if (tb1) {
825 /* find tb(n) in circular list */
826 for(;;) {
827 tb1 = *ptb;
828 n1 = (long)tb1 & 3;
829 tb1 = (TranslationBlock *)((long)tb1 & ~3);
830 if (n1 == n && tb1 == tb)
831 break;
832 if (n1 == 2) {
833 ptb = &tb1->jmp_first;
834 } else {
835 ptb = &tb1->jmp_next[n1];
836 }
837 }
838 /* now we can suppress tb(n) from the list */
839 *ptb = tb->jmp_next[n];
840
841 tb->jmp_next[n] = NULL;
842 }
843}
844
845/* reset the jump entry 'n' of a TB so that it is not chained to
846 another TB */
847#ifndef VBOX
848static inline void tb_reset_jump(TranslationBlock *tb, int n)
849#else
850DECLINLINE(void) tb_reset_jump(TranslationBlock *tb, int n)
851#endif
852{
853 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
854}
855
856void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
857{
858 CPUState *env;
859 PageDesc *p;
860 unsigned int h, n1;
861 target_phys_addr_t phys_pc;
862 TranslationBlock *tb1, *tb2;
863
864 /* remove the TB from the hash list */
865 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
866 h = tb_phys_hash_func(phys_pc);
867 tb_remove(&tb_phys_hash[h], tb,
868 offsetof(TranslationBlock, phys_hash_next));
869
870 /* remove the TB from the page list */
871 if (tb->page_addr[0] != page_addr) {
872 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
873 tb_page_remove(&p->first_tb, tb);
874 invalidate_page_bitmap(p);
875 }
876 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
877 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
878 tb_page_remove(&p->first_tb, tb);
879 invalidate_page_bitmap(p);
880 }
881
882 tb_invalidated_flag = 1;
883
884 /* remove the TB from the hash list */
885 h = tb_jmp_cache_hash_func(tb->pc);
886 for(env = first_cpu; env != NULL; env = env->next_cpu) {
887 if (env->tb_jmp_cache[h] == tb)
888 env->tb_jmp_cache[h] = NULL;
889 }
890
891 /* suppress this TB from the two jump lists */
892 tb_jmp_remove(tb, 0);
893 tb_jmp_remove(tb, 1);
894
895 /* suppress any remaining jumps to this TB */
896 tb1 = tb->jmp_first;
897 for(;;) {
898 n1 = (long)tb1 & 3;
899 if (n1 == 2)
900 break;
901 tb1 = (TranslationBlock *)((long)tb1 & ~3);
902 tb2 = tb1->jmp_next[n1];
903 tb_reset_jump(tb1, n1);
904 tb1->jmp_next[n1] = NULL;
905 tb1 = tb2;
906 }
907 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
908
909#ifndef VBOX
910 tb_phys_invalidate_count++;
911#endif
912}
913
914
915#ifdef VBOX
916void tb_invalidate_virt(CPUState *env, uint32_t eip)
917{
918# if 1
919 tb_flush(env);
920# else
921 uint8_t *cs_base, *pc;
922 unsigned int flags, h, phys_pc;
923 TranslationBlock *tb, **ptb;
924
925 flags = env->hflags;
926 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
927 cs_base = env->segs[R_CS].base;
928 pc = cs_base + eip;
929
930 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
931 flags);
932
933 if(tb)
934 {
935# ifdef DEBUG
936 printf("invalidating TB (%08X) at %08X\n", tb, eip);
937# endif
938 tb_invalidate(tb);
939 //Note: this will leak TBs, but the whole cache will be flushed
940 // when it happens too often
941 tb->pc = 0;
942 tb->cs_base = 0;
943 tb->flags = 0;
944 }
945# endif
946}
947
948# ifdef VBOX_STRICT
949/**
950 * Gets the page offset.
951 */
952unsigned long get_phys_page_offset(target_ulong addr)
953{
954 PhysPageDesc *p = phys_page_find(addr >> TARGET_PAGE_BITS);
955 return p ? p->phys_offset : 0;
956}
957# endif /* VBOX_STRICT */
958#endif /* VBOX */
959
960#ifndef VBOX
961static inline void set_bits(uint8_t *tab, int start, int len)
962#else
963DECLINLINE(void) set_bits(uint8_t *tab, int start, int len)
964#endif
965{
966 int end, mask, end1;
967
968 end = start + len;
969 tab += start >> 3;
970 mask = 0xff << (start & 7);
971 if ((start & ~7) == (end & ~7)) {
972 if (start < end) {
973 mask &= ~(0xff << (end & 7));
974 *tab |= mask;
975 }
976 } else {
977 *tab++ |= mask;
978 start = (start + 8) & ~7;
979 end1 = end & ~7;
980 while (start < end1) {
981 *tab++ = 0xff;
982 start += 8;
983 }
984 if (start < end) {
985 mask = ~(0xff << (end & 7));
986 *tab |= mask;
987 }
988 }
989}
990
991static void build_page_bitmap(PageDesc *p)
992{
993 int n, tb_start, tb_end;
994 TranslationBlock *tb;
995
996 p->code_bitmap = qemu_malloc(TARGET_PAGE_SIZE / 8);
997 if (!p->code_bitmap)
998 return;
999 memset(p->code_bitmap, 0, TARGET_PAGE_SIZE / 8);
1000
1001 tb = p->first_tb;
1002 while (tb != NULL) {
1003 n = (long)tb & 3;
1004 tb = (TranslationBlock *)((long)tb & ~3);
1005 /* NOTE: this is subtle as a TB may span two physical pages */
1006 if (n == 0) {
1007 /* NOTE: tb_end may be after the end of the page, but
1008 it is not a problem */
1009 tb_start = tb->pc & ~TARGET_PAGE_MASK;
1010 tb_end = tb_start + tb->size;
1011 if (tb_end > TARGET_PAGE_SIZE)
1012 tb_end = TARGET_PAGE_SIZE;
1013 } else {
1014 tb_start = 0;
1015 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
1016 }
1017 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
1018 tb = tb->page_next[n];
1019 }
1020}
1021
1022TranslationBlock *tb_gen_code(CPUState *env,
1023 target_ulong pc, target_ulong cs_base,
1024 int flags, int cflags)
1025{
1026 TranslationBlock *tb;
1027 uint8_t *tc_ptr;
1028 target_ulong phys_pc, phys_page2, virt_page2;
1029 int code_gen_size;
1030
1031 phys_pc = get_phys_addr_code(env, pc);
1032 tb = tb_alloc(pc);
1033 if (!tb) {
1034 /* flush must be done */
1035 tb_flush(env);
1036 /* cannot fail at this point */
1037 tb = tb_alloc(pc);
1038 /* Don't forget to invalidate previous TB info. */
1039 tb_invalidated_flag = 1;
1040 }
1041 tc_ptr = code_gen_ptr;
1042 tb->tc_ptr = tc_ptr;
1043 tb->cs_base = cs_base;
1044 tb->flags = flags;
1045 tb->cflags = cflags;
1046 cpu_gen_code(env, tb, &code_gen_size);
1047 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
1048
1049 /* check next page if needed */
1050 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
1051 phys_page2 = -1;
1052 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
1053 phys_page2 = get_phys_addr_code(env, virt_page2);
1054 }
1055 tb_link_phys(tb, phys_pc, phys_page2);
1056 return tb;
1057}
1058
1059/* invalidate all TBs which intersect with the target physical page
1060 starting in range [start;end[. NOTE: start and end must refer to
1061 the same physical page. 'is_cpu_write_access' should be true if called
1062 from a real cpu write access: the virtual CPU will exit the current
1063 TB if code is modified inside this TB. */
1064void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
1065 int is_cpu_write_access)
1066{
1067 int n, current_tb_modified, current_tb_not_found, current_flags;
1068 CPUState *env = cpu_single_env;
1069 PageDesc *p;
1070 TranslationBlock *tb, *tb_next, *current_tb, *saved_tb;
1071 target_ulong tb_start, tb_end;
1072 target_ulong current_pc, current_cs_base;
1073
1074 p = page_find(start >> TARGET_PAGE_BITS);
1075 if (!p)
1076 return;
1077 if (!p->code_bitmap &&
1078 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
1079 is_cpu_write_access) {
1080 /* build code bitmap */
1081 build_page_bitmap(p);
1082 }
1083
1084 /* we remove all the TBs in the range [start, end[ */
1085 /* XXX: see if in some cases it could be faster to invalidate all the code */
1086 current_tb_not_found = is_cpu_write_access;
1087 current_tb_modified = 0;
1088 current_tb = NULL; /* avoid warning */
1089 current_pc = 0; /* avoid warning */
1090 current_cs_base = 0; /* avoid warning */
1091 current_flags = 0; /* avoid warning */
1092 tb = p->first_tb;
1093 while (tb != NULL) {
1094 n = (long)tb & 3;
1095 tb = (TranslationBlock *)((long)tb & ~3);
1096 tb_next = tb->page_next[n];
1097 /* NOTE: this is subtle as a TB may span two physical pages */
1098 if (n == 0) {
1099 /* NOTE: tb_end may be after the end of the page, but
1100 it is not a problem */
1101 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
1102 tb_end = tb_start + tb->size;
1103 } else {
1104 tb_start = tb->page_addr[1];
1105 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
1106 }
1107 if (!(tb_end <= start || tb_start >= end)) {
1108#ifdef TARGET_HAS_PRECISE_SMC
1109 if (current_tb_not_found) {
1110 current_tb_not_found = 0;
1111 current_tb = NULL;
1112 if (env->mem_io_pc) {
1113 /* now we have a real cpu fault */
1114 current_tb = tb_find_pc(env->mem_io_pc);
1115 }
1116 }
1117 if (current_tb == tb &&
1118 (current_tb->cflags & CF_COUNT_MASK) != 1) {
1119 /* If we are modifying the current TB, we must stop
1120 its execution. We could be more precise by checking
1121 that the modification is after the current PC, but it
1122 would require a specialized function to partially
1123 restore the CPU state */
1124
1125 current_tb_modified = 1;
1126 cpu_restore_state(current_tb, env,
1127 env->mem_io_pc, NULL);
1128#if defined(TARGET_I386)
1129 current_flags = env->hflags;
1130 current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
1131 current_cs_base = (target_ulong)env->segs[R_CS].base;
1132 current_pc = current_cs_base + env->eip;
1133#else
1134#error unsupported CPU
1135#endif
1136 }
1137#endif /* TARGET_HAS_PRECISE_SMC */
1138 /* we need to do that to handle the case where a signal
1139 occurs while doing tb_phys_invalidate() */
1140 saved_tb = NULL;
1141 if (env) {
1142 saved_tb = env->current_tb;
1143 env->current_tb = NULL;
1144 }
1145 tb_phys_invalidate(tb, -1);
1146 if (env) {
1147 env->current_tb = saved_tb;
1148 if (env->interrupt_request && env->current_tb)
1149 cpu_interrupt(env, env->interrupt_request);
1150 }
1151 }
1152 tb = tb_next;
1153 }
1154#if !defined(CONFIG_USER_ONLY)
1155 /* if no code remaining, no need to continue to use slow writes */
1156 if (!p->first_tb) {
1157 invalidate_page_bitmap(p);
1158 if (is_cpu_write_access) {
1159 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
1160 }
1161 }
1162#endif
1163#ifdef TARGET_HAS_PRECISE_SMC
1164 if (current_tb_modified) {
1165 /* we generate a block containing just the instruction
1166 modifying the memory. It will ensure that it cannot modify
1167 itself */
1168 env->current_tb = NULL;
1169 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1170 cpu_resume_from_signal(env, NULL);
1171 }
1172#endif
1173}
1174
1175
1176/* len must be <= 8 and start must be a multiple of len */
1177#ifndef VBOX
1178static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
1179#else
1180DECLINLINE(void) tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
1181#endif
1182{
1183 PageDesc *p;
1184 int offset, b;
1185#if 0
1186 if (1) {
1187 if (loglevel) {
1188 fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1189 cpu_single_env->mem_io_vaddr, len,
1190 cpu_single_env->eip,
1191 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1192 }
1193 }
1194#endif
1195 p = page_find(start >> TARGET_PAGE_BITS);
1196 if (!p)
1197 return;
1198 if (p->code_bitmap) {
1199 offset = start & ~TARGET_PAGE_MASK;
1200 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1201 if (b & ((1 << len) - 1))
1202 goto do_invalidate;
1203 } else {
1204 do_invalidate:
1205 tb_invalidate_phys_page_range(start, start + len, 1);
1206 }
1207}
1208
1209
1210#if !defined(CONFIG_SOFTMMU)
1211static void tb_invalidate_phys_page(target_phys_addr_t addr,
1212 unsigned long pc, void *puc)
1213{
1214 int n, current_flags, current_tb_modified;
1215 target_ulong current_pc, current_cs_base;
1216 PageDesc *p;
1217 TranslationBlock *tb, *current_tb;
1218#ifdef TARGET_HAS_PRECISE_SMC
1219 CPUState *env = cpu_single_env;
1220#endif
1221
1222 addr &= TARGET_PAGE_MASK;
1223 p = page_find(addr >> TARGET_PAGE_BITS);
1224 if (!p)
1225 return;
1226 tb = p->first_tb;
1227 current_tb_modified = 0;
1228 current_tb = NULL;
1229 current_pc = 0; /* avoid warning */
1230 current_cs_base = 0; /* avoid warning */
1231 current_flags = 0; /* avoid warning */
1232#ifdef TARGET_HAS_PRECISE_SMC
1233 if (tb && pc != 0) {
1234 current_tb = tb_find_pc(pc);
1235 }
1236#endif
1237 while (tb != NULL) {
1238 n = (long)tb & 3;
1239 tb = (TranslationBlock *)((long)tb & ~3);
1240#ifdef TARGET_HAS_PRECISE_SMC
1241 if (current_tb == tb &&
1242 (current_tb->cflags & CF_COUNT_MASK) != 1) {
1243 /* If we are modifying the current TB, we must stop
1244 its execution. We could be more precise by checking
1245 that the modification is after the current PC, but it
1246 would require a specialized function to partially
1247 restore the CPU state */
1248
1249 current_tb_modified = 1;
1250 cpu_restore_state(current_tb, env, pc, puc);
1251#if defined(TARGET_I386)
1252 current_flags = env->hflags;
1253 current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
1254 current_cs_base = (target_ulong)env->segs[R_CS].base;
1255 current_pc = current_cs_base + env->eip;
1256#else
1257#error unsupported CPU
1258#endif
1259 }
1260#endif /* TARGET_HAS_PRECISE_SMC */
1261 tb_phys_invalidate(tb, addr);
1262 tb = tb->page_next[n];
1263 }
1264 p->first_tb = NULL;
1265#ifdef TARGET_HAS_PRECISE_SMC
1266 if (current_tb_modified) {
1267 /* we generate a block containing just the instruction
1268 modifying the memory. It will ensure that it cannot modify
1269 itself */
1270 env->current_tb = NULL;
1271 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1272 cpu_resume_from_signal(env, puc);
1273 }
1274#endif
1275}
1276#endif
1277
1278/* add the tb in the target page and protect it if necessary */
1279#ifndef VBOX
1280static inline void tb_alloc_page(TranslationBlock *tb,
1281 unsigned int n, target_ulong page_addr)
1282#else
1283DECLINLINE(void) tb_alloc_page(TranslationBlock *tb,
1284 unsigned int n, target_ulong page_addr)
1285#endif
1286{
1287 PageDesc *p;
1288 TranslationBlock *last_first_tb;
1289
1290 tb->page_addr[n] = page_addr;
1291 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
1292 tb->page_next[n] = p->first_tb;
1293 last_first_tb = p->first_tb;
1294 p->first_tb = (TranslationBlock *)((long)tb | n);
1295 invalidate_page_bitmap(p);
1296
1297#if defined(TARGET_HAS_SMC) || 1
1298
1299#if defined(CONFIG_USER_ONLY)
1300 if (p->flags & PAGE_WRITE) {
1301 target_ulong addr;
1302 PageDesc *p2;
1303 int prot;
1304
1305 /* force the host page as non writable (writes will have a
1306 page fault + mprotect overhead) */
1307 page_addr &= qemu_host_page_mask;
1308 prot = 0;
1309 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1310 addr += TARGET_PAGE_SIZE) {
1311
1312 p2 = page_find (addr >> TARGET_PAGE_BITS);
1313 if (!p2)
1314 continue;
1315 prot |= p2->flags;
1316 p2->flags &= ~PAGE_WRITE;
1317 page_get_flags(addr);
1318 }
1319 mprotect(g2h(page_addr), qemu_host_page_size,
1320 (prot & PAGE_BITS) & ~PAGE_WRITE);
1321#ifdef DEBUG_TB_INVALIDATE
1322 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
1323 page_addr);
1324#endif
1325 }
1326#else
1327 /* if some code is already present, then the pages are already
1328 protected. So we handle the case where only the first TB is
1329 allocated in a physical page */
1330 if (!last_first_tb) {
1331 tlb_protect_code(page_addr);
1332 }
1333#endif
1334
1335#endif /* TARGET_HAS_SMC */
1336}
1337
1338/* Allocate a new translation block. Flush the translation buffer if
1339 too many translation blocks or too much generated code. */
1340TranslationBlock *tb_alloc(target_ulong pc)
1341{
1342 TranslationBlock *tb;
1343
1344 if (nb_tbs >= code_gen_max_blocks ||
1345#ifndef VBOX
1346 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
1347#else
1348 (code_gen_ptr - code_gen_buffer) >= (int)code_gen_buffer_max_size)
1349#endif
1350 return NULL;
1351 tb = &tbs[nb_tbs++];
1352 tb->pc = pc;
1353 tb->cflags = 0;
1354 return tb;
1355}
1356
1357void tb_free(TranslationBlock *tb)
1358{
1359 /* In practice this is mostly used for single use temporary TB
1360 Ignore the hard cases and just back up if this TB happens to
1361 be the last one generated. */
1362 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1363 code_gen_ptr = tb->tc_ptr;
1364 nb_tbs--;
1365 }
1366}
1367
1368/* add a new TB and link it to the physical page tables. phys_page2 is
1369 (-1) to indicate that only one page contains the TB. */
1370void tb_link_phys(TranslationBlock *tb,
1371 target_ulong phys_pc, target_ulong phys_page2)
1372{
1373 unsigned int h;
1374 TranslationBlock **ptb;
1375
1376 /* Grab the mmap lock to stop another thread invalidating this TB
1377 before we are done. */
1378 mmap_lock();
1379 /* add in the physical hash table */
1380 h = tb_phys_hash_func(phys_pc);
1381 ptb = &tb_phys_hash[h];
1382 tb->phys_hash_next = *ptb;
1383 *ptb = tb;
1384
1385 /* add in the page list */
1386 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1387 if (phys_page2 != -1)
1388 tb_alloc_page(tb, 1, phys_page2);
1389 else
1390 tb->page_addr[1] = -1;
1391
1392 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1393 tb->jmp_next[0] = NULL;
1394 tb->jmp_next[1] = NULL;
1395
1396 /* init original jump addresses */
1397 if (tb->tb_next_offset[0] != 0xffff)
1398 tb_reset_jump(tb, 0);
1399 if (tb->tb_next_offset[1] != 0xffff)
1400 tb_reset_jump(tb, 1);
1401
1402#ifdef DEBUG_TB_CHECK
1403 tb_page_check();
1404#endif
1405 mmap_unlock();
1406}
1407
1408/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1409 tb[1].tc_ptr. Return NULL if not found */
1410TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1411{
1412 int m_min, m_max, m;
1413 unsigned long v;
1414 TranslationBlock *tb;
1415
1416 if (nb_tbs <= 0)
1417 return NULL;
1418 if (tc_ptr < (unsigned long)code_gen_buffer ||
1419 tc_ptr >= (unsigned long)code_gen_ptr)
1420 return NULL;
1421 /* binary search (cf Knuth) */
1422 m_min = 0;
1423 m_max = nb_tbs - 1;
1424 while (m_min <= m_max) {
1425 m = (m_min + m_max) >> 1;
1426 tb = &tbs[m];
1427 v = (unsigned long)tb->tc_ptr;
1428 if (v == tc_ptr)
1429 return tb;
1430 else if (tc_ptr < v) {
1431 m_max = m - 1;
1432 } else {
1433 m_min = m + 1;
1434 }
1435 }
1436 return &tbs[m_max];
1437}
1438
1439static void tb_reset_jump_recursive(TranslationBlock *tb);
1440
1441#ifndef VBOX
1442static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1443#else
1444DECLINLINE(void) tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1445#endif
1446{
1447 TranslationBlock *tb1, *tb_next, **ptb;
1448 unsigned int n1;
1449
1450 tb1 = tb->jmp_next[n];
1451 if (tb1 != NULL) {
1452 /* find head of list */
1453 for(;;) {
1454 n1 = (long)tb1 & 3;
1455 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1456 if (n1 == 2)
1457 break;
1458 tb1 = tb1->jmp_next[n1];
1459 }
1460 /* we are now sure now that tb jumps to tb1 */
1461 tb_next = tb1;
1462
1463 /* remove tb from the jmp_first list */
1464 ptb = &tb_next->jmp_first;
1465 for(;;) {
1466 tb1 = *ptb;
1467 n1 = (long)tb1 & 3;
1468 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1469 if (n1 == n && tb1 == tb)
1470 break;
1471 ptb = &tb1->jmp_next[n1];
1472 }
1473 *ptb = tb->jmp_next[n];
1474 tb->jmp_next[n] = NULL;
1475
1476 /* suppress the jump to next tb in generated code */
1477 tb_reset_jump(tb, n);
1478
1479 /* suppress jumps in the tb on which we could have jumped */
1480 tb_reset_jump_recursive(tb_next);
1481 }
1482}
1483
1484static void tb_reset_jump_recursive(TranslationBlock *tb)
1485{
1486 tb_reset_jump_recursive2(tb, 0);
1487 tb_reset_jump_recursive2(tb, 1);
1488}
1489
1490#if defined(TARGET_HAS_ICE)
1491static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1492{
1493 target_ulong addr, pd;
1494 ram_addr_t ram_addr;
1495 PhysPageDesc *p;
1496
1497 addr = cpu_get_phys_page_debug(env, pc);
1498 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1499 if (!p) {
1500 pd = IO_MEM_UNASSIGNED;
1501 } else {
1502 pd = p->phys_offset;
1503 }
1504 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
1505 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1506}
1507#endif
1508
1509/* Add a watchpoint. */
1510int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type)
1511{
1512 int i;
1513
1514 for (i = 0; i < env->nb_watchpoints; i++) {
1515 if (addr == env->watchpoint[i].vaddr)
1516 return 0;
1517 }
1518 if (env->nb_watchpoints >= MAX_WATCHPOINTS)
1519 return -1;
1520
1521 i = env->nb_watchpoints++;
1522 env->watchpoint[i].vaddr = addr;
1523 env->watchpoint[i].type = type;
1524 tlb_flush_page(env, addr);
1525 /* FIXME: This flush is needed because of the hack to make memory ops
1526 terminate the TB. It can be removed once the proper IO trap and
1527 re-execute bits are in. */
1528 tb_flush(env);
1529 return i;
1530}
1531
1532/* Remove a watchpoint. */
1533int cpu_watchpoint_remove(CPUState *env, target_ulong addr)
1534{
1535 int i;
1536
1537 for (i = 0; i < env->nb_watchpoints; i++) {
1538 if (addr == env->watchpoint[i].vaddr) {
1539 env->nb_watchpoints--;
1540 env->watchpoint[i] = env->watchpoint[env->nb_watchpoints];
1541 tlb_flush_page(env, addr);
1542 return 0;
1543 }
1544 }
1545 return -1;
1546}
1547
1548/* Remove all watchpoints. */
1549void cpu_watchpoint_remove_all(CPUState *env) {
1550 int i;
1551
1552 for (i = 0; i < env->nb_watchpoints; i++) {
1553 tlb_flush_page(env, env->watchpoint[i].vaddr);
1554 }
1555 env->nb_watchpoints = 0;
1556}
1557
1558/* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
1559 breakpoint is reached */
1560int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
1561{
1562#if defined(TARGET_HAS_ICE)
1563 int i;
1564
1565 for(i = 0; i < env->nb_breakpoints; i++) {
1566 if (env->breakpoints[i] == pc)
1567 return 0;
1568 }
1569
1570 if (env->nb_breakpoints >= MAX_BREAKPOINTS)
1571 return -1;
1572 env->breakpoints[env->nb_breakpoints++] = pc;
1573
1574 breakpoint_invalidate(env, pc);
1575 return 0;
1576#else
1577 return -1;
1578#endif
1579}
1580
1581/* remove all breakpoints */
1582void cpu_breakpoint_remove_all(CPUState *env) {
1583#if defined(TARGET_HAS_ICE)
1584 int i;
1585 for(i = 0; i < env->nb_breakpoints; i++) {
1586 breakpoint_invalidate(env, env->breakpoints[i]);
1587 }
1588 env->nb_breakpoints = 0;
1589#endif
1590}
1591
1592/* remove a breakpoint */
1593int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
1594{
1595#if defined(TARGET_HAS_ICE)
1596 int i;
1597 for(i = 0; i < env->nb_breakpoints; i++) {
1598 if (env->breakpoints[i] == pc)
1599 goto found;
1600 }
1601 return -1;
1602 found:
1603 env->nb_breakpoints--;
1604 if (i < env->nb_breakpoints)
1605 env->breakpoints[i] = env->breakpoints[env->nb_breakpoints];
1606
1607 breakpoint_invalidate(env, pc);
1608 return 0;
1609#else
1610 return -1;
1611#endif
1612}
1613
1614/* enable or disable single step mode. EXCP_DEBUG is returned by the
1615 CPU loop after each instruction */
1616void cpu_single_step(CPUState *env, int enabled)
1617{
1618#if defined(TARGET_HAS_ICE)
1619 if (env->singlestep_enabled != enabled) {
1620 env->singlestep_enabled = enabled;
1621 /* must flush all the translated code to avoid inconsistancies */
1622 /* XXX: only flush what is necessary */
1623 tb_flush(env);
1624 }
1625#endif
1626}
1627
1628#ifndef VBOX
1629/* enable or disable low levels log */
1630void cpu_set_log(int log_flags)
1631{
1632 loglevel = log_flags;
1633 if (loglevel && !logfile) {
1634 logfile = fopen(logfilename, "w");
1635 if (!logfile) {
1636 perror(logfilename);
1637 _exit(1);
1638 }
1639#if !defined(CONFIG_SOFTMMU)
1640 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1641 {
1642 static uint8_t logfile_buf[4096];
1643 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1644 }
1645#else
1646 setvbuf(logfile, NULL, _IOLBF, 0);
1647#endif
1648 }
1649}
1650
1651void cpu_set_log_filename(const char *filename)
1652{
1653 logfilename = strdup(filename);
1654}
1655#endif /* !VBOX */
1656
1657/* mask must never be zero, except for A20 change call */
1658void cpu_interrupt(CPUState *env, int mask)
1659{
1660#if !defined(USE_NPTL)
1661 TranslationBlock *tb;
1662 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
1663#endif
1664 int old_mask;
1665
1666 old_mask = env->interrupt_request;
1667#ifdef VBOX
1668 VM_ASSERT_EMT(env->pVM);
1669 ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request, mask);
1670#else /* !VBOX */
1671 /* FIXME: This is probably not threadsafe. A different thread could
1672 be in the middle of a read-modify-write operation. */
1673 env->interrupt_request |= mask;
1674#endif /* !VBOX */
1675#if defined(USE_NPTL)
1676 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1677 problem and hope the cpu will stop of its own accord. For userspace
1678 emulation this often isn't actually as bad as it sounds. Often
1679 signals are used primarily to interrupt blocking syscalls. */
1680#else
1681 if (use_icount) {
1682 env->icount_decr.u16.high = 0xffff;
1683#ifndef CONFIG_USER_ONLY
1684 /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
1685 an async event happened and we need to process it. */
1686 if (!can_do_io(env)
1687 && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
1688 cpu_abort(env, "Raised interrupt while not in I/O function");
1689 }
1690#endif
1691 } else {
1692 tb = env->current_tb;
1693 /* if the cpu is currently executing code, we must unlink it and
1694 all the potentially executing TB */
1695 if (tb && !testandset(&interrupt_lock)) {
1696 env->current_tb = NULL;
1697 tb_reset_jump_recursive(tb);
1698 resetlock(&interrupt_lock);
1699 }
1700 }
1701#endif
1702}
1703
1704void cpu_reset_interrupt(CPUState *env, int mask)
1705{
1706#ifdef VBOX
1707 /*
1708 * Note: the current implementation can be executed by another thread without problems; make sure this remains true
1709 * for future changes!
1710 */
1711 ASMAtomicAndS32((int32_t volatile *)&env->interrupt_request, ~mask);
1712#else /* !VBOX */
1713 env->interrupt_request &= ~mask;
1714#endif /* !VBOX */
1715}
1716
1717#ifndef VBOX
1718CPULogItem cpu_log_items[] = {
1719 { CPU_LOG_TB_OUT_ASM, "out_asm",
1720 "show generated host assembly code for each compiled TB" },
1721 { CPU_LOG_TB_IN_ASM, "in_asm",
1722 "show target assembly code for each compiled TB" },
1723 { CPU_LOG_TB_OP, "op",
1724 "show micro ops for each compiled TB (only usable if 'in_asm' used)" },
1725#ifdef TARGET_I386
1726 { CPU_LOG_TB_OP_OPT, "op_opt",
1727 "show micro ops after optimization for each compiled TB" },
1728#endif
1729 { CPU_LOG_INT, "int",
1730 "show interrupts/exceptions in short format" },
1731 { CPU_LOG_EXEC, "exec",
1732 "show trace before each executed TB (lots of logs)" },
1733 { CPU_LOG_TB_CPU, "cpu",
1734 "show CPU state before bloc translation" },
1735#ifdef TARGET_I386
1736 { CPU_LOG_PCALL, "pcall",
1737 "show protected mode far calls/returns/exceptions" },
1738#endif
1739#ifdef DEBUG_IOPORT
1740 { CPU_LOG_IOPORT, "ioport",
1741 "show all i/o ports accesses" },
1742#endif
1743 { 0, NULL, NULL },
1744};
1745
1746static int cmp1(const char *s1, int n, const char *s2)
1747{
1748 if (strlen(s2) != n)
1749 return 0;
1750 return memcmp(s1, s2, n) == 0;
1751}
1752
1753/* takes a comma separated list of log masks. Return 0 if error. */
1754int cpu_str_to_log_mask(const char *str)
1755{
1756 CPULogItem *item;
1757 int mask;
1758 const char *p, *p1;
1759
1760 p = str;
1761 mask = 0;
1762 for(;;) {
1763 p1 = strchr(p, ',');
1764 if (!p1)
1765 p1 = p + strlen(p);
1766 if(cmp1(p,p1-p,"all")) {
1767 for(item = cpu_log_items; item->mask != 0; item++) {
1768 mask |= item->mask;
1769 }
1770 } else {
1771 for(item = cpu_log_items; item->mask != 0; item++) {
1772 if (cmp1(p, p1 - p, item->name))
1773 goto found;
1774 }
1775 return 0;
1776 }
1777 found:
1778 mask |= item->mask;
1779 if (*p1 != ',')
1780 break;
1781 p = p1 + 1;
1782 }
1783 return mask;
1784}
1785#endif /* !VBOX */
1786
1787#ifndef VBOX /* VBOX: we have our own routine. */
1788void cpu_abort(CPUState *env, const char *fmt, ...)
1789{
1790 va_list ap;
1791
1792 va_start(ap, fmt);
1793 fprintf(stderr, "qemu: fatal: ");
1794 vfprintf(stderr, fmt, ap);
1795 fprintf(stderr, "\n");
1796#ifdef TARGET_I386
1797 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1798#else
1799 cpu_dump_state(env, stderr, fprintf, 0);
1800#endif
1801 va_end(ap);
1802 abort();
1803}
1804#endif /* !VBOX */
1805
1806#ifndef VBOX
1807CPUState *cpu_copy(CPUState *env)
1808{
1809 CPUState *new_env = cpu_init(env->cpu_model_str);
1810 /* preserve chaining and index */
1811 CPUState *next_cpu = new_env->next_cpu;
1812 int cpu_index = new_env->cpu_index;
1813 memcpy(new_env, env, sizeof(CPUState));
1814 new_env->next_cpu = next_cpu;
1815 new_env->cpu_index = cpu_index;
1816 return new_env;
1817}
1818#endif
1819
1820#if !defined(CONFIG_USER_ONLY)
1821
1822#ifndef VBOX
1823static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1824#else
1825DECLINLINE(void) tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1826#endif
1827{
1828 unsigned int i;
1829
1830 /* Discard jump cache entries for any tb which might potentially
1831 overlap the flushed page. */
1832 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1833 memset (&env->tb_jmp_cache[i], 0,
1834 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1835
1836 i = tb_jmp_cache_hash_page(addr);
1837 memset (&env->tb_jmp_cache[i], 0,
1838 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1839
1840#ifdef VBOX
1841 /* inform raw mode about TLB page flush */
1842 remR3FlushPage(env, addr);
1843#endif /* VBOX */
1844}
1845
1846/* NOTE: if flush_global is true, also flush global entries (not
1847 implemented yet) */
1848void tlb_flush(CPUState *env, int flush_global)
1849{
1850 int i;
1851
1852#if defined(DEBUG_TLB)
1853 printf("tlb_flush:\n");
1854#endif
1855 /* must reset current TB so that interrupts cannot modify the
1856 links while we are modifying them */
1857 env->current_tb = NULL;
1858
1859 for(i = 0; i < CPU_TLB_SIZE; i++) {
1860 env->tlb_table[0][i].addr_read = -1;
1861 env->tlb_table[0][i].addr_write = -1;
1862 env->tlb_table[0][i].addr_code = -1;
1863 env->tlb_table[1][i].addr_read = -1;
1864 env->tlb_table[1][i].addr_write = -1;
1865 env->tlb_table[1][i].addr_code = -1;
1866#if (NB_MMU_MODES >= 3)
1867 env->tlb_table[2][i].addr_read = -1;
1868 env->tlb_table[2][i].addr_write = -1;
1869 env->tlb_table[2][i].addr_code = -1;
1870#if (NB_MMU_MODES == 4)
1871 env->tlb_table[3][i].addr_read = -1;
1872 env->tlb_table[3][i].addr_write = -1;
1873 env->tlb_table[3][i].addr_code = -1;
1874#endif
1875#endif
1876 }
1877
1878 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
1879
1880#ifdef VBOX
1881 /* inform raw mode about TLB flush */
1882 remR3FlushTLB(env, flush_global);
1883#endif
1884#ifdef USE_KQEMU
1885 if (env->kqemu_enabled) {
1886 kqemu_flush(env, flush_global);
1887 }
1888#endif
1889 tlb_flush_count++;
1890}
1891
1892#ifndef VBOX
1893static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1894#else
1895DECLINLINE(void) tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1896#endif
1897{
1898 if (addr == (tlb_entry->addr_read &
1899 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1900 addr == (tlb_entry->addr_write &
1901 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1902 addr == (tlb_entry->addr_code &
1903 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1904 tlb_entry->addr_read = -1;
1905 tlb_entry->addr_write = -1;
1906 tlb_entry->addr_code = -1;
1907 }
1908}
1909
1910void tlb_flush_page(CPUState *env, target_ulong addr)
1911{
1912 int i;
1913
1914#if defined(DEBUG_TLB)
1915 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
1916#endif
1917 /* must reset current TB so that interrupts cannot modify the
1918 links while we are modifying them */
1919 env->current_tb = NULL;
1920
1921 addr &= TARGET_PAGE_MASK;
1922 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1923 tlb_flush_entry(&env->tlb_table[0][i], addr);
1924 tlb_flush_entry(&env->tlb_table[1][i], addr);
1925#if (NB_MMU_MODES >= 3)
1926 tlb_flush_entry(&env->tlb_table[2][i], addr);
1927#if (NB_MMU_MODES == 4)
1928 tlb_flush_entry(&env->tlb_table[3][i], addr);
1929#endif
1930#endif
1931
1932 tlb_flush_jmp_cache(env, addr);
1933
1934#ifdef USE_KQEMU
1935 if (env->kqemu_enabled) {
1936 kqemu_flush_page(env, addr);
1937 }
1938#endif
1939}
1940
1941/* update the TLBs so that writes to code in the virtual page 'addr'
1942 can be detected */
1943static void tlb_protect_code(ram_addr_t ram_addr)
1944{
1945 cpu_physical_memory_reset_dirty(ram_addr,
1946 ram_addr + TARGET_PAGE_SIZE,
1947 CODE_DIRTY_FLAG);
1948#if defined(VBOX) && defined(REM_MONITOR_CODE_PAGES)
1949 /** @todo Retest this? This function has changed... */
1950 remR3ProtectCode(cpu_single_env, ram_addr);
1951#endif
1952}
1953
1954/* update the TLB so that writes in physical page 'phys_addr' are no longer
1955 tested for self modifying code */
1956static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
1957 target_ulong vaddr)
1958{
1959#ifdef VBOX
1960 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
1961#endif
1962 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
1963}
1964
1965#ifndef VBOX
1966static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1967 unsigned long start, unsigned long length)
1968#else
1969DECLINLINE(void) tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1970 unsigned long start, unsigned long length)
1971#endif
1972{
1973 unsigned long addr;
1974
1975#ifdef VBOX
1976 if (start & 3)
1977 return;
1978#endif
1979 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1980 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1981 if ((addr - start) < length) {
1982 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_NOTDIRTY;
1983 }
1984 }
1985}
1986
1987void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1988 int dirty_flags)
1989{
1990 CPUState *env;
1991 unsigned long length, start1;
1992 int i, mask, len;
1993 uint8_t *p;
1994
1995 start &= TARGET_PAGE_MASK;
1996 end = TARGET_PAGE_ALIGN(end);
1997
1998 length = end - start;
1999 if (length == 0)
2000 return;
2001 len = length >> TARGET_PAGE_BITS;
2002#ifdef USE_KQEMU
2003 /* XXX: should not depend on cpu context */
2004 env = first_cpu;
2005 if (env->kqemu_enabled) {
2006 ram_addr_t addr;
2007 addr = start;
2008 for(i = 0; i < len; i++) {
2009 kqemu_set_notdirty(env, addr);
2010 addr += TARGET_PAGE_SIZE;
2011 }
2012 }
2013#endif
2014 mask = ~dirty_flags;
2015 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
2016#ifdef VBOX
2017 if (RT_LIKELY((start >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2018#endif
2019 for(i = 0; i < len; i++)
2020 p[i] &= mask;
2021
2022 /* we modify the TLB cache so that the dirty bit will be set again
2023 when accessing the range */
2024#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
2025 start1 = start;
2026#elif !defined(VBOX)
2027 start1 = start + (unsigned long)phys_ram_base;
2028#else
2029 start1 = (unsigned long)remR3TlbGCPhys2Ptr(first_cpu, start, 1 /*fWritable*/); /** @todo this can be harmful with VBOX_WITH_NEW_PHYS_CODE, fix interface/whatever. */
2030#endif
2031 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2032 for(i = 0; i < CPU_TLB_SIZE; i++)
2033 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
2034 for(i = 0; i < CPU_TLB_SIZE; i++)
2035 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
2036#if (NB_MMU_MODES >= 3)
2037 for(i = 0; i < CPU_TLB_SIZE; i++)
2038 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
2039#if (NB_MMU_MODES == 4)
2040 for(i = 0; i < CPU_TLB_SIZE; i++)
2041 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
2042#endif
2043#endif
2044 }
2045}
2046
2047#ifndef VBOX
2048int cpu_physical_memory_set_dirty_tracking(int enable)
2049{
2050 in_migration = enable;
2051 return 0;
2052}
2053
2054int cpu_physical_memory_get_dirty_tracking(void)
2055{
2056 return in_migration;
2057}
2058#endif
2059
2060#ifndef VBOX
2061static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
2062#else
2063DECLINLINE(void) tlb_update_dirty(CPUTLBEntry *tlb_entry)
2064#endif
2065{
2066 ram_addr_t ram_addr;
2067
2068 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
2069 /* RAM case */
2070#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
2071 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
2072#elif !defined(VBOX)
2073 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
2074 tlb_entry->addend - (unsigned long)phys_ram_base;
2075#else
2076 ram_addr = remR3HCVirt2GCPhys(first_cpu, (void*)((tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend));
2077#endif
2078 if (!cpu_physical_memory_is_dirty(ram_addr)) {
2079 tlb_entry->addr_write |= TLB_NOTDIRTY;
2080 }
2081 }
2082}
2083
2084/* update the TLB according to the current state of the dirty bits */
2085void cpu_tlb_update_dirty(CPUState *env)
2086{
2087 int i;
2088 for(i = 0; i < CPU_TLB_SIZE; i++)
2089 tlb_update_dirty(&env->tlb_table[0][i]);
2090 for(i = 0; i < CPU_TLB_SIZE; i++)
2091 tlb_update_dirty(&env->tlb_table[1][i]);
2092#if (NB_MMU_MODES >= 3)
2093 for(i = 0; i < CPU_TLB_SIZE; i++)
2094 tlb_update_dirty(&env->tlb_table[2][i]);
2095#if (NB_MMU_MODES == 4)
2096 for(i = 0; i < CPU_TLB_SIZE; i++)
2097 tlb_update_dirty(&env->tlb_table[3][i]);
2098#endif
2099#endif
2100}
2101
2102#ifndef VBOX
2103static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
2104#else
2105DECLINLINE(void) tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
2106#endif
2107{
2108 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
2109 tlb_entry->addr_write = vaddr;
2110}
2111
2112
2113/* update the TLB corresponding to virtual page vaddr and phys addr
2114 addr so that it is no longer dirty */
2115#ifndef VBOX
2116static inline void tlb_set_dirty(CPUState *env,
2117 unsigned long addr, target_ulong vaddr)
2118#else
2119DECLINLINE(void) tlb_set_dirty(CPUState *env,
2120 unsigned long addr, target_ulong vaddr)
2121#endif
2122{
2123 int i;
2124
2125 addr &= TARGET_PAGE_MASK;
2126 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2127 tlb_set_dirty1(&env->tlb_table[0][i], addr);
2128 tlb_set_dirty1(&env->tlb_table[1][i], addr);
2129#if (NB_MMU_MODES >= 3)
2130 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
2131#if (NB_MMU_MODES == 4)
2132 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
2133#endif
2134#endif
2135}
2136
2137/* add a new TLB entry. At most one entry for a given virtual address
2138 is permitted. Return 0 if OK or 2 if the page could not be mapped
2139 (can only happen in non SOFTMMU mode for I/O pages or pages
2140 conflicting with the host address space). */
2141int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2142 target_phys_addr_t paddr, int prot,
2143 int mmu_idx, int is_softmmu)
2144{
2145 PhysPageDesc *p;
2146 unsigned long pd;
2147 unsigned int index;
2148 target_ulong address;
2149 target_ulong code_address;
2150 target_phys_addr_t addend;
2151 int ret;
2152 CPUTLBEntry *te;
2153 int i;
2154 target_phys_addr_t iotlb;
2155#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2156 int read_mods = 0, write_mods = 0, code_mods = 0;
2157#endif
2158
2159 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
2160 if (!p) {
2161 pd = IO_MEM_UNASSIGNED;
2162 } else {
2163 pd = p->phys_offset;
2164 }
2165#if defined(DEBUG_TLB)
2166 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
2167 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
2168#endif
2169
2170 ret = 0;
2171 address = vaddr;
2172 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
2173 /* IO memory case (romd handled later) */
2174 address |= TLB_MMIO;
2175 }
2176#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
2177 addend = pd & TARGET_PAGE_MASK;
2178#elif !defined(VBOX)
2179 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
2180#else
2181 /** @todo this is racing the phys_page_find call above since it may register
2182 * a new chunk of memory... */
2183 addend = (unsigned long)remR3TlbGCPhys2Ptr(env,
2184 pd & TARGET_PAGE_MASK,
2185 !!(prot & PAGE_WRITE));
2186#endif
2187
2188 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
2189 /* Normal RAM. */
2190 iotlb = pd & TARGET_PAGE_MASK;
2191 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
2192 iotlb |= IO_MEM_NOTDIRTY;
2193 else
2194 iotlb |= IO_MEM_ROM;
2195 } else {
2196 /* IO handlers are currently passed a phsical address.
2197 It would be nice to pass an offset from the base address
2198 of that region. This would avoid having to special case RAM,
2199 and avoid full address decoding in every device.
2200 We can't use the high bits of pd for this because
2201 IO_MEM_ROMD uses these as a ram address. */
2202 iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
2203 }
2204
2205 code_address = address;
2206
2207#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2208 if (addend & 0x3)
2209 {
2210 if (addend & 0x2)
2211 {
2212 /* catch write */
2213 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
2214 write_mods |= TLB_MMIO;
2215 }
2216 else if (addend & 0x1)
2217 {
2218 /* catch all */
2219 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
2220 {
2221 read_mods |= TLB_MMIO;
2222 write_mods |= TLB_MMIO;
2223 code_mods |= TLB_MMIO;
2224 }
2225 }
2226 if ((iotlb & ~TARGET_PAGE_MASK) == 0)
2227 iotlb = env->pVM->rem.s.iHandlerMemType + paddr;
2228 addend &= ~(target_ulong)0x3;
2229 }
2230#endif
2231
2232 /* Make accesses to pages with watchpoints go via the
2233 watchpoint trap routines. */
2234 for (i = 0; i < env->nb_watchpoints; i++) {
2235 if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) {
2236 iotlb = io_mem_watch + paddr;
2237 /* TODO: The memory case can be optimized by not trapping
2238 reads of pages with a write breakpoint. */
2239 address |= TLB_MMIO;
2240 }
2241 }
2242
2243 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2244 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2245 te = &env->tlb_table[mmu_idx][index];
2246 te->addend = addend - vaddr;
2247 if (prot & PAGE_READ) {
2248 te->addr_read = address;
2249 } else {
2250 te->addr_read = -1;
2251 }
2252
2253 if (prot & PAGE_EXEC) {
2254 te->addr_code = code_address;
2255 } else {
2256 te->addr_code = -1;
2257 }
2258 if (prot & PAGE_WRITE) {
2259 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2260 (pd & IO_MEM_ROMD)) {
2261 /* Write access calls the I/O callback. */
2262 te->addr_write = address | TLB_MMIO;
2263 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2264 !cpu_physical_memory_is_dirty(pd)) {
2265 te->addr_write = address | TLB_NOTDIRTY;
2266 } else {
2267 te->addr_write = address;
2268 }
2269 } else {
2270 te->addr_write = -1;
2271 }
2272
2273#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2274 if (prot & PAGE_READ)
2275 te->addr_read |= read_mods;
2276 if (prot & PAGE_EXEC)
2277 te->addr_code |= code_mods;
2278 if (prot & PAGE_WRITE)
2279 te->addr_write |= write_mods;
2280#endif
2281
2282#ifdef VBOX
2283 /* inform raw mode about TLB page change */
2284 remR3FlushPage(env, vaddr);
2285#endif
2286 return ret;
2287}
2288#if 0
2289/* called from signal handler: invalidate the code and unprotect the
2290 page. Return TRUE if the fault was succesfully handled. */
2291int page_unprotect(target_ulong addr, unsigned long pc, void *puc)
2292{
2293#if !defined(CONFIG_SOFTMMU)
2294 VirtPageDesc *vp;
2295
2296#if defined(DEBUG_TLB)
2297 printf("page_unprotect: addr=0x%08x\n", addr);
2298#endif
2299 addr &= TARGET_PAGE_MASK;
2300
2301 /* if it is not mapped, no need to worry here */
2302 if (addr >= MMAP_AREA_END)
2303 return 0;
2304 vp = virt_page_find(addr >> TARGET_PAGE_BITS);
2305 if (!vp)
2306 return 0;
2307 /* NOTE: in this case, validate_tag is _not_ tested as it
2308 validates only the code TLB */
2309 if (vp->valid_tag != virt_valid_tag)
2310 return 0;
2311 if (!(vp->prot & PAGE_WRITE))
2312 return 0;
2313#if defined(DEBUG_TLB)
2314 printf("page_unprotect: addr=0x%08x phys_addr=0x%08x prot=%x\n",
2315 addr, vp->phys_addr, vp->prot);
2316#endif
2317 if (mprotect((void *)addr, TARGET_PAGE_SIZE, vp->prot) < 0)
2318 cpu_abort(cpu_single_env, "error mprotect addr=0x%lx prot=%d\n",
2319 (unsigned long)addr, vp->prot);
2320 /* set the dirty bit */
2321 phys_ram_dirty[vp->phys_addr >> TARGET_PAGE_BITS] = 0xff;
2322 /* flush the code inside */
2323 tb_invalidate_phys_page(vp->phys_addr, pc, puc);
2324 return 1;
2325#elif defined(VBOX)
2326 addr &= TARGET_PAGE_MASK;
2327
2328 /* if it is not mapped, no need to worry here */
2329 if (addr >= MMAP_AREA_END)
2330 return 0;
2331 return 1;
2332#else
2333 return 0;
2334#endif
2335}
2336#endif /* 0 */
2337
2338#else
2339
2340void tlb_flush(CPUState *env, int flush_global)
2341{
2342}
2343
2344void tlb_flush_page(CPUState *env, target_ulong addr)
2345{
2346}
2347
2348int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2349 target_phys_addr_t paddr, int prot,
2350 int mmu_idx, int is_softmmu)
2351{
2352 return 0;
2353}
2354
2355#ifndef VBOX
2356/* dump memory mappings */
2357void page_dump(FILE *f)
2358{
2359 unsigned long start, end;
2360 int i, j, prot, prot1;
2361 PageDesc *p;
2362
2363 fprintf(f, "%-8s %-8s %-8s %s\n",
2364 "start", "end", "size", "prot");
2365 start = -1;
2366 end = -1;
2367 prot = 0;
2368 for(i = 0; i <= L1_SIZE; i++) {
2369 if (i < L1_SIZE)
2370 p = l1_map[i];
2371 else
2372 p = NULL;
2373 for(j = 0;j < L2_SIZE; j++) {
2374 if (!p)
2375 prot1 = 0;
2376 else
2377 prot1 = p[j].flags;
2378 if (prot1 != prot) {
2379 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2380 if (start != -1) {
2381 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
2382 start, end, end - start,
2383 prot & PAGE_READ ? 'r' : '-',
2384 prot & PAGE_WRITE ? 'w' : '-',
2385 prot & PAGE_EXEC ? 'x' : '-');
2386 }
2387 if (prot1 != 0)
2388 start = end;
2389 else
2390 start = -1;
2391 prot = prot1;
2392 }
2393 if (!p)
2394 break;
2395 }
2396 }
2397}
2398#endif /* !VBOX */
2399
2400int page_get_flags(target_ulong address)
2401{
2402 PageDesc *p;
2403
2404 p = page_find(address >> TARGET_PAGE_BITS);
2405 if (!p)
2406 return 0;
2407 return p->flags;
2408}
2409
2410/* modify the flags of a page and invalidate the code if
2411 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2412 depending on PAGE_WRITE */
2413void page_set_flags(target_ulong start, target_ulong end, int flags)
2414{
2415 PageDesc *p;
2416 target_ulong addr;
2417
2418 start = start & TARGET_PAGE_MASK;
2419 end = TARGET_PAGE_ALIGN(end);
2420 if (flags & PAGE_WRITE)
2421 flags |= PAGE_WRITE_ORG;
2422#ifdef VBOX
2423 AssertMsgFailed(("We shouldn't be here, and if we should, we must have an env to do the proper locking!\n"));
2424#endif
2425 spin_lock(&tb_lock);
2426 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2427 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
2428 /* if the write protection is set, then we invalidate the code
2429 inside */
2430 if (!(p->flags & PAGE_WRITE) &&
2431 (flags & PAGE_WRITE) &&
2432 p->first_tb) {
2433 tb_invalidate_phys_page(addr, 0, NULL);
2434 }
2435 p->flags = flags;
2436 }
2437 spin_unlock(&tb_lock);
2438}
2439
2440int page_check_range(target_ulong start, target_ulong len, int flags)
2441{
2442 PageDesc *p;
2443 target_ulong end;
2444 target_ulong addr;
2445
2446 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2447 start = start & TARGET_PAGE_MASK;
2448
2449 if( end < start )
2450 /* we've wrapped around */
2451 return -1;
2452 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2453 p = page_find(addr >> TARGET_PAGE_BITS);
2454 if( !p )
2455 return -1;
2456 if( !(p->flags & PAGE_VALID) )
2457 return -1;
2458
2459 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
2460 return -1;
2461 if (flags & PAGE_WRITE) {
2462 if (!(p->flags & PAGE_WRITE_ORG))
2463 return -1;
2464 /* unprotect the page if it was put read-only because it
2465 contains translated code */
2466 if (!(p->flags & PAGE_WRITE)) {
2467 if (!page_unprotect(addr, 0, NULL))
2468 return -1;
2469 }
2470 return 0;
2471 }
2472 }
2473 return 0;
2474}
2475
2476/* called from signal handler: invalidate the code and unprotect the
2477 page. Return TRUE if the fault was succesfully handled. */
2478int page_unprotect(target_ulong address, unsigned long pc, void *puc)
2479{
2480 unsigned int page_index, prot, pindex;
2481 PageDesc *p, *p1;
2482 target_ulong host_start, host_end, addr;
2483
2484 /* Technically this isn't safe inside a signal handler. However we
2485 know this only ever happens in a synchronous SEGV handler, so in
2486 practice it seems to be ok. */
2487 mmap_lock();
2488
2489 host_start = address & qemu_host_page_mask;
2490 page_index = host_start >> TARGET_PAGE_BITS;
2491 p1 = page_find(page_index);
2492 if (!p1) {
2493 mmap_unlock();
2494 return 0;
2495 }
2496 host_end = host_start + qemu_host_page_size;
2497 p = p1;
2498 prot = 0;
2499 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2500 prot |= p->flags;
2501 p++;
2502 }
2503 /* if the page was really writable, then we change its
2504 protection back to writable */
2505 if (prot & PAGE_WRITE_ORG) {
2506 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2507 if (!(p1[pindex].flags & PAGE_WRITE)) {
2508 mprotect((void *)g2h(host_start), qemu_host_page_size,
2509 (prot & PAGE_BITS) | PAGE_WRITE);
2510 p1[pindex].flags |= PAGE_WRITE;
2511 /* and since the content will be modified, we must invalidate
2512 the corresponding translated code. */
2513 tb_invalidate_phys_page(address, pc, puc);
2514#ifdef DEBUG_TB_CHECK
2515 tb_invalidate_check(address);
2516#endif
2517 mmap_unlock();
2518 return 1;
2519 }
2520 }
2521 mmap_unlock();
2522 return 0;
2523}
2524
2525static inline void tlb_set_dirty(CPUState *env,
2526 unsigned long addr, target_ulong vaddr)
2527{
2528}
2529#endif /* defined(CONFIG_USER_ONLY) */
2530
2531#if !defined(CONFIG_USER_ONLY)
2532static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2533 ram_addr_t memory);
2534static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2535 ram_addr_t orig_memory);
2536#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2537 need_subpage) \
2538 do { \
2539 if (addr > start_addr) \
2540 start_addr2 = 0; \
2541 else { \
2542 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2543 if (start_addr2 > 0) \
2544 need_subpage = 1; \
2545 } \
2546 \
2547 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
2548 end_addr2 = TARGET_PAGE_SIZE - 1; \
2549 else { \
2550 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2551 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2552 need_subpage = 1; \
2553 } \
2554 } while (0)
2555
2556
2557/* register physical memory. 'size' must be a multiple of the target
2558 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2559 io memory page */
2560void cpu_register_physical_memory(target_phys_addr_t start_addr,
2561 unsigned long size,
2562 unsigned long phys_offset)
2563{
2564 target_phys_addr_t addr, end_addr;
2565 PhysPageDesc *p;
2566 CPUState *env;
2567 ram_addr_t orig_size = size;
2568 void *subpage;
2569
2570#ifdef USE_KQEMU
2571 /* XXX: should not depend on cpu context */
2572 env = first_cpu;
2573 if (env->kqemu_enabled) {
2574 kqemu_set_phys_mem(start_addr, size, phys_offset);
2575 }
2576#endif
2577 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2578 end_addr = start_addr + (target_phys_addr_t)size;
2579 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
2580 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2581 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
2582 ram_addr_t orig_memory = p->phys_offset;
2583 target_phys_addr_t start_addr2, end_addr2;
2584 int need_subpage = 0;
2585
2586 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2587 need_subpage);
2588 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
2589 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2590 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2591 &p->phys_offset, orig_memory);
2592 } else {
2593 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2594 >> IO_MEM_SHIFT];
2595 }
2596 subpage_register(subpage, start_addr2, end_addr2, phys_offset);
2597 } else {
2598 p->phys_offset = phys_offset;
2599#if !defined(VBOX) || defined(VBOX_WITH_NEW_PHYS_CODE)
2600 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2601 (phys_offset & IO_MEM_ROMD))
2602#else
2603 if ( (phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM
2604 || (phys_offset & IO_MEM_ROMD)
2605 || (phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING)
2606#endif
2607 phys_offset += TARGET_PAGE_SIZE;
2608 }
2609 } else {
2610 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2611 p->phys_offset = phys_offset;
2612#if !defined(VBOX) || defined(VBOX_WITH_NEW_PHYS_CODE)
2613 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2614 (phys_offset & IO_MEM_ROMD))
2615#else
2616 if ( (phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM
2617 || (phys_offset & IO_MEM_ROMD)
2618 || (phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING)
2619#endif
2620 phys_offset += TARGET_PAGE_SIZE;
2621 else {
2622 target_phys_addr_t start_addr2, end_addr2;
2623 int need_subpage = 0;
2624
2625 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2626 end_addr2, need_subpage);
2627
2628 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
2629 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2630 &p->phys_offset, IO_MEM_UNASSIGNED);
2631 subpage_register(subpage, start_addr2, end_addr2,
2632 phys_offset);
2633 }
2634 }
2635 }
2636 }
2637 /* since each CPU stores ram addresses in its TLB cache, we must
2638 reset the modified entries */
2639 /* XXX: slow ! */
2640 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2641 tlb_flush(env, 1);
2642 }
2643}
2644
2645/* XXX: temporary until new memory mapping API */
2646uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
2647{
2648 PhysPageDesc *p;
2649
2650 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2651 if (!p)
2652 return IO_MEM_UNASSIGNED;
2653 return p->phys_offset;
2654}
2655
2656#ifndef VBOX
2657/* XXX: better than nothing */
2658ram_addr_t qemu_ram_alloc(ram_addr_t size)
2659{
2660 ram_addr_t addr;
2661 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
2662 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
2663 (uint64_t)size, (uint64_t)phys_ram_size);
2664 abort();
2665 }
2666 addr = phys_ram_alloc_offset;
2667 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2668 return addr;
2669}
2670
2671void qemu_ram_free(ram_addr_t addr)
2672{
2673}
2674#endif
2675
2676
2677static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
2678{
2679#ifdef DEBUG_UNASSIGNED
2680 printf("Unassigned mem read 0x%08x\n", (int)addr);
2681#endif
2682#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2683 do_unassigned_access(addr, 0, 0, 0, 1);
2684#endif
2685 return 0;
2686}
2687
2688static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2689{
2690#ifdef DEBUG_UNASSIGNED
2691 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2692#endif
2693#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2694 do_unassigned_access(addr, 0, 0, 0, 2);
2695#endif
2696 return 0;
2697}
2698
2699static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2700{
2701#ifdef DEBUG_UNASSIGNED
2702 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2703#endif
2704#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2705 do_unassigned_access(addr, 0, 0, 0, 4);
2706#endif
2707 return 0;
2708}
2709
2710static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2711{
2712#ifdef DEBUG_UNASSIGNED
2713 printf("Unassigned mem write 0x%08x = 0x%x\n", (int)addr, val);
2714#endif
2715}
2716
2717static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2718{
2719#ifdef DEBUG_UNASSIGNED
2720 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2721#endif
2722#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2723 do_unassigned_access(addr, 1, 0, 0, 2);
2724#endif
2725}
2726
2727static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2728{
2729#ifdef DEBUG_UNASSIGNED
2730 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2731#endif
2732#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2733 do_unassigned_access(addr, 1, 0, 0, 4);
2734#endif
2735}
2736static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2737 unassigned_mem_readb,
2738 unassigned_mem_readw,
2739 unassigned_mem_readl,
2740};
2741
2742static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2743 unassigned_mem_writeb,
2744 unassigned_mem_writew,
2745 unassigned_mem_writel,
2746};
2747
2748static void notdirty_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2749{
2750 unsigned long ram_addr;
2751 int dirty_flags;
2752#if defined(VBOX)
2753 ram_addr = addr;
2754#elif
2755 ram_addr = addr - (unsigned long)phys_ram_base;
2756#endif
2757#ifdef VBOX
2758 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2759 dirty_flags = 0xff;
2760 else
2761#endif /* VBOX */
2762 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2763 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2764#if !defined(CONFIG_USER_ONLY)
2765 tb_invalidate_phys_page_fast(ram_addr, 1);
2766# ifdef VBOX
2767 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2768 dirty_flags = 0xff;
2769 else
2770# endif /* VBOX */
2771 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2772#endif
2773 }
2774#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2775 remR3PhysWriteU8(addr, val);
2776#else
2777 stb_p((uint8_t *)(long)addr, val);
2778#endif
2779#ifdef USE_KQEMU
2780 if (cpu_single_env->kqemu_enabled &&
2781 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2782 kqemu_modify_page(cpu_single_env, ram_addr);
2783#endif
2784 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2785#ifdef VBOX
2786 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2787#endif /* !VBOX */
2788 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2789 /* we remove the notdirty callback only if the code has been
2790 flushed */
2791 if (dirty_flags == 0xff)
2792 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_io_vaddr);
2793}
2794
2795static void notdirty_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2796{
2797 unsigned long ram_addr;
2798 int dirty_flags;
2799#if defined(VBOX)
2800 ram_addr = addr;
2801#else
2802 ram_addr = addr - (unsigned long)phys_ram_base;
2803#endif
2804#ifdef VBOX
2805 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2806 dirty_flags = 0xff;
2807 else
2808#endif /* VBOX */
2809 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2810 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2811#if !defined(CONFIG_USER_ONLY)
2812 tb_invalidate_phys_page_fast(ram_addr, 2);
2813# ifdef VBOX
2814 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2815 dirty_flags = 0xff;
2816 else
2817# endif /* VBOX */
2818 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2819#endif
2820 }
2821#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2822 remR3PhysWriteU16(addr, val);
2823#else
2824 stw_p((uint8_t *)(long)addr, val);
2825#endif
2826
2827#ifdef USE_KQEMU
2828 if (cpu_single_env->kqemu_enabled &&
2829 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2830 kqemu_modify_page(cpu_single_env, ram_addr);
2831#endif
2832 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2833#ifdef VBOX
2834 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2835#endif
2836 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2837 /* we remove the notdirty callback only if the code has been
2838 flushed */
2839 if (dirty_flags == 0xff)
2840 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_io_vaddr);
2841}
2842
2843static void notdirty_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2844{
2845 unsigned long ram_addr;
2846 int dirty_flags;
2847#if defined(VBOX)
2848 ram_addr = addr;
2849#else
2850 ram_addr = addr - (unsigned long)phys_ram_base;
2851#endif
2852#ifdef VBOX
2853 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2854 dirty_flags = 0xff;
2855 else
2856#endif /* VBOX */
2857 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2858 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2859#if !defined(CONFIG_USER_ONLY)
2860 tb_invalidate_phys_page_fast(ram_addr, 4);
2861# ifdef VBOX
2862 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2863 dirty_flags = 0xff;
2864 else
2865# endif /* VBOX */
2866 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2867#endif
2868 }
2869#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2870 remR3PhysWriteU32(addr, val);
2871#else
2872 stl_p((uint8_t *)(long)addr, val);
2873#endif
2874#ifdef USE_KQEMU
2875 if (cpu_single_env->kqemu_enabled &&
2876 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2877 kqemu_modify_page(cpu_single_env, ram_addr);
2878#endif
2879 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2880#ifdef VBOX
2881 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2882#endif
2883 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2884 /* we remove the notdirty callback only if the code has been
2885 flushed */
2886 if (dirty_flags == 0xff)
2887 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_io_vaddr);
2888}
2889
2890static CPUReadMemoryFunc *error_mem_read[3] = {
2891 NULL, /* never used */
2892 NULL, /* never used */
2893 NULL, /* never used */
2894};
2895
2896static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2897 notdirty_mem_writeb,
2898 notdirty_mem_writew,
2899 notdirty_mem_writel,
2900};
2901
2902
2903/* Generate a debug exception if a watchpoint has been hit. */
2904static void check_watchpoint(int offset, int flags)
2905{
2906 CPUState *env = cpu_single_env;
2907 target_ulong vaddr;
2908 int i;
2909
2910 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2911 for (i = 0; i < env->nb_watchpoints; i++) {
2912 if (vaddr == env->watchpoint[i].vaddr
2913 && (env->watchpoint[i].type & flags)) {
2914 env->watchpoint_hit = i + 1;
2915 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2916 break;
2917 }
2918 }
2919}
2920
2921/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2922 so these check for a hit then pass through to the normal out-of-line
2923 phys routines. */
2924static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2925{
2926 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
2927 return ldub_phys(addr);
2928}
2929
2930static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2931{
2932 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
2933 return lduw_phys(addr);
2934}
2935
2936static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2937{
2938 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
2939 return ldl_phys(addr);
2940}
2941
2942static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2943 uint32_t val)
2944{
2945 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
2946 stb_phys(addr, val);
2947}
2948
2949static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2950 uint32_t val)
2951{
2952 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
2953 stw_phys(addr, val);
2954}
2955
2956static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2957 uint32_t val)
2958{
2959 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
2960 stl_phys(addr, val);
2961}
2962
2963static CPUReadMemoryFunc *watch_mem_read[3] = {
2964 watch_mem_readb,
2965 watch_mem_readw,
2966 watch_mem_readl,
2967};
2968
2969static CPUWriteMemoryFunc *watch_mem_write[3] = {
2970 watch_mem_writeb,
2971 watch_mem_writew,
2972 watch_mem_writel,
2973};
2974
2975static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2976 unsigned int len)
2977{
2978 uint32_t ret;
2979 unsigned int idx;
2980
2981 idx = SUBPAGE_IDX(addr - mmio->base);
2982#if defined(DEBUG_SUBPAGE)
2983 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2984 mmio, len, addr, idx);
2985#endif
2986 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
2987
2988 return ret;
2989}
2990
2991static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2992 uint32_t value, unsigned int len)
2993{
2994 unsigned int idx;
2995
2996 idx = SUBPAGE_IDX(addr - mmio->base);
2997#if defined(DEBUG_SUBPAGE)
2998 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2999 mmio, len, addr, idx, value);
3000#endif
3001 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
3002}
3003
3004static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
3005{
3006#if defined(DEBUG_SUBPAGE)
3007 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
3008#endif
3009
3010 return subpage_readlen(opaque, addr, 0);
3011}
3012
3013static void subpage_writeb (void *opaque, target_phys_addr_t addr,
3014 uint32_t value)
3015{
3016#if defined(DEBUG_SUBPAGE)
3017 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
3018#endif
3019 subpage_writelen(opaque, addr, value, 0);
3020}
3021
3022static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
3023{
3024#if defined(DEBUG_SUBPAGE)
3025 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
3026#endif
3027
3028 return subpage_readlen(opaque, addr, 1);
3029}
3030
3031static void subpage_writew (void *opaque, target_phys_addr_t addr,
3032 uint32_t value)
3033{
3034#if defined(DEBUG_SUBPAGE)
3035 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
3036#endif
3037 subpage_writelen(opaque, addr, value, 1);
3038}
3039
3040static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
3041{
3042#if defined(DEBUG_SUBPAGE)
3043 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
3044#endif
3045
3046 return subpage_readlen(opaque, addr, 2);
3047}
3048
3049static void subpage_writel (void *opaque,
3050 target_phys_addr_t addr, uint32_t value)
3051{
3052#if defined(DEBUG_SUBPAGE)
3053 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
3054#endif
3055 subpage_writelen(opaque, addr, value, 2);
3056}
3057
3058static CPUReadMemoryFunc *subpage_read[] = {
3059 &subpage_readb,
3060 &subpage_readw,
3061 &subpage_readl,
3062};
3063
3064static CPUWriteMemoryFunc *subpage_write[] = {
3065 &subpage_writeb,
3066 &subpage_writew,
3067 &subpage_writel,
3068};
3069
3070static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
3071 ram_addr_t memory)
3072{
3073 int idx, eidx;
3074 unsigned int i;
3075
3076 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
3077 return -1;
3078 idx = SUBPAGE_IDX(start);
3079 eidx = SUBPAGE_IDX(end);
3080#if defined(DEBUG_SUBPAGE)
3081 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
3082 mmio, start, end, idx, eidx, memory);
3083#endif
3084 memory >>= IO_MEM_SHIFT;
3085 for (; idx <= eidx; idx++) {
3086 for (i = 0; i < 4; i++) {
3087 if (io_mem_read[memory][i]) {
3088 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
3089 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
3090 }
3091 if (io_mem_write[memory][i]) {
3092 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
3093 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
3094 }
3095 }
3096 }
3097
3098 return 0;
3099}
3100
3101static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
3102 ram_addr_t orig_memory)
3103{
3104 subpage_t *mmio;
3105 int subpage_memory;
3106
3107 mmio = qemu_mallocz(sizeof(subpage_t));
3108 if (mmio != NULL) {
3109 mmio->base = base;
3110 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
3111#if defined(DEBUG_SUBPAGE)
3112 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
3113 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
3114#endif
3115 *phys = subpage_memory | IO_MEM_SUBPAGE;
3116 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
3117 }
3118
3119 return mmio;
3120}
3121
3122static void io_mem_init(void)
3123{
3124 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
3125 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
3126 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
3127#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
3128 cpu_register_io_memory(IO_MEM_RAM_MISSING >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
3129 io_mem_nb = 6;
3130#else
3131 io_mem_nb = 5;
3132#endif
3133
3134 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
3135 watch_mem_write, NULL);
3136
3137#ifndef VBOX /* VBOX: we do this later when the RAM is allocated. */
3138 /* alloc dirty bits array */
3139 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
3140 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
3141#endif /* !VBOX */
3142}
3143
3144/* mem_read and mem_write are arrays of functions containing the
3145 function to access byte (index 0), word (index 1) and dword (index
3146 2). Functions can be omitted with a NULL function pointer. The
3147 registered functions may be modified dynamically later.
3148 If io_index is non zero, the corresponding io zone is
3149 modified. If it is zero, a new io zone is allocated. The return
3150 value can be used with cpu_register_physical_memory(). (-1) is
3151 returned if error. */
3152int cpu_register_io_memory(int io_index,
3153 CPUReadMemoryFunc **mem_read,
3154 CPUWriteMemoryFunc **mem_write,
3155 void *opaque)
3156{
3157 int i, subwidth = 0;
3158
3159 if (io_index <= 0) {
3160 if (io_mem_nb >= IO_MEM_NB_ENTRIES)
3161 return -1;
3162 io_index = io_mem_nb++;
3163 } else {
3164 if (io_index >= IO_MEM_NB_ENTRIES)
3165 return -1;
3166 }
3167
3168 for(i = 0;i < 3; i++) {
3169 if (!mem_read[i] || !mem_write[i])
3170 subwidth = IO_MEM_SUBWIDTH;
3171 io_mem_read[io_index][i] = mem_read[i];
3172 io_mem_write[io_index][i] = mem_write[i];
3173 }
3174 io_mem_opaque[io_index] = opaque;
3175 return (io_index << IO_MEM_SHIFT) | subwidth;
3176}
3177
3178CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
3179{
3180 return io_mem_write[io_index >> IO_MEM_SHIFT];
3181}
3182
3183CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
3184{
3185 return io_mem_read[io_index >> IO_MEM_SHIFT];
3186}
3187#endif /* !defined(CONFIG_USER_ONLY) */
3188
3189/* physical memory access (slow version, mainly for debug) */
3190#if defined(CONFIG_USER_ONLY)
3191void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3192 int len, int is_write)
3193{
3194 int l, flags;
3195 target_ulong page;
3196 void * p;
3197
3198 while (len > 0) {
3199 page = addr & TARGET_PAGE_MASK;
3200 l = (page + TARGET_PAGE_SIZE) - addr;
3201 if (l > len)
3202 l = len;
3203 flags = page_get_flags(page);
3204 if (!(flags & PAGE_VALID))
3205 return;
3206 if (is_write) {
3207 if (!(flags & PAGE_WRITE))
3208 return;
3209 /* XXX: this code should not depend on lock_user */
3210 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3211 /* FIXME - should this return an error rather than just fail? */
3212 return;
3213 memcpy(p, buf, len);
3214 unlock_user(p, addr, len);
3215 } else {
3216 if (!(flags & PAGE_READ))
3217 return;
3218 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3219 /* FIXME - should this return an error rather than just fail? */
3220 return;
3221 memcpy(buf, p, len);
3222 unlock_user(p, addr, 0);
3223 }
3224 len -= l;
3225 buf += l;
3226 addr += l;
3227 }
3228}
3229
3230#else
3231void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3232 int len, int is_write)
3233{
3234 int l, io_index;
3235 uint8_t *ptr;
3236 uint32_t val;
3237 target_phys_addr_t page;
3238 unsigned long pd;
3239 PhysPageDesc *p;
3240
3241 while (len > 0) {
3242 page = addr & TARGET_PAGE_MASK;
3243 l = (page + TARGET_PAGE_SIZE) - addr;
3244 if (l > len)
3245 l = len;
3246 p = phys_page_find(page >> TARGET_PAGE_BITS);
3247 if (!p) {
3248 pd = IO_MEM_UNASSIGNED;
3249 } else {
3250 pd = p->phys_offset;
3251 }
3252
3253 if (is_write) {
3254 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3255 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3256 /* XXX: could force cpu_single_env to NULL to avoid
3257 potential bugs */
3258 if (l >= 4 && ((addr & 3) == 0)) {
3259 /* 32 bit write access */
3260#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3261 val = ldl_p(buf);
3262#else
3263 val = *(const uint32_t *)buf;
3264#endif
3265 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3266 l = 4;
3267 } else if (l >= 2 && ((addr & 1) == 0)) {
3268 /* 16 bit write access */
3269#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3270 val = lduw_p(buf);
3271#else
3272 val = *(const uint16_t *)buf;
3273#endif
3274 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
3275 l = 2;
3276 } else {
3277 /* 8 bit write access */
3278#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3279 val = ldub_p(buf);
3280#else
3281 val = *(const uint8_t *)buf;
3282#endif
3283 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
3284 l = 1;
3285 }
3286 } else {
3287 unsigned long addr1;
3288 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3289 /* RAM case */
3290#ifdef VBOX
3291 remR3PhysWrite(addr1, buf, l); NOREF(ptr);
3292#else
3293 ptr = phys_ram_base + addr1;
3294 memcpy(ptr, buf, l);
3295#endif
3296 if (!cpu_physical_memory_is_dirty(addr1)) {
3297 /* invalidate code */
3298 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3299 /* set dirty bit */
3300#ifdef VBOX
3301 if (RT_LIKELY((addr1 >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
3302#endif
3303 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3304 (0xff & ~CODE_DIRTY_FLAG);
3305 }
3306 }
3307 } else {
3308 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3309 !(pd & IO_MEM_ROMD)) {
3310 /* I/O case */
3311 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3312 if (l >= 4 && ((addr & 3) == 0)) {
3313 /* 32 bit read access */
3314 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3315#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3316 stl_p(buf, val);
3317#else
3318 *(uint32_t *)buf = val;
3319#endif
3320 l = 4;
3321 } else if (l >= 2 && ((addr & 1) == 0)) {
3322 /* 16 bit read access */
3323 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
3324#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3325 stw_p(buf, val);
3326#else
3327 *(uint16_t *)buf = val;
3328#endif
3329 l = 2;
3330 } else {
3331 /* 8 bit read access */
3332 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
3333#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3334 stb_p(buf, val);
3335#else
3336 *(uint8_t *)buf = val;
3337#endif
3338 l = 1;
3339 }
3340 } else {
3341 /* RAM case */
3342#ifdef VBOX
3343 remR3PhysRead((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), buf, l); NOREF(ptr);
3344#else
3345 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3346 (addr & ~TARGET_PAGE_MASK);
3347 memcpy(buf, ptr, l);
3348#endif
3349 }
3350 }
3351 len -= l;
3352 buf += l;
3353 addr += l;
3354 }
3355}
3356
3357#ifndef VBOX
3358/* used for ROM loading : can write in RAM and ROM */
3359void cpu_physical_memory_write_rom(target_phys_addr_t addr,
3360 const uint8_t *buf, int len)
3361{
3362 int l;
3363 uint8_t *ptr;
3364 target_phys_addr_t page;
3365 unsigned long pd;
3366 PhysPageDesc *p;
3367
3368 while (len > 0) {
3369 page = addr & TARGET_PAGE_MASK;
3370 l = (page + TARGET_PAGE_SIZE) - addr;
3371 if (l > len)
3372 l = len;
3373 p = phys_page_find(page >> TARGET_PAGE_BITS);
3374 if (!p) {
3375 pd = IO_MEM_UNASSIGNED;
3376 } else {
3377 pd = p->phys_offset;
3378 }
3379
3380 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
3381 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3382 !(pd & IO_MEM_ROMD)) {
3383 /* do nothing */
3384 } else {
3385 unsigned long addr1;
3386 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3387 /* ROM/RAM case */
3388 ptr = phys_ram_base + addr1;
3389 memcpy(ptr, buf, l);
3390 }
3391 len -= l;
3392 buf += l;
3393 addr += l;
3394 }
3395}
3396#endif /* !VBOX */
3397
3398
3399/* warning: addr must be aligned */
3400uint32_t ldl_phys(target_phys_addr_t addr)
3401{
3402 int io_index;
3403 uint8_t *ptr;
3404 uint32_t val;
3405 unsigned long pd;
3406 PhysPageDesc *p;
3407
3408 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3409 if (!p) {
3410 pd = IO_MEM_UNASSIGNED;
3411 } else {
3412 pd = p->phys_offset;
3413 }
3414
3415 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3416 !(pd & IO_MEM_ROMD)) {
3417 /* I/O case */
3418 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3419 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3420 } else {
3421 /* RAM case */
3422#ifndef VBOX
3423 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3424 (addr & ~TARGET_PAGE_MASK);
3425 val = ldl_p(ptr);
3426#else
3427 val = remR3PhysReadU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
3428#endif
3429 }
3430 return val;
3431}
3432
3433/* warning: addr must be aligned */
3434uint64_t ldq_phys(target_phys_addr_t addr)
3435{
3436 int io_index;
3437 uint8_t *ptr;
3438 uint64_t val;
3439 unsigned long pd;
3440 PhysPageDesc *p;
3441
3442 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3443 if (!p) {
3444 pd = IO_MEM_UNASSIGNED;
3445 } else {
3446 pd = p->phys_offset;
3447 }
3448
3449 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3450 !(pd & IO_MEM_ROMD)) {
3451 /* I/O case */
3452 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3453#ifdef TARGET_WORDS_BIGENDIAN
3454 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3455 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3456#else
3457 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3458 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3459#endif
3460 } else {
3461 /* RAM case */
3462#ifndef VBOX
3463 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3464 (addr & ~TARGET_PAGE_MASK);
3465 val = ldq_p(ptr);
3466#else
3467 val = remR3PhysReadU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
3468#endif
3469 }
3470 return val;
3471}
3472
3473/* XXX: optimize */
3474uint32_t ldub_phys(target_phys_addr_t addr)
3475{
3476 uint8_t val;
3477 cpu_physical_memory_read(addr, &val, 1);
3478 return val;
3479}
3480
3481/* XXX: optimize */
3482uint32_t lduw_phys(target_phys_addr_t addr)
3483{
3484 uint16_t val;
3485 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3486 return tswap16(val);
3487}
3488
3489/* warning: addr must be aligned. The ram page is not masked as dirty
3490 and the code inside is not invalidated. It is useful if the dirty
3491 bits are used to track modified PTEs */
3492void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3493{
3494 int io_index;
3495 uint8_t *ptr;
3496 unsigned long pd;
3497 PhysPageDesc *p;
3498
3499 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3500 if (!p) {
3501 pd = IO_MEM_UNASSIGNED;
3502 } else {
3503 pd = p->phys_offset;
3504 }
3505
3506 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3507 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3508 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3509 } else {
3510#ifndef VBOX
3511 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3512 (addr & ~TARGET_PAGE_MASK);
3513 stl_p(ptr, val);
3514#else
3515 remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
3516#endif
3517#ifndef VBOX
3518 if (unlikely(in_migration)) {
3519 if (!cpu_physical_memory_is_dirty(addr1)) {
3520 /* invalidate code */
3521 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3522 /* set dirty bit */
3523 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3524 (0xff & ~CODE_DIRTY_FLAG);
3525 }
3526 }
3527#endif
3528 }
3529}
3530
3531void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3532{
3533 int io_index;
3534 uint8_t *ptr;
3535 unsigned long pd;
3536 PhysPageDesc *p;
3537
3538 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3539 if (!p) {
3540 pd = IO_MEM_UNASSIGNED;
3541 } else {
3542 pd = p->phys_offset;
3543 }
3544
3545 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3546 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3547#ifdef TARGET_WORDS_BIGENDIAN
3548 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3549 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3550#else
3551 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3552 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3553#endif
3554 } else {
3555#ifndef VBOX
3556 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3557 (addr & ~TARGET_PAGE_MASK);
3558 stq_p(ptr, val);
3559#else
3560 remR3PhysWriteU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
3561#endif
3562 }
3563}
3564
3565
3566/* warning: addr must be aligned */
3567void stl_phys(target_phys_addr_t addr, uint32_t val)
3568{
3569 int io_index;
3570 uint8_t *ptr;
3571 unsigned long pd;
3572 PhysPageDesc *p;
3573
3574 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3575 if (!p) {
3576 pd = IO_MEM_UNASSIGNED;
3577 } else {
3578 pd = p->phys_offset;
3579 }
3580
3581 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3582 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3583 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3584 } else {
3585 unsigned long addr1;
3586 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3587 /* RAM case */
3588#ifndef VBOX
3589 ptr = phys_ram_base + addr1;
3590 stl_p(ptr, val);
3591#else
3592 remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
3593#endif
3594 if (!cpu_physical_memory_is_dirty(addr1)) {
3595 /* invalidate code */
3596 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3597 /* set dirty bit */
3598#ifdef VBOX
3599 if (RT_LIKELY((addr1 >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
3600#endif
3601 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3602 (0xff & ~CODE_DIRTY_FLAG);
3603 }
3604 }
3605}
3606
3607/* XXX: optimize */
3608void stb_phys(target_phys_addr_t addr, uint32_t val)
3609{
3610 uint8_t v = val;
3611 cpu_physical_memory_write(addr, &v, 1);
3612}
3613
3614/* XXX: optimize */
3615void stw_phys(target_phys_addr_t addr, uint32_t val)
3616{
3617 uint16_t v = tswap16(val);
3618 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3619}
3620
3621/* XXX: optimize */
3622void stq_phys(target_phys_addr_t addr, uint64_t val)
3623{
3624 val = tswap64(val);
3625 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3626}
3627
3628#endif
3629
3630/* virtual memory access for debug */
3631int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3632 uint8_t *buf, int len, int is_write)
3633{
3634 int l;
3635 target_ulong page, phys_addr;
3636
3637 while (len > 0) {
3638 page = addr & TARGET_PAGE_MASK;
3639 phys_addr = cpu_get_phys_page_debug(env, page);
3640 /* if no physical page mapped, return an error */
3641 if (phys_addr == -1)
3642 return -1;
3643 l = (page + TARGET_PAGE_SIZE) - addr;
3644 if (l > len)
3645 l = len;
3646 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
3647 buf, l, is_write);
3648 len -= l;
3649 buf += l;
3650 addr += l;
3651 }
3652 return 0;
3653}
3654
3655/* in deterministic execution mode, instructions doing device I/Os
3656 must be at the end of the TB */
3657void cpu_io_recompile(CPUState *env, void *retaddr)
3658{
3659 TranslationBlock *tb;
3660 uint32_t n, cflags;
3661 target_ulong pc, cs_base;
3662 uint64_t flags;
3663
3664 tb = tb_find_pc((unsigned long)retaddr);
3665 if (!tb) {
3666 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3667 retaddr);
3668 }
3669 n = env->icount_decr.u16.low + tb->icount;
3670 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3671 /* Calculate how many instructions had been executed before the fault
3672 occurred. */
3673 n = n - env->icount_decr.u16.low;
3674 /* Generate a new TB ending on the I/O insn. */
3675 n++;
3676 /* On MIPS and SH, delay slot instructions can only be restarted if
3677 they were already the first instruction in the TB. If this is not
3678 the first instruction in a TB then re-execute the preceding
3679 branch. */
3680#if defined(TARGET_MIPS)
3681 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3682 env->active_tc.PC -= 4;
3683 env->icount_decr.u16.low++;
3684 env->hflags &= ~MIPS_HFLAG_BMASK;
3685 }
3686#elif defined(TARGET_SH4)
3687 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3688 && n > 1) {
3689 env->pc -= 2;
3690 env->icount_decr.u16.low++;
3691 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3692 }
3693#endif
3694 /* This should never happen. */
3695 if (n > CF_COUNT_MASK)
3696 cpu_abort(env, "TB too big during recompile");
3697
3698 cflags = n | CF_LAST_IO;
3699 pc = tb->pc;
3700 cs_base = tb->cs_base;
3701 flags = tb->flags;
3702 tb_phys_invalidate(tb, -1);
3703 /* FIXME: In theory this could raise an exception. In practice
3704 we have already translated the block once so it's probably ok. */
3705 tb_gen_code(env, pc, cs_base, flags, cflags);
3706 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
3707 the first in the TB) then we end up generating a whole new TB and
3708 repeating the fault, which is horribly inefficient.
3709 Better would be to execute just this insn uncached, or generate a
3710 second new TB. */
3711 cpu_resume_from_signal(env, NULL);
3712}
3713
3714#ifndef VBOX
3715void dump_exec_info(FILE *f,
3716 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3717{
3718 int i, target_code_size, max_target_code_size;
3719 int direct_jmp_count, direct_jmp2_count, cross_page;
3720 TranslationBlock *tb;
3721
3722 target_code_size = 0;
3723 max_target_code_size = 0;
3724 cross_page = 0;
3725 direct_jmp_count = 0;
3726 direct_jmp2_count = 0;
3727 for(i = 0; i < nb_tbs; i++) {
3728 tb = &tbs[i];
3729 target_code_size += tb->size;
3730 if (tb->size > max_target_code_size)
3731 max_target_code_size = tb->size;
3732 if (tb->page_addr[1] != -1)
3733 cross_page++;
3734 if (tb->tb_next_offset[0] != 0xffff) {
3735 direct_jmp_count++;
3736 if (tb->tb_next_offset[1] != 0xffff) {
3737 direct_jmp2_count++;
3738 }
3739 }
3740 }
3741 /* XXX: avoid using doubles ? */
3742 cpu_fprintf(f, "Translation buffer state:\n");
3743 cpu_fprintf(f, "gen code size %ld/%ld\n",
3744 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3745 cpu_fprintf(f, "TB count %d/%d\n",
3746 nb_tbs, code_gen_max_blocks);
3747 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
3748 nb_tbs ? target_code_size / nb_tbs : 0,
3749 max_target_code_size);
3750 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
3751 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3752 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
3753 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3754 cross_page,
3755 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3756 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
3757 direct_jmp_count,
3758 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3759 direct_jmp2_count,
3760 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
3761 cpu_fprintf(f, "\nStatistics:\n");
3762 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3763 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3764 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
3765 tcg_dump_info(f, cpu_fprintf);
3766}
3767#endif /* !VBOX */
3768
3769#if !defined(CONFIG_USER_ONLY)
3770
3771#define MMUSUFFIX _cmmu
3772#define GETPC() NULL
3773#define env cpu_single_env
3774#define SOFTMMU_CODE_ACCESS
3775
3776#define SHIFT 0
3777#include "softmmu_template.h"
3778
3779#define SHIFT 1
3780#include "softmmu_template.h"
3781
3782#define SHIFT 2
3783#include "softmmu_template.h"
3784
3785#define SHIFT 3
3786#include "softmmu_template.h"
3787
3788#undef env
3789
3790#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette