VirtualBox

source: vbox/trunk/src/recompiler_new/exec.c@ 17401

Last change on this file since 17401 was 17342, checked in by vboxsync, 16 years ago

REM: remove excessive assertions, as new HVA -> PGA works just fine

  • Property svn:eol-style set to native
File size: 112.7 KB
Line 
1/*
2 * virtual page mapping and translated block handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#include "config.h"
30#ifndef VBOX
31#ifdef _WIN32
32#include <windows.h>
33#else
34#include <sys/types.h>
35#include <sys/mman.h>
36#endif
37#include <stdlib.h>
38#include <stdio.h>
39#include <stdarg.h>
40#include <string.h>
41#include <errno.h>
42#include <unistd.h>
43#include <inttypes.h>
44#else /* VBOX */
45# include <stdlib.h>
46# include <stdio.h>
47# include <iprt/alloc.h>
48# include <iprt/string.h>
49# include <iprt/param.h>
50# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
51#endif /* VBOX */
52
53#include "cpu.h"
54#include "exec-all.h"
55#if defined(CONFIG_USER_ONLY)
56#include <qemu.h>
57#endif
58
59//#define DEBUG_TB_INVALIDATE
60//#define DEBUG_FLUSH
61//#define DEBUG_TLB
62//#define DEBUG_UNASSIGNED
63
64/* make various TB consistency checks */
65//#define DEBUG_TB_CHECK
66//#define DEBUG_TLB_CHECK
67
68#if !defined(CONFIG_USER_ONLY)
69/* TB consistency checks only implemented for usermode emulation. */
70#undef DEBUG_TB_CHECK
71#endif
72
73#define SMC_BITMAP_USE_THRESHOLD 10
74
75#define MMAP_AREA_START 0x00000000
76#define MMAP_AREA_END 0xa8000000
77
78#if defined(TARGET_SPARC64)
79#define TARGET_PHYS_ADDR_SPACE_BITS 41
80#elif defined(TARGET_SPARC)
81#define TARGET_PHYS_ADDR_SPACE_BITS 36
82#elif defined(TARGET_ALPHA)
83#define TARGET_PHYS_ADDR_SPACE_BITS 42
84#define TARGET_VIRT_ADDR_SPACE_BITS 42
85#elif defined(TARGET_PPC64)
86#define TARGET_PHYS_ADDR_SPACE_BITS 42
87#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
88#define TARGET_PHYS_ADDR_SPACE_BITS 42
89#elif defined(TARGET_I386) && !defined(USE_KQEMU)
90#define TARGET_PHYS_ADDR_SPACE_BITS 36
91#else
92/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
93#define TARGET_PHYS_ADDR_SPACE_BITS 32
94#endif
95
96static TranslationBlock *tbs;
97int code_gen_max_blocks;
98TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
99static int nb_tbs;
100/* any access to the tbs or the page table must use this lock */
101spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
102
103#ifndef VBOX
104#if defined(__arm__) || defined(__sparc_v9__)
105/* The prologue must be reachable with a direct jump. ARM and Sparc64
106 have limited branch ranges (possibly also PPC) so place it in a
107 section close to code segment. */
108#define code_gen_section \
109 __attribute__((__section__(".gen_code"))) \
110 __attribute__((aligned (32)))
111#else
112#define code_gen_section \
113 __attribute__((aligned (32)))
114#endif
115uint8_t code_gen_prologue[1024] code_gen_section;
116
117#else /* VBOX */
118extern uint8_t* code_gen_prologue;
119#endif /* VBOX */
120
121static uint8_t *code_gen_buffer;
122static unsigned long code_gen_buffer_size;
123/* threshold to flush the translated code buffer */
124static unsigned long code_gen_buffer_max_size;
125uint8_t *code_gen_ptr;
126
127#ifndef VBOX
128#if !defined(CONFIG_USER_ONLY)
129ram_addr_t phys_ram_size;
130int phys_ram_fd;
131uint8_t *phys_ram_base;
132uint8_t *phys_ram_dirty;
133static int in_migration;
134static ram_addr_t phys_ram_alloc_offset = 0;
135#endif
136#else /* VBOX */
137RTGCPHYS phys_ram_size;
138/* we have memory ranges (the high PC-BIOS mapping) which
139 causes some pages to fall outside the dirty map here. */
140uint32_t phys_ram_dirty_size;
141#endif /* VBOX */
142#if !defined(VBOX)
143uint8_t *phys_ram_base;
144#endif
145uint8_t *phys_ram_dirty;
146
147CPUState *first_cpu;
148/* current CPU in the current thread. It is only valid inside
149 cpu_exec() */
150CPUState *cpu_single_env;
151/* 0 = Do not count executed instructions.
152 1 = Precise instruction counting.
153 2 = Adaptive rate instruction counting. */
154int use_icount = 0;
155/* Current instruction counter. While executing translated code this may
156 include some instructions that have not yet been executed. */
157int64_t qemu_icount;
158
159typedef struct PageDesc {
160 /* list of TBs intersecting this ram page */
161 TranslationBlock *first_tb;
162 /* in order to optimize self modifying code, we count the number
163 of lookups we do to a given page to use a bitmap */
164 unsigned int code_write_count;
165 uint8_t *code_bitmap;
166#if defined(CONFIG_USER_ONLY)
167 unsigned long flags;
168#endif
169} PageDesc;
170
171typedef struct PhysPageDesc {
172 /* offset in host memory of the page + io_index in the low 12 bits */
173 ram_addr_t phys_offset;
174} PhysPageDesc;
175
176#define L2_BITS 10
177#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
178/* XXX: this is a temporary hack for alpha target.
179 * In the future, this is to be replaced by a multi-level table
180 * to actually be able to handle the complete 64 bits address space.
181 */
182#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
183#else
184#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
185#endif
186
187#define L1_SIZE (1 << L1_BITS)
188#define L2_SIZE (1 << L2_BITS)
189
190static void io_mem_init(void);
191
192unsigned long qemu_real_host_page_size;
193unsigned long qemu_host_page_bits;
194unsigned long qemu_host_page_size;
195unsigned long qemu_host_page_mask;
196
197/* XXX: for system emulation, it could just be an array */
198static PageDesc *l1_map[L1_SIZE];
199static PhysPageDesc **l1_phys_map;
200
201#if !defined(CONFIG_USER_ONLY)
202static void io_mem_init(void);
203
204/* io memory support */
205CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
206CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
207void *io_mem_opaque[IO_MEM_NB_ENTRIES];
208static int io_mem_nb;
209static int io_mem_watch;
210#endif
211
212#ifndef VBOX
213/* log support */
214static const char *logfilename = "/tmp/qemu.log";
215#endif /* !VBOX */
216FILE *logfile;
217int loglevel;
218#ifndef VBOX
219static int log_append = 0;
220#endif
221
222/* statistics */
223static int tlb_flush_count;
224static int tb_flush_count;
225#ifndef VBOX
226static int tb_phys_invalidate_count;
227#endif /* !VBOX */
228
229#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
230typedef struct subpage_t {
231 target_phys_addr_t base;
232 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
233 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
234 void *opaque[TARGET_PAGE_SIZE][2][4];
235} subpage_t;
236
237
238#ifndef VBOX
239#ifdef _WIN32
240static void map_exec(void *addr, long size)
241{
242 DWORD old_protect;
243 VirtualProtect(addr, size,
244 PAGE_EXECUTE_READWRITE, &old_protect);
245
246}
247#else
248static void map_exec(void *addr, long size)
249{
250 unsigned long start, end, page_size;
251
252 page_size = getpagesize();
253 start = (unsigned long)addr;
254 start &= ~(page_size - 1);
255
256 end = (unsigned long)addr + size;
257 end += page_size - 1;
258 end &= ~(page_size - 1);
259
260 mprotect((void *)start, end - start,
261 PROT_READ | PROT_WRITE | PROT_EXEC);
262}
263#endif
264#else // VBOX
265static void map_exec(void *addr, long size)
266{
267 RTMemProtect(addr, size,
268 RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
269}
270#endif
271
272static void page_init(void)
273{
274 /* NOTE: we can always suppose that qemu_host_page_size >=
275 TARGET_PAGE_SIZE */
276#ifdef VBOX
277 RTMemProtect(code_gen_buffer, sizeof(code_gen_buffer),
278 RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
279 qemu_real_host_page_size = PAGE_SIZE;
280#else /* !VBOX */
281#ifdef _WIN32
282 {
283 SYSTEM_INFO system_info;
284 DWORD old_protect;
285
286 GetSystemInfo(&system_info);
287 qemu_real_host_page_size = system_info.dwPageSize;
288 }
289#else
290 qemu_real_host_page_size = getpagesize();
291#endif
292#endif /* !VBOX */
293
294 if (qemu_host_page_size == 0)
295 qemu_host_page_size = qemu_real_host_page_size;
296 if (qemu_host_page_size < TARGET_PAGE_SIZE)
297 qemu_host_page_size = TARGET_PAGE_SIZE;
298 qemu_host_page_bits = 0;
299#ifndef VBOX
300 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
301#else
302 while ((1 << qemu_host_page_bits) < (int)qemu_host_page_size)
303#endif
304 qemu_host_page_bits++;
305 qemu_host_page_mask = ~(qemu_host_page_size - 1);
306 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
307 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
308#ifdef VBOX
309 /* We use other means to set reserved bit on our pages */
310#else
311#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
312 {
313 long long startaddr, endaddr;
314 FILE *f;
315 int n;
316
317 mmap_lock();
318 last_brk = (unsigned long)sbrk(0);
319 f = fopen("/proc/self/maps", "r");
320 if (f) {
321 do {
322 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
323 if (n == 2) {
324 startaddr = MIN(startaddr,
325 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
326 endaddr = MIN(endaddr,
327 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
328 page_set_flags(startaddr & TARGET_PAGE_MASK,
329 TARGET_PAGE_ALIGN(endaddr),
330 PAGE_RESERVED);
331 }
332 } while (!feof(f));
333 fclose(f);
334 }
335 mmap_unlock();
336 }
337#endif
338#endif
339}
340
341#ifndef VBOX
342static inline PageDesc **page_l1_map(target_ulong index)
343#else
344DECLINLINE(PageDesc **) page_l1_map(target_ulong index)
345#endif
346{
347#if TARGET_LONG_BITS > 32
348 /* Host memory outside guest VM. For 32-bit targets we have already
349 excluded high addresses. */
350 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
351 return NULL;
352#endif
353 return &l1_map[index >> L2_BITS];
354}
355
356#ifndef VBOX
357static inline PageDesc *page_find_alloc(target_ulong index)
358#else
359DECLINLINE(PageDesc *) page_find_alloc(target_ulong index)
360#endif
361{
362 PageDesc **lp, *p;
363 lp = page_l1_map(index);
364 if (!lp)
365 return NULL;
366
367 p = *lp;
368 if (!p) {
369 /* allocate if not found */
370#if defined(CONFIG_USER_ONLY)
371 unsigned long addr;
372 size_t len = sizeof(PageDesc) * L2_SIZE;
373 /* Don't use qemu_malloc because it may recurse. */
374 p = mmap(0, len, PROT_READ | PROT_WRITE,
375 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
376 *lp = p;
377 addr = h2g(p);
378 if (addr == (target_ulong)addr) {
379 page_set_flags(addr & TARGET_PAGE_MASK,
380 TARGET_PAGE_ALIGN(addr + len),
381 PAGE_RESERVED);
382 }
383#else
384 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
385 *lp = p;
386#endif
387 }
388 return p + (index & (L2_SIZE - 1));
389}
390
391#ifndef VBOX
392static inline PageDesc *page_find(target_ulong index)
393#else
394DECLINLINE(PageDesc *) page_find(target_ulong index)
395#endif
396{
397 PageDesc **lp, *p;
398 lp = page_l1_map(index);
399 if (!lp)
400 return NULL;
401
402 p = *lp;
403 if (!p)
404 return 0;
405 return p + (index & (L2_SIZE - 1));
406}
407
408static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
409{
410 void **lp, **p;
411 PhysPageDesc *pd;
412
413 p = (void **)l1_phys_map;
414#if TARGET_PHYS_ADDR_SPACE_BITS > 32
415
416#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
417#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
418#endif
419 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
420 p = *lp;
421 if (!p) {
422 /* allocate if not found */
423 if (!alloc)
424 return NULL;
425 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
426 memset(p, 0, sizeof(void *) * L1_SIZE);
427 *lp = p;
428 }
429#endif
430 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
431 pd = *lp;
432 if (!pd) {
433 int i;
434 /* allocate if not found */
435 if (!alloc)
436 return NULL;
437 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
438 *lp = pd;
439 for (i = 0; i < L2_SIZE; i++)
440 pd[i].phys_offset = IO_MEM_UNASSIGNED;
441 }
442#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
443 pd = ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
444 if (RT_UNLIKELY((pd->phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING))
445 remR3GrowDynRange(pd->phys_offset & TARGET_PAGE_MASK);
446 return pd;
447#else
448 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
449#endif
450}
451
452#ifndef VBOX
453static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
454#else
455DECLINLINE(PhysPageDesc *) phys_page_find(target_phys_addr_t index)
456#endif
457{
458 return phys_page_find_alloc(index, 0);
459}
460
461#if !defined(CONFIG_USER_ONLY)
462static void tlb_protect_code(ram_addr_t ram_addr);
463static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
464 target_ulong vaddr);
465#define mmap_lock() do { } while(0)
466#define mmap_unlock() do { } while(0)
467#endif
468
469#ifdef VBOX
470/** @todo nike: isn't 32M too much ? */
471#endif
472#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
473
474#if defined(CONFIG_USER_ONLY)
475/* Currently it is not recommanded to allocate big chunks of data in
476 user mode. It will change when a dedicated libc will be used */
477#define USE_STATIC_CODE_GEN_BUFFER
478#endif
479
480/* VBox allocates codegen buffer dynamically */
481#ifndef VBOX
482#ifdef USE_STATIC_CODE_GEN_BUFFER
483static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
484#endif
485#endif
486
487static void code_gen_alloc(unsigned long tb_size)
488{
489#ifdef USE_STATIC_CODE_GEN_BUFFER
490 code_gen_buffer = static_code_gen_buffer;
491 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
492 map_exec(code_gen_buffer, code_gen_buffer_size);
493#else
494 code_gen_buffer_size = tb_size;
495 if (code_gen_buffer_size == 0) {
496#if defined(CONFIG_USER_ONLY)
497 /* in user mode, phys_ram_size is not meaningful */
498 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
499#else
500 /* XXX: needs ajustments */
501 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
502#endif
503 }
504 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
505 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
506 /* The code gen buffer location may have constraints depending on
507 the host cpu and OS */
508#ifdef VBOX
509 code_gen_buffer = RTMemExecAlloc(code_gen_buffer_size);
510
511 if (!code_gen_buffer) {
512 LogRel(("REM: failed allocate codegen buffer %lld\n",
513 code_gen_buffer_size));
514 return;
515 }
516#else //!VBOX
517#if defined(__linux__)
518 {
519 int flags;
520 void *start = NULL;
521
522 flags = MAP_PRIVATE | MAP_ANONYMOUS;
523#if defined(__x86_64__)
524 flags |= MAP_32BIT;
525 /* Cannot map more than that */
526 if (code_gen_buffer_size > (800 * 1024 * 1024))
527 code_gen_buffer_size = (800 * 1024 * 1024);
528#elif defined(__sparc_v9__)
529 // Map the buffer below 2G, so we can use direct calls and branches
530 flags |= MAP_FIXED;
531 start = (void *) 0x60000000UL;
532 if (code_gen_buffer_size > (512 * 1024 * 1024))
533 code_gen_buffer_size = (512 * 1024 * 1024);
534#endif
535 code_gen_buffer = mmap(start, code_gen_buffer_size,
536 PROT_WRITE | PROT_READ | PROT_EXEC,
537 flags, -1, 0);
538 if (code_gen_buffer == MAP_FAILED) {
539 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
540 exit(1);
541 }
542 }
543#elif defined(__FreeBSD__)
544 {
545 int flags;
546 void *addr = NULL;
547 flags = MAP_PRIVATE | MAP_ANONYMOUS;
548#if defined(__x86_64__)
549 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
550 * 0x40000000 is free */
551 flags |= MAP_FIXED;
552 addr = (void *)0x40000000;
553 /* Cannot map more than that */
554 if (code_gen_buffer_size > (800 * 1024 * 1024))
555 code_gen_buffer_size = (800 * 1024 * 1024);
556#endif
557 code_gen_buffer = mmap(addr, code_gen_buffer_size,
558 PROT_WRITE | PROT_READ | PROT_EXEC,
559 flags, -1, 0);
560 if (code_gen_buffer == MAP_FAILED) {
561 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
562 exit(1);
563 }
564 }
565#else
566 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
567 if (!code_gen_buffer) {
568 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
569 exit(1);
570 }
571 map_exec(code_gen_buffer, code_gen_buffer_size);
572#endif
573 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
574#endif /* !VBOX */
575#endif /* !USE_STATIC_CODE_GEN_BUFFER */
576#ifndef VBOX
577 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
578#else
579 map_exec(code_gen_prologue, _1K);
580#endif
581
582 code_gen_buffer_max_size = code_gen_buffer_size -
583 code_gen_max_block_size();
584 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
585 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
586}
587
588/* Must be called before using the QEMU cpus. 'tb_size' is the size
589 (in bytes) allocated to the translation buffer. Zero means default
590 size. */
591void cpu_exec_init_all(unsigned long tb_size)
592{
593 cpu_gen_init();
594 code_gen_alloc(tb_size);
595 code_gen_ptr = code_gen_buffer;
596 page_init();
597#if !defined(CONFIG_USER_ONLY)
598 io_mem_init();
599#endif
600}
601
602#ifndef VBOX
603#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
604
605#define CPU_COMMON_SAVE_VERSION 1
606
607static void cpu_common_save(QEMUFile *f, void *opaque)
608{
609 CPUState *env = opaque;
610
611 qemu_put_be32s(f, &env->halted);
612 qemu_put_be32s(f, &env->interrupt_request);
613}
614
615static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
616{
617 CPUState *env = opaque;
618
619 if (version_id != CPU_COMMON_SAVE_VERSION)
620 return -EINVAL;
621
622 qemu_get_be32s(f, &env->halted);
623 qemu_get_be32s(f, &env->interrupt_request);
624 tlb_flush(env, 1);
625
626 return 0;
627}
628#endif
629#endif //!VBOX
630
631void cpu_exec_init(CPUState *env)
632{
633 CPUState **penv;
634 int cpu_index;
635
636 env->next_cpu = NULL;
637 penv = &first_cpu;
638 cpu_index = 0;
639 while (*penv != NULL) {
640 penv = (CPUState **)&(*penv)->next_cpu;
641 cpu_index++;
642 }
643 env->cpu_index = cpu_index;
644 env->nb_watchpoints = 0;
645 *penv = env;
646#ifndef VBOX
647#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
648 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
649 cpu_common_save, cpu_common_load, env);
650 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
651 cpu_save, cpu_load, env);
652#endif
653#endif // !VBOX
654}
655
656#ifndef VBOX
657static inline void invalidate_page_bitmap(PageDesc *p)
658#else
659DECLINLINE(void) invalidate_page_bitmap(PageDesc *p)
660#endif
661{
662 if (p->code_bitmap) {
663 qemu_free(p->code_bitmap);
664 p->code_bitmap = NULL;
665 }
666 p->code_write_count = 0;
667}
668
669/* set to NULL all the 'first_tb' fields in all PageDescs */
670static void page_flush_tb(void)
671{
672 int i, j;
673 PageDesc *p;
674
675 for(i = 0; i < L1_SIZE; i++) {
676 p = l1_map[i];
677 if (p) {
678 for(j = 0; j < L2_SIZE; j++) {
679 p->first_tb = NULL;
680 invalidate_page_bitmap(p);
681 p++;
682 }
683 }
684 }
685}
686
687/* flush all the translation blocks */
688/* XXX: tb_flush is currently not thread safe */
689void tb_flush(CPUState *env1)
690{
691 CPUState *env;
692#if defined(DEBUG_FLUSH)
693 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
694 (unsigned long)(code_gen_ptr - code_gen_buffer),
695 nb_tbs, nb_tbs > 0 ?
696 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
697#endif
698 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
699 cpu_abort(env1, "Internal error: code buffer overflow\n");
700
701 nb_tbs = 0;
702
703 for(env = first_cpu; env != NULL; env = env->next_cpu) {
704 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
705 }
706
707 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
708 page_flush_tb();
709
710 code_gen_ptr = code_gen_buffer;
711 /* XXX: flush processor icache at this point if cache flush is
712 expensive */
713 tb_flush_count++;
714}
715
716#ifdef DEBUG_TB_CHECK
717static void tb_invalidate_check(target_ulong address)
718{
719 TranslationBlock *tb;
720 int i;
721 address &= TARGET_PAGE_MASK;
722 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
723 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
724 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
725 address >= tb->pc + tb->size)) {
726 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
727 address, (long)tb->pc, tb->size);
728 }
729 }
730 }
731}
732
733/* verify that all the pages have correct rights for code */
734static void tb_page_check(void)
735{
736 TranslationBlock *tb;
737 int i, flags1, flags2;
738
739 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
740 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
741 flags1 = page_get_flags(tb->pc);
742 flags2 = page_get_flags(tb->pc + tb->size - 1);
743 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
744 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
745 (long)tb->pc, tb->size, flags1, flags2);
746 }
747 }
748 }
749}
750
751static void tb_jmp_check(TranslationBlock *tb)
752{
753 TranslationBlock *tb1;
754 unsigned int n1;
755
756 /* suppress any remaining jumps to this TB */
757 tb1 = tb->jmp_first;
758 for(;;) {
759 n1 = (long)tb1 & 3;
760 tb1 = (TranslationBlock *)((long)tb1 & ~3);
761 if (n1 == 2)
762 break;
763 tb1 = tb1->jmp_next[n1];
764 }
765 /* check end of list */
766 if (tb1 != tb) {
767 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
768 }
769}
770#endif // DEBUG_TB_CHECK
771
772/* invalidate one TB */
773#ifndef VBOX
774static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
775 int next_offset)
776#else
777DECLINLINE(void) tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
778 int next_offset)
779#endif
780{
781 TranslationBlock *tb1;
782 for(;;) {
783 tb1 = *ptb;
784 if (tb1 == tb) {
785 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
786 break;
787 }
788 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
789 }
790}
791
792#ifndef VBOX
793static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
794#else
795DECLINLINE(void) tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
796#endif
797{
798 TranslationBlock *tb1;
799 unsigned int n1;
800
801 for(;;) {
802 tb1 = *ptb;
803 n1 = (long)tb1 & 3;
804 tb1 = (TranslationBlock *)((long)tb1 & ~3);
805 if (tb1 == tb) {
806 *ptb = tb1->page_next[n1];
807 break;
808 }
809 ptb = &tb1->page_next[n1];
810 }
811}
812
813#ifndef VBOX
814static inline void tb_jmp_remove(TranslationBlock *tb, int n)
815#else
816DECLINLINE(void) tb_jmp_remove(TranslationBlock *tb, int n)
817#endif
818{
819 TranslationBlock *tb1, **ptb;
820 unsigned int n1;
821
822 ptb = &tb->jmp_next[n];
823 tb1 = *ptb;
824 if (tb1) {
825 /* find tb(n) in circular list */
826 for(;;) {
827 tb1 = *ptb;
828 n1 = (long)tb1 & 3;
829 tb1 = (TranslationBlock *)((long)tb1 & ~3);
830 if (n1 == n && tb1 == tb)
831 break;
832 if (n1 == 2) {
833 ptb = &tb1->jmp_first;
834 } else {
835 ptb = &tb1->jmp_next[n1];
836 }
837 }
838 /* now we can suppress tb(n) from the list */
839 *ptb = tb->jmp_next[n];
840
841 tb->jmp_next[n] = NULL;
842 }
843}
844
845/* reset the jump entry 'n' of a TB so that it is not chained to
846 another TB */
847#ifndef VBOX
848static inline void tb_reset_jump(TranslationBlock *tb, int n)
849#else
850DECLINLINE(void) tb_reset_jump(TranslationBlock *tb, int n)
851#endif
852{
853 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
854}
855
856void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
857{
858 CPUState *env;
859 PageDesc *p;
860 unsigned int h, n1;
861 target_phys_addr_t phys_pc;
862 TranslationBlock *tb1, *tb2;
863
864 /* remove the TB from the hash list */
865 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
866 h = tb_phys_hash_func(phys_pc);
867 tb_remove(&tb_phys_hash[h], tb,
868 offsetof(TranslationBlock, phys_hash_next));
869
870 /* remove the TB from the page list */
871 if (tb->page_addr[0] != page_addr) {
872 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
873 tb_page_remove(&p->first_tb, tb);
874 invalidate_page_bitmap(p);
875 }
876 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
877 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
878 tb_page_remove(&p->first_tb, tb);
879 invalidate_page_bitmap(p);
880 }
881
882 tb_invalidated_flag = 1;
883
884 /* remove the TB from the hash list */
885 h = tb_jmp_cache_hash_func(tb->pc);
886 for(env = first_cpu; env != NULL; env = env->next_cpu) {
887 if (env->tb_jmp_cache[h] == tb)
888 env->tb_jmp_cache[h] = NULL;
889 }
890
891 /* suppress this TB from the two jump lists */
892 tb_jmp_remove(tb, 0);
893 tb_jmp_remove(tb, 1);
894
895 /* suppress any remaining jumps to this TB */
896 tb1 = tb->jmp_first;
897 for(;;) {
898 n1 = (long)tb1 & 3;
899 if (n1 == 2)
900 break;
901 tb1 = (TranslationBlock *)((long)tb1 & ~3);
902 tb2 = tb1->jmp_next[n1];
903 tb_reset_jump(tb1, n1);
904 tb1->jmp_next[n1] = NULL;
905 tb1 = tb2;
906 }
907 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
908
909#ifndef VBOX
910 tb_phys_invalidate_count++;
911#endif
912}
913
914
915#ifdef VBOX
916void tb_invalidate_virt(CPUState *env, uint32_t eip)
917{
918# if 1
919 tb_flush(env);
920# else
921 uint8_t *cs_base, *pc;
922 unsigned int flags, h, phys_pc;
923 TranslationBlock *tb, **ptb;
924
925 flags = env->hflags;
926 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
927 cs_base = env->segs[R_CS].base;
928 pc = cs_base + eip;
929
930 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
931 flags);
932
933 if(tb)
934 {
935# ifdef DEBUG
936 printf("invalidating TB (%08X) at %08X\n", tb, eip);
937# endif
938 tb_invalidate(tb);
939 //Note: this will leak TBs, but the whole cache will be flushed
940 // when it happens too often
941 tb->pc = 0;
942 tb->cs_base = 0;
943 tb->flags = 0;
944 }
945# endif
946}
947
948# ifdef VBOX_STRICT
949/**
950 * Gets the page offset.
951 */
952unsigned long get_phys_page_offset(target_ulong addr)
953{
954 PhysPageDesc *p = phys_page_find(addr >> TARGET_PAGE_BITS);
955 return p ? p->phys_offset : 0;
956}
957# endif /* VBOX_STRICT */
958#endif /* VBOX */
959
960#ifndef VBOX
961static inline void set_bits(uint8_t *tab, int start, int len)
962#else
963DECLINLINE(void) set_bits(uint8_t *tab, int start, int len)
964#endif
965{
966 int end, mask, end1;
967
968 end = start + len;
969 tab += start >> 3;
970 mask = 0xff << (start & 7);
971 if ((start & ~7) == (end & ~7)) {
972 if (start < end) {
973 mask &= ~(0xff << (end & 7));
974 *tab |= mask;
975 }
976 } else {
977 *tab++ |= mask;
978 start = (start + 8) & ~7;
979 end1 = end & ~7;
980 while (start < end1) {
981 *tab++ = 0xff;
982 start += 8;
983 }
984 if (start < end) {
985 mask = ~(0xff << (end & 7));
986 *tab |= mask;
987 }
988 }
989}
990
991static void build_page_bitmap(PageDesc *p)
992{
993 int n, tb_start, tb_end;
994 TranslationBlock *tb;
995
996 p->code_bitmap = qemu_malloc(TARGET_PAGE_SIZE / 8);
997 if (!p->code_bitmap)
998 return;
999 memset(p->code_bitmap, 0, TARGET_PAGE_SIZE / 8);
1000
1001 tb = p->first_tb;
1002 while (tb != NULL) {
1003 n = (long)tb & 3;
1004 tb = (TranslationBlock *)((long)tb & ~3);
1005 /* NOTE: this is subtle as a TB may span two physical pages */
1006 if (n == 0) {
1007 /* NOTE: tb_end may be after the end of the page, but
1008 it is not a problem */
1009 tb_start = tb->pc & ~TARGET_PAGE_MASK;
1010 tb_end = tb_start + tb->size;
1011 if (tb_end > TARGET_PAGE_SIZE)
1012 tb_end = TARGET_PAGE_SIZE;
1013 } else {
1014 tb_start = 0;
1015 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
1016 }
1017 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
1018 tb = tb->page_next[n];
1019 }
1020}
1021
1022TranslationBlock *tb_gen_code(CPUState *env,
1023 target_ulong pc, target_ulong cs_base,
1024 int flags, int cflags)
1025{
1026 TranslationBlock *tb;
1027 uint8_t *tc_ptr;
1028 target_ulong phys_pc, phys_page2, virt_page2;
1029 int code_gen_size;
1030
1031 phys_pc = get_phys_addr_code(env, pc);
1032 tb = tb_alloc(pc);
1033 if (!tb) {
1034 /* flush must be done */
1035 tb_flush(env);
1036 /* cannot fail at this point */
1037 tb = tb_alloc(pc);
1038 /* Don't forget to invalidate previous TB info. */
1039 tb_invalidated_flag = 1;
1040 }
1041 tc_ptr = code_gen_ptr;
1042 tb->tc_ptr = tc_ptr;
1043 tb->cs_base = cs_base;
1044 tb->flags = flags;
1045 tb->cflags = cflags;
1046 cpu_gen_code(env, tb, &code_gen_size);
1047 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
1048
1049 /* check next page if needed */
1050 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
1051 phys_page2 = -1;
1052 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
1053 phys_page2 = get_phys_addr_code(env, virt_page2);
1054 }
1055 tb_link_phys(tb, phys_pc, phys_page2);
1056 return tb;
1057}
1058
1059/* invalidate all TBs which intersect with the target physical page
1060 starting in range [start;end[. NOTE: start and end must refer to
1061 the same physical page. 'is_cpu_write_access' should be true if called
1062 from a real cpu write access: the virtual CPU will exit the current
1063 TB if code is modified inside this TB. */
1064void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
1065 int is_cpu_write_access)
1066{
1067 int n, current_tb_modified, current_tb_not_found, current_flags;
1068 CPUState *env = cpu_single_env;
1069 PageDesc *p;
1070 TranslationBlock *tb, *tb_next, *current_tb, *saved_tb;
1071 target_ulong tb_start, tb_end;
1072 target_ulong current_pc, current_cs_base;
1073
1074 p = page_find(start >> TARGET_PAGE_BITS);
1075 if (!p)
1076 return;
1077 if (!p->code_bitmap &&
1078 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
1079 is_cpu_write_access) {
1080 /* build code bitmap */
1081 build_page_bitmap(p);
1082 }
1083
1084 /* we remove all the TBs in the range [start, end[ */
1085 /* XXX: see if in some cases it could be faster to invalidate all the code */
1086 current_tb_not_found = is_cpu_write_access;
1087 current_tb_modified = 0;
1088 current_tb = NULL; /* avoid warning */
1089 current_pc = 0; /* avoid warning */
1090 current_cs_base = 0; /* avoid warning */
1091 current_flags = 0; /* avoid warning */
1092 tb = p->first_tb;
1093 while (tb != NULL) {
1094 n = (long)tb & 3;
1095 tb = (TranslationBlock *)((long)tb & ~3);
1096 tb_next = tb->page_next[n];
1097 /* NOTE: this is subtle as a TB may span two physical pages */
1098 if (n == 0) {
1099 /* NOTE: tb_end may be after the end of the page, but
1100 it is not a problem */
1101 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
1102 tb_end = tb_start + tb->size;
1103 } else {
1104 tb_start = tb->page_addr[1];
1105 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
1106 }
1107 if (!(tb_end <= start || tb_start >= end)) {
1108#ifdef TARGET_HAS_PRECISE_SMC
1109 if (current_tb_not_found) {
1110 current_tb_not_found = 0;
1111 current_tb = NULL;
1112 if (env->mem_io_pc) {
1113 /* now we have a real cpu fault */
1114 current_tb = tb_find_pc(env->mem_io_pc);
1115 }
1116 }
1117 if (current_tb == tb &&
1118 (current_tb->cflags & CF_COUNT_MASK) != 1) {
1119 /* If we are modifying the current TB, we must stop
1120 its execution. We could be more precise by checking
1121 that the modification is after the current PC, but it
1122 would require a specialized function to partially
1123 restore the CPU state */
1124
1125 current_tb_modified = 1;
1126 cpu_restore_state(current_tb, env,
1127 env->mem_io_pc, NULL);
1128#if defined(TARGET_I386)
1129 current_flags = env->hflags;
1130 current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
1131 current_cs_base = (target_ulong)env->segs[R_CS].base;
1132 current_pc = current_cs_base + env->eip;
1133#else
1134#error unsupported CPU
1135#endif
1136 }
1137#endif /* TARGET_HAS_PRECISE_SMC */
1138 /* we need to do that to handle the case where a signal
1139 occurs while doing tb_phys_invalidate() */
1140 saved_tb = NULL;
1141 if (env) {
1142 saved_tb = env->current_tb;
1143 env->current_tb = NULL;
1144 }
1145 tb_phys_invalidate(tb, -1);
1146 if (env) {
1147 env->current_tb = saved_tb;
1148 if (env->interrupt_request && env->current_tb)
1149 cpu_interrupt(env, env->interrupt_request);
1150 }
1151 }
1152 tb = tb_next;
1153 }
1154#if !defined(CONFIG_USER_ONLY)
1155 /* if no code remaining, no need to continue to use slow writes */
1156 if (!p->first_tb) {
1157 invalidate_page_bitmap(p);
1158 if (is_cpu_write_access) {
1159 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
1160 }
1161 }
1162#endif
1163#ifdef TARGET_HAS_PRECISE_SMC
1164 if (current_tb_modified) {
1165 /* we generate a block containing just the instruction
1166 modifying the memory. It will ensure that it cannot modify
1167 itself */
1168 env->current_tb = NULL;
1169 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1170 cpu_resume_from_signal(env, NULL);
1171 }
1172#endif
1173}
1174
1175
1176/* len must be <= 8 and start must be a multiple of len */
1177#ifndef VBOX
1178static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
1179#else
1180DECLINLINE(void) tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
1181#endif
1182{
1183 PageDesc *p;
1184 int offset, b;
1185#if 0
1186 if (1) {
1187 if (loglevel) {
1188 fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1189 cpu_single_env->mem_io_vaddr, len,
1190 cpu_single_env->eip,
1191 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1192 }
1193 }
1194#endif
1195 p = page_find(start >> TARGET_PAGE_BITS);
1196 if (!p)
1197 return;
1198 if (p->code_bitmap) {
1199 offset = start & ~TARGET_PAGE_MASK;
1200 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1201 if (b & ((1 << len) - 1))
1202 goto do_invalidate;
1203 } else {
1204 do_invalidate:
1205 tb_invalidate_phys_page_range(start, start + len, 1);
1206 }
1207}
1208
1209
1210#if !defined(CONFIG_SOFTMMU)
1211static void tb_invalidate_phys_page(target_phys_addr_t addr,
1212 unsigned long pc, void *puc)
1213{
1214 int n, current_flags, current_tb_modified;
1215 target_ulong current_pc, current_cs_base;
1216 PageDesc *p;
1217 TranslationBlock *tb, *current_tb;
1218#ifdef TARGET_HAS_PRECISE_SMC
1219 CPUState *env = cpu_single_env;
1220#endif
1221
1222 addr &= TARGET_PAGE_MASK;
1223 p = page_find(addr >> TARGET_PAGE_BITS);
1224 if (!p)
1225 return;
1226 tb = p->first_tb;
1227 current_tb_modified = 0;
1228 current_tb = NULL;
1229 current_pc = 0; /* avoid warning */
1230 current_cs_base = 0; /* avoid warning */
1231 current_flags = 0; /* avoid warning */
1232#ifdef TARGET_HAS_PRECISE_SMC
1233 if (tb && pc != 0) {
1234 current_tb = tb_find_pc(pc);
1235 }
1236#endif
1237 while (tb != NULL) {
1238 n = (long)tb & 3;
1239 tb = (TranslationBlock *)((long)tb & ~3);
1240#ifdef TARGET_HAS_PRECISE_SMC
1241 if (current_tb == tb &&
1242 (current_tb->cflags & CF_COUNT_MASK) != 1) {
1243 /* If we are modifying the current TB, we must stop
1244 its execution. We could be more precise by checking
1245 that the modification is after the current PC, but it
1246 would require a specialized function to partially
1247 restore the CPU state */
1248
1249 current_tb_modified = 1;
1250 cpu_restore_state(current_tb, env, pc, puc);
1251#if defined(TARGET_I386)
1252 current_flags = env->hflags;
1253 current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
1254 current_cs_base = (target_ulong)env->segs[R_CS].base;
1255 current_pc = current_cs_base + env->eip;
1256#else
1257#error unsupported CPU
1258#endif
1259 }
1260#endif /* TARGET_HAS_PRECISE_SMC */
1261 tb_phys_invalidate(tb, addr);
1262 tb = tb->page_next[n];
1263 }
1264 p->first_tb = NULL;
1265#ifdef TARGET_HAS_PRECISE_SMC
1266 if (current_tb_modified) {
1267 /* we generate a block containing just the instruction
1268 modifying the memory. It will ensure that it cannot modify
1269 itself */
1270 env->current_tb = NULL;
1271 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1272 cpu_resume_from_signal(env, puc);
1273 }
1274#endif
1275}
1276#endif
1277
1278/* add the tb in the target page and protect it if necessary */
1279#ifndef VBOX
1280static inline void tb_alloc_page(TranslationBlock *tb,
1281 unsigned int n, target_ulong page_addr)
1282#else
1283DECLINLINE(void) tb_alloc_page(TranslationBlock *tb,
1284 unsigned int n, target_ulong page_addr)
1285#endif
1286{
1287 PageDesc *p;
1288 TranslationBlock *last_first_tb;
1289
1290 tb->page_addr[n] = page_addr;
1291 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
1292 tb->page_next[n] = p->first_tb;
1293 last_first_tb = p->first_tb;
1294 p->first_tb = (TranslationBlock *)((long)tb | n);
1295 invalidate_page_bitmap(p);
1296
1297#if defined(TARGET_HAS_SMC) || 1
1298
1299#if defined(CONFIG_USER_ONLY)
1300 if (p->flags & PAGE_WRITE) {
1301 target_ulong addr;
1302 PageDesc *p2;
1303 int prot;
1304
1305 /* force the host page as non writable (writes will have a
1306 page fault + mprotect overhead) */
1307 page_addr &= qemu_host_page_mask;
1308 prot = 0;
1309 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1310 addr += TARGET_PAGE_SIZE) {
1311
1312 p2 = page_find (addr >> TARGET_PAGE_BITS);
1313 if (!p2)
1314 continue;
1315 prot |= p2->flags;
1316 p2->flags &= ~PAGE_WRITE;
1317 page_get_flags(addr);
1318 }
1319 mprotect(g2h(page_addr), qemu_host_page_size,
1320 (prot & PAGE_BITS) & ~PAGE_WRITE);
1321#ifdef DEBUG_TB_INVALIDATE
1322 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
1323 page_addr);
1324#endif
1325 }
1326#else
1327 /* if some code is already present, then the pages are already
1328 protected. So we handle the case where only the first TB is
1329 allocated in a physical page */
1330 if (!last_first_tb) {
1331 tlb_protect_code(page_addr);
1332 }
1333#endif
1334
1335#endif /* TARGET_HAS_SMC */
1336}
1337
1338/* Allocate a new translation block. Flush the translation buffer if
1339 too many translation blocks or too much generated code. */
1340TranslationBlock *tb_alloc(target_ulong pc)
1341{
1342 TranslationBlock *tb;
1343
1344 if (nb_tbs >= code_gen_max_blocks ||
1345#ifndef VBOX
1346 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
1347#else
1348 (code_gen_ptr - code_gen_buffer) >= (int)code_gen_buffer_max_size)
1349#endif
1350 return NULL;
1351 tb = &tbs[nb_tbs++];
1352 tb->pc = pc;
1353 tb->cflags = 0;
1354 return tb;
1355}
1356
1357void tb_free(TranslationBlock *tb)
1358{
1359 /* In practice this is mostly used for single use temporary TB
1360 Ignore the hard cases and just back up if this TB happens to
1361 be the last one generated. */
1362 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1363 code_gen_ptr = tb->tc_ptr;
1364 nb_tbs--;
1365 }
1366}
1367
1368/* add a new TB and link it to the physical page tables. phys_page2 is
1369 (-1) to indicate that only one page contains the TB. */
1370void tb_link_phys(TranslationBlock *tb,
1371 target_ulong phys_pc, target_ulong phys_page2)
1372{
1373 unsigned int h;
1374 TranslationBlock **ptb;
1375
1376 /* Grab the mmap lock to stop another thread invalidating this TB
1377 before we are done. */
1378 mmap_lock();
1379 /* add in the physical hash table */
1380 h = tb_phys_hash_func(phys_pc);
1381 ptb = &tb_phys_hash[h];
1382 tb->phys_hash_next = *ptb;
1383 *ptb = tb;
1384
1385 /* add in the page list */
1386 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1387 if (phys_page2 != -1)
1388 tb_alloc_page(tb, 1, phys_page2);
1389 else
1390 tb->page_addr[1] = -1;
1391
1392 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1393 tb->jmp_next[0] = NULL;
1394 tb->jmp_next[1] = NULL;
1395
1396 /* init original jump addresses */
1397 if (tb->tb_next_offset[0] != 0xffff)
1398 tb_reset_jump(tb, 0);
1399 if (tb->tb_next_offset[1] != 0xffff)
1400 tb_reset_jump(tb, 1);
1401
1402#ifdef DEBUG_TB_CHECK
1403 tb_page_check();
1404#endif
1405 mmap_unlock();
1406}
1407
1408/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1409 tb[1].tc_ptr. Return NULL if not found */
1410TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1411{
1412 int m_min, m_max, m;
1413 unsigned long v;
1414 TranslationBlock *tb;
1415
1416 if (nb_tbs <= 0)
1417 return NULL;
1418 if (tc_ptr < (unsigned long)code_gen_buffer ||
1419 tc_ptr >= (unsigned long)code_gen_ptr)
1420 return NULL;
1421 /* binary search (cf Knuth) */
1422 m_min = 0;
1423 m_max = nb_tbs - 1;
1424 while (m_min <= m_max) {
1425 m = (m_min + m_max) >> 1;
1426 tb = &tbs[m];
1427 v = (unsigned long)tb->tc_ptr;
1428 if (v == tc_ptr)
1429 return tb;
1430 else if (tc_ptr < v) {
1431 m_max = m - 1;
1432 } else {
1433 m_min = m + 1;
1434 }
1435 }
1436 return &tbs[m_max];
1437}
1438
1439static void tb_reset_jump_recursive(TranslationBlock *tb);
1440
1441#ifndef VBOX
1442static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1443#else
1444DECLINLINE(void) tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1445#endif
1446{
1447 TranslationBlock *tb1, *tb_next, **ptb;
1448 unsigned int n1;
1449
1450 tb1 = tb->jmp_next[n];
1451 if (tb1 != NULL) {
1452 /* find head of list */
1453 for(;;) {
1454 n1 = (long)tb1 & 3;
1455 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1456 if (n1 == 2)
1457 break;
1458 tb1 = tb1->jmp_next[n1];
1459 }
1460 /* we are now sure now that tb jumps to tb1 */
1461 tb_next = tb1;
1462
1463 /* remove tb from the jmp_first list */
1464 ptb = &tb_next->jmp_first;
1465 for(;;) {
1466 tb1 = *ptb;
1467 n1 = (long)tb1 & 3;
1468 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1469 if (n1 == n && tb1 == tb)
1470 break;
1471 ptb = &tb1->jmp_next[n1];
1472 }
1473 *ptb = tb->jmp_next[n];
1474 tb->jmp_next[n] = NULL;
1475
1476 /* suppress the jump to next tb in generated code */
1477 tb_reset_jump(tb, n);
1478
1479 /* suppress jumps in the tb on which we could have jumped */
1480 tb_reset_jump_recursive(tb_next);
1481 }
1482}
1483
1484static void tb_reset_jump_recursive(TranslationBlock *tb)
1485{
1486 tb_reset_jump_recursive2(tb, 0);
1487 tb_reset_jump_recursive2(tb, 1);
1488}
1489
1490#if defined(TARGET_HAS_ICE)
1491static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1492{
1493 target_ulong addr, pd;
1494 ram_addr_t ram_addr;
1495 PhysPageDesc *p;
1496
1497 addr = cpu_get_phys_page_debug(env, pc);
1498 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1499 if (!p) {
1500 pd = IO_MEM_UNASSIGNED;
1501 } else {
1502 pd = p->phys_offset;
1503 }
1504 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
1505 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1506}
1507#endif
1508
1509/* Add a watchpoint. */
1510int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type)
1511{
1512 int i;
1513
1514 for (i = 0; i < env->nb_watchpoints; i++) {
1515 if (addr == env->watchpoint[i].vaddr)
1516 return 0;
1517 }
1518 if (env->nb_watchpoints >= MAX_WATCHPOINTS)
1519 return -1;
1520
1521 i = env->nb_watchpoints++;
1522 env->watchpoint[i].vaddr = addr;
1523 env->watchpoint[i].type = type;
1524 tlb_flush_page(env, addr);
1525 /* FIXME: This flush is needed because of the hack to make memory ops
1526 terminate the TB. It can be removed once the proper IO trap and
1527 re-execute bits are in. */
1528 tb_flush(env);
1529 return i;
1530}
1531
1532/* Remove a watchpoint. */
1533int cpu_watchpoint_remove(CPUState *env, target_ulong addr)
1534{
1535 int i;
1536
1537 for (i = 0; i < env->nb_watchpoints; i++) {
1538 if (addr == env->watchpoint[i].vaddr) {
1539 env->nb_watchpoints--;
1540 env->watchpoint[i] = env->watchpoint[env->nb_watchpoints];
1541 tlb_flush_page(env, addr);
1542 return 0;
1543 }
1544 }
1545 return -1;
1546}
1547
1548/* Remove all watchpoints. */
1549void cpu_watchpoint_remove_all(CPUState *env) {
1550 int i;
1551
1552 for (i = 0; i < env->nb_watchpoints; i++) {
1553 tlb_flush_page(env, env->watchpoint[i].vaddr);
1554 }
1555 env->nb_watchpoints = 0;
1556}
1557
1558/* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
1559 breakpoint is reached */
1560int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
1561{
1562#if defined(TARGET_HAS_ICE)
1563 int i;
1564
1565 for(i = 0; i < env->nb_breakpoints; i++) {
1566 if (env->breakpoints[i] == pc)
1567 return 0;
1568 }
1569
1570 if (env->nb_breakpoints >= MAX_BREAKPOINTS)
1571 return -1;
1572 env->breakpoints[env->nb_breakpoints++] = pc;
1573
1574 breakpoint_invalidate(env, pc);
1575 return 0;
1576#else
1577 return -1;
1578#endif
1579}
1580
1581/* remove all breakpoints */
1582void cpu_breakpoint_remove_all(CPUState *env) {
1583#if defined(TARGET_HAS_ICE)
1584 int i;
1585 for(i = 0; i < env->nb_breakpoints; i++) {
1586 breakpoint_invalidate(env, env->breakpoints[i]);
1587 }
1588 env->nb_breakpoints = 0;
1589#endif
1590}
1591
1592/* remove a breakpoint */
1593int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
1594{
1595#if defined(TARGET_HAS_ICE)
1596 int i;
1597 for(i = 0; i < env->nb_breakpoints; i++) {
1598 if (env->breakpoints[i] == pc)
1599 goto found;
1600 }
1601 return -1;
1602 found:
1603 env->nb_breakpoints--;
1604 if (i < env->nb_breakpoints)
1605 env->breakpoints[i] = env->breakpoints[env->nb_breakpoints];
1606
1607 breakpoint_invalidate(env, pc);
1608 return 0;
1609#else
1610 return -1;
1611#endif
1612}
1613
1614/* enable or disable single step mode. EXCP_DEBUG is returned by the
1615 CPU loop after each instruction */
1616void cpu_single_step(CPUState *env, int enabled)
1617{
1618#if defined(TARGET_HAS_ICE)
1619 if (env->singlestep_enabled != enabled) {
1620 env->singlestep_enabled = enabled;
1621 /* must flush all the translated code to avoid inconsistancies */
1622 /* XXX: only flush what is necessary */
1623 tb_flush(env);
1624 }
1625#endif
1626}
1627
1628#ifndef VBOX
1629/* enable or disable low levels log */
1630void cpu_set_log(int log_flags)
1631{
1632 loglevel = log_flags;
1633 if (loglevel && !logfile) {
1634 logfile = fopen(logfilename, "w");
1635 if (!logfile) {
1636 perror(logfilename);
1637 _exit(1);
1638 }
1639#if !defined(CONFIG_SOFTMMU)
1640 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1641 {
1642 static uint8_t logfile_buf[4096];
1643 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1644 }
1645#else
1646 setvbuf(logfile, NULL, _IOLBF, 0);
1647#endif
1648 }
1649}
1650
1651void cpu_set_log_filename(const char *filename)
1652{
1653 logfilename = strdup(filename);
1654}
1655#endif /* !VBOX */
1656
1657/* mask must never be zero, except for A20 change call */
1658void cpu_interrupt(CPUState *env, int mask)
1659{
1660#if !defined(USE_NPTL)
1661 TranslationBlock *tb;
1662 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
1663#endif
1664 int old_mask;
1665
1666 old_mask = env->interrupt_request;
1667#ifdef VBOX
1668 VM_ASSERT_EMT(env->pVM);
1669 ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request, mask);
1670#else /* !VBOX */
1671 /* FIXME: This is probably not threadsafe. A different thread could
1672 be in the middle of a read-modify-write operation. */
1673 env->interrupt_request |= mask;
1674#endif /* !VBOX */
1675#if defined(USE_NPTL)
1676 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1677 problem and hope the cpu will stop of its own accord. For userspace
1678 emulation this often isn't actually as bad as it sounds. Often
1679 signals are used primarily to interrupt blocking syscalls. */
1680#else
1681 if (use_icount) {
1682 env->icount_decr.u16.high = 0xffff;
1683#ifndef CONFIG_USER_ONLY
1684 /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
1685 an async event happened and we need to process it. */
1686 if (!can_do_io(env)
1687 && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
1688 cpu_abort(env, "Raised interrupt while not in I/O function");
1689 }
1690#endif
1691 } else {
1692 tb = env->current_tb;
1693 /* if the cpu is currently executing code, we must unlink it and
1694 all the potentially executing TB */
1695 if (tb && !testandset(&interrupt_lock)) {
1696 env->current_tb = NULL;
1697 tb_reset_jump_recursive(tb);
1698 resetlock(&interrupt_lock);
1699 }
1700 }
1701#endif
1702}
1703
1704void cpu_reset_interrupt(CPUState *env, int mask)
1705{
1706#ifdef VBOX
1707 /*
1708 * Note: the current implementation can be executed by another thread without problems; make sure this remains true
1709 * for future changes!
1710 */
1711 ASMAtomicAndS32((int32_t volatile *)&env->interrupt_request, ~mask);
1712#else /* !VBOX */
1713 env->interrupt_request &= ~mask;
1714#endif /* !VBOX */
1715}
1716
1717#ifndef VBOX
1718CPULogItem cpu_log_items[] = {
1719 { CPU_LOG_TB_OUT_ASM, "out_asm",
1720 "show generated host assembly code for each compiled TB" },
1721 { CPU_LOG_TB_IN_ASM, "in_asm",
1722 "show target assembly code for each compiled TB" },
1723 { CPU_LOG_TB_OP, "op",
1724 "show micro ops for each compiled TB (only usable if 'in_asm' used)" },
1725#ifdef TARGET_I386
1726 { CPU_LOG_TB_OP_OPT, "op_opt",
1727 "show micro ops after optimization for each compiled TB" },
1728#endif
1729 { CPU_LOG_INT, "int",
1730 "show interrupts/exceptions in short format" },
1731 { CPU_LOG_EXEC, "exec",
1732 "show trace before each executed TB (lots of logs)" },
1733 { CPU_LOG_TB_CPU, "cpu",
1734 "show CPU state before bloc translation" },
1735#ifdef TARGET_I386
1736 { CPU_LOG_PCALL, "pcall",
1737 "show protected mode far calls/returns/exceptions" },
1738#endif
1739#ifdef DEBUG_IOPORT
1740 { CPU_LOG_IOPORT, "ioport",
1741 "show all i/o ports accesses" },
1742#endif
1743 { 0, NULL, NULL },
1744};
1745
1746static int cmp1(const char *s1, int n, const char *s2)
1747{
1748 if (strlen(s2) != n)
1749 return 0;
1750 return memcmp(s1, s2, n) == 0;
1751}
1752
1753/* takes a comma separated list of log masks. Return 0 if error. */
1754int cpu_str_to_log_mask(const char *str)
1755{
1756 CPULogItem *item;
1757 int mask;
1758 const char *p, *p1;
1759
1760 p = str;
1761 mask = 0;
1762 for(;;) {
1763 p1 = strchr(p, ',');
1764 if (!p1)
1765 p1 = p + strlen(p);
1766 if(cmp1(p,p1-p,"all")) {
1767 for(item = cpu_log_items; item->mask != 0; item++) {
1768 mask |= item->mask;
1769 }
1770 } else {
1771 for(item = cpu_log_items; item->mask != 0; item++) {
1772 if (cmp1(p, p1 - p, item->name))
1773 goto found;
1774 }
1775 return 0;
1776 }
1777 found:
1778 mask |= item->mask;
1779 if (*p1 != ',')
1780 break;
1781 p = p1 + 1;
1782 }
1783 return mask;
1784}
1785#endif /* !VBOX */
1786
1787#ifndef VBOX /* VBOX: we have our own routine. */
1788void cpu_abort(CPUState *env, const char *fmt, ...)
1789{
1790 va_list ap;
1791
1792 va_start(ap, fmt);
1793 fprintf(stderr, "qemu: fatal: ");
1794 vfprintf(stderr, fmt, ap);
1795 fprintf(stderr, "\n");
1796#ifdef TARGET_I386
1797 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1798#else
1799 cpu_dump_state(env, stderr, fprintf, 0);
1800#endif
1801 va_end(ap);
1802 abort();
1803}
1804#endif /* !VBOX */
1805
1806#ifndef VBOX
1807CPUState *cpu_copy(CPUState *env)
1808{
1809 CPUState *new_env = cpu_init(env->cpu_model_str);
1810 /* preserve chaining and index */
1811 CPUState *next_cpu = new_env->next_cpu;
1812 int cpu_index = new_env->cpu_index;
1813 memcpy(new_env, env, sizeof(CPUState));
1814 new_env->next_cpu = next_cpu;
1815 new_env->cpu_index = cpu_index;
1816 return new_env;
1817}
1818#endif
1819
1820#if !defined(CONFIG_USER_ONLY)
1821
1822#ifndef VBOX
1823static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1824#else
1825DECLINLINE(void) tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1826#endif
1827{
1828 unsigned int i;
1829
1830 /* Discard jump cache entries for any tb which might potentially
1831 overlap the flushed page. */
1832 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1833 memset (&env->tb_jmp_cache[i], 0,
1834 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1835
1836 i = tb_jmp_cache_hash_page(addr);
1837 memset (&env->tb_jmp_cache[i], 0,
1838 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1839
1840#ifdef VBOX
1841 /* inform raw mode about TLB page flush */
1842 remR3FlushPage(env, addr);
1843#endif /* VBOX */
1844}
1845
1846/* NOTE: if flush_global is true, also flush global entries (not
1847 implemented yet) */
1848void tlb_flush(CPUState *env, int flush_global)
1849{
1850 int i;
1851#if defined(DEBUG_TLB)
1852 printf("tlb_flush:\n");
1853#endif
1854 /* must reset current TB so that interrupts cannot modify the
1855 links while we are modifying them */
1856 env->current_tb = NULL;
1857
1858 for(i = 0; i < CPU_TLB_SIZE; i++) {
1859 env->tlb_table[0][i].addr_read = -1;
1860 env->tlb_table[0][i].addr_write = -1;
1861 env->tlb_table[0][i].addr_code = -1;
1862 env->tlb_table[1][i].addr_read = -1;
1863 env->tlb_table[1][i].addr_write = -1;
1864 env->tlb_table[1][i].addr_code = -1;
1865#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
1866 env->phys_addends[0][i] = -1;
1867 env->phys_addends[1][i] = -1;
1868#endif
1869#if (NB_MMU_MODES >= 3)
1870 env->tlb_table[2][i].addr_read = -1;
1871 env->tlb_table[2][i].addr_write = -1;
1872 env->tlb_table[2][i].addr_code = -1;
1873#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
1874 env->phys_addends[2][i] = -1;
1875#endif
1876#if (NB_MMU_MODES == 4)
1877 env->tlb_table[3][i].addr_read = -1;
1878 env->tlb_table[3][i].addr_write = -1;
1879 env->tlb_table[3][i].addr_code = -1;
1880#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
1881 env->phys_addends[3][i] = -1;
1882#endif
1883#endif
1884#endif
1885 }
1886
1887 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
1888
1889#ifdef VBOX
1890 /* inform raw mode about TLB flush */
1891 remR3FlushTLB(env, flush_global);
1892#endif
1893#ifdef USE_KQEMU
1894 if (env->kqemu_enabled) {
1895 kqemu_flush(env, flush_global);
1896 }
1897#endif
1898 tlb_flush_count++;
1899}
1900
1901#ifndef VBOX
1902static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1903#else
1904DECLINLINE(void) tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1905#endif
1906{
1907 if (addr == (tlb_entry->addr_read &
1908 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1909 addr == (tlb_entry->addr_write &
1910 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1911 addr == (tlb_entry->addr_code &
1912 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1913 tlb_entry->addr_read = -1;
1914 tlb_entry->addr_write = -1;
1915 tlb_entry->addr_code = -1;
1916 }
1917}
1918
1919void tlb_flush_page(CPUState *env, target_ulong addr)
1920{
1921 int i;
1922
1923#if defined(DEBUG_TLB)
1924 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
1925#endif
1926 /* must reset current TB so that interrupts cannot modify the
1927 links while we are modifying them */
1928 env->current_tb = NULL;
1929
1930 addr &= TARGET_PAGE_MASK;
1931 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1932 tlb_flush_entry(&env->tlb_table[0][i], addr);
1933 tlb_flush_entry(&env->tlb_table[1][i], addr);
1934#if (NB_MMU_MODES >= 3)
1935 tlb_flush_entry(&env->tlb_table[2][i], addr);
1936#if (NB_MMU_MODES == 4)
1937 tlb_flush_entry(&env->tlb_table[3][i], addr);
1938#endif
1939#endif
1940
1941 tlb_flush_jmp_cache(env, addr);
1942
1943#ifdef USE_KQEMU
1944 if (env->kqemu_enabled) {
1945 kqemu_flush_page(env, addr);
1946 }
1947#endif
1948}
1949
1950/* update the TLBs so that writes to code in the virtual page 'addr'
1951 can be detected */
1952static void tlb_protect_code(ram_addr_t ram_addr)
1953{
1954 cpu_physical_memory_reset_dirty(ram_addr,
1955 ram_addr + TARGET_PAGE_SIZE,
1956 CODE_DIRTY_FLAG);
1957#if defined(VBOX) && defined(REM_MONITOR_CODE_PAGES)
1958 /** @todo Retest this? This function has changed... */
1959 remR3ProtectCode(cpu_single_env, ram_addr);
1960#endif
1961}
1962
1963/* update the TLB so that writes in physical page 'phys_addr' are no longer
1964 tested for self modifying code */
1965static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
1966 target_ulong vaddr)
1967{
1968#ifdef VBOX
1969 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
1970#endif
1971 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
1972}
1973
1974#ifndef VBOX
1975static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1976 unsigned long start, unsigned long length)
1977#else
1978DECLINLINE(void) tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1979 unsigned long start, unsigned long length)
1980#endif
1981{
1982 unsigned long addr;
1983
1984#ifdef VBOX
1985 if (start & 3)
1986 return;
1987#endif
1988 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1989 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1990 if ((addr - start) < length) {
1991 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_NOTDIRTY;
1992 }
1993 }
1994}
1995
1996void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1997 int dirty_flags)
1998{
1999 CPUState *env;
2000 unsigned long length, start1;
2001 int i, mask, len;
2002 uint8_t *p;
2003
2004 start &= TARGET_PAGE_MASK;
2005 end = TARGET_PAGE_ALIGN(end);
2006
2007 length = end - start;
2008 if (length == 0)
2009 return;
2010 len = length >> TARGET_PAGE_BITS;
2011#ifdef USE_KQEMU
2012 /* XXX: should not depend on cpu context */
2013 env = first_cpu;
2014 if (env->kqemu_enabled) {
2015 ram_addr_t addr;
2016 addr = start;
2017 for(i = 0; i < len; i++) {
2018 kqemu_set_notdirty(env, addr);
2019 addr += TARGET_PAGE_SIZE;
2020 }
2021 }
2022#endif
2023 mask = ~dirty_flags;
2024 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
2025#ifdef VBOX
2026 if (RT_LIKELY((start >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2027#endif
2028 for(i = 0; i < len; i++)
2029 p[i] &= mask;
2030
2031 /* we modify the TLB cache so that the dirty bit will be set again
2032 when accessing the range */
2033#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
2034 start1 = start;
2035#elif !defined(VBOX)
2036 start1 = start + (unsigned long)phys_ram_base;
2037#else
2038 start1 = (unsigned long)remR3TlbGCPhys2Ptr(first_cpu, start, 1 /*fWritable*/); /** @todo this can be harmful with VBOX_WITH_NEW_PHYS_CODE, fix interface/whatever. */
2039#endif
2040 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2041 for(i = 0; i < CPU_TLB_SIZE; i++)
2042 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
2043 for(i = 0; i < CPU_TLB_SIZE; i++)
2044 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
2045#if (NB_MMU_MODES >= 3)
2046 for(i = 0; i < CPU_TLB_SIZE; i++)
2047 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
2048#if (NB_MMU_MODES == 4)
2049 for(i = 0; i < CPU_TLB_SIZE; i++)
2050 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
2051#endif
2052#endif
2053 }
2054}
2055
2056#ifndef VBOX
2057int cpu_physical_memory_set_dirty_tracking(int enable)
2058{
2059 in_migration = enable;
2060 return 0;
2061}
2062
2063int cpu_physical_memory_get_dirty_tracking(void)
2064{
2065 return in_migration;
2066}
2067#endif
2068
2069#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2070DECLINLINE(void) tlb_update_dirty(CPUTLBEntry *tlb_entry, target_phys_addr_t phys_addend)
2071#else
2072static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
2073#endif
2074{
2075 ram_addr_t ram_addr;
2076
2077 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
2078 /* RAM case */
2079#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
2080 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
2081#elif !defined(VBOX)
2082 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
2083 tlb_entry->addend - (unsigned long)phys_ram_base;
2084#else
2085 Assert(phys_addend != -1);
2086 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + phys_addend;
2087#endif
2088 if (!cpu_physical_memory_is_dirty(ram_addr)) {
2089 tlb_entry->addr_write |= TLB_NOTDIRTY;
2090 }
2091 }
2092}
2093
2094/* update the TLB according to the current state of the dirty bits */
2095void cpu_tlb_update_dirty(CPUState *env)
2096{
2097 int i;
2098#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2099 for(i = 0; i < CPU_TLB_SIZE; i++)
2100 tlb_update_dirty(&env->tlb_table[0][i], env->phys_addends[0][i]);
2101 for(i = 0; i < CPU_TLB_SIZE; i++)
2102 tlb_update_dirty(&env->tlb_table[1][i], env->phys_addends[1][i]);
2103#if (NB_MMU_MODES >= 3)
2104 for(i = 0; i < CPU_TLB_SIZE; i++)
2105 tlb_update_dirty(&env->tlb_table[2][i], env->phys_addends[2][i]);
2106#if (NB_MMU_MODES == 4)
2107 for(i = 0; i < CPU_TLB_SIZE; i++)
2108 tlb_update_dirty(&env->tlb_table[3][i], env->phys_addends[3][i]);
2109#endif
2110#endif
2111#else /* VBOX */
2112 for(i = 0; i < CPU_TLB_SIZE; i++)
2113 tlb_update_dirty(&env->tlb_table[0][i]);
2114 for(i = 0; i < CPU_TLB_SIZE; i++)
2115 tlb_update_dirty(&env->tlb_table[1][i]);
2116#if (NB_MMU_MODES >= 3)
2117 for(i = 0; i < CPU_TLB_SIZE; i++)
2118 tlb_update_dirty(&env->tlb_table[2][i]);
2119#if (NB_MMU_MODES == 4)
2120 for(i = 0; i < CPU_TLB_SIZE; i++)
2121 tlb_update_dirty(&env->tlb_table[3][i]);
2122#endif
2123#endif
2124#endif /* VBOX */
2125}
2126
2127#ifndef VBOX
2128static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
2129#else
2130DECLINLINE(void) tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
2131#endif
2132{
2133 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
2134 tlb_entry->addr_write = vaddr;
2135}
2136
2137
2138/* update the TLB corresponding to virtual page vaddr and phys addr
2139 addr so that it is no longer dirty */
2140#ifndef VBOX
2141static inline void tlb_set_dirty(CPUState *env,
2142 unsigned long addr, target_ulong vaddr)
2143#else
2144DECLINLINE(void) tlb_set_dirty(CPUState *env,
2145 unsigned long addr, target_ulong vaddr)
2146#endif
2147{
2148 int i;
2149
2150 addr &= TARGET_PAGE_MASK;
2151 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2152 tlb_set_dirty1(&env->tlb_table[0][i], addr);
2153 tlb_set_dirty1(&env->tlb_table[1][i], addr);
2154#if (NB_MMU_MODES >= 3)
2155 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
2156#if (NB_MMU_MODES == 4)
2157 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
2158#endif
2159#endif
2160}
2161
2162/* add a new TLB entry. At most one entry for a given virtual address
2163 is permitted. Return 0 if OK or 2 if the page could not be mapped
2164 (can only happen in non SOFTMMU mode for I/O pages or pages
2165 conflicting with the host address space). */
2166int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2167 target_phys_addr_t paddr, int prot,
2168 int mmu_idx, int is_softmmu)
2169{
2170 PhysPageDesc *p;
2171 unsigned long pd;
2172 unsigned int index;
2173 target_ulong address;
2174 target_ulong code_address;
2175 target_phys_addr_t addend;
2176 int ret;
2177 CPUTLBEntry *te;
2178 int i;
2179 target_phys_addr_t iotlb;
2180#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2181 int read_mods = 0, write_mods = 0, code_mods = 0;
2182#endif
2183
2184 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
2185 if (!p) {
2186 pd = IO_MEM_UNASSIGNED;
2187 } else {
2188 pd = p->phys_offset;
2189 }
2190#if defined(DEBUG_TLB)
2191 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
2192 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
2193#endif
2194
2195 ret = 0;
2196 address = vaddr;
2197 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
2198 /* IO memory case (romd handled later) */
2199 address |= TLB_MMIO;
2200 }
2201#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
2202 addend = pd & TARGET_PAGE_MASK;
2203#elif !defined(VBOX)
2204 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
2205#else
2206 /** @todo this is racing the phys_page_find call above since it may register
2207 * a new chunk of memory... */
2208 addend = (unsigned long)remR3TlbGCPhys2Ptr(env,
2209 pd & TARGET_PAGE_MASK,
2210 !!(prot & PAGE_WRITE));
2211#endif
2212
2213 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
2214 /* Normal RAM. */
2215 iotlb = pd & TARGET_PAGE_MASK;
2216 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
2217 iotlb |= IO_MEM_NOTDIRTY;
2218 else
2219 iotlb |= IO_MEM_ROM;
2220 } else {
2221 /* IO handlers are currently passed a phsical address.
2222 It would be nice to pass an offset from the base address
2223 of that region. This would avoid having to special case RAM,
2224 and avoid full address decoding in every device.
2225 We can't use the high bits of pd for this because
2226 IO_MEM_ROMD uses these as a ram address. */
2227 iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
2228 }
2229
2230 code_address = address;
2231
2232#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2233 if (addend & 0x3)
2234 {
2235 if (addend & 0x2)
2236 {
2237 /* catch write */
2238 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
2239 write_mods |= TLB_MMIO;
2240 }
2241 else if (addend & 0x1)
2242 {
2243 /* catch all */
2244 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
2245 {
2246 read_mods |= TLB_MMIO;
2247 write_mods |= TLB_MMIO;
2248 code_mods |= TLB_MMIO;
2249 }
2250 }
2251 if ((iotlb & ~TARGET_PAGE_MASK) == 0)
2252 iotlb = env->pVM->rem.s.iHandlerMemType + paddr;
2253 addend &= ~(target_ulong)0x3;
2254 }
2255#endif
2256
2257 /* Make accesses to pages with watchpoints go via the
2258 watchpoint trap routines. */
2259 for (i = 0; i < env->nb_watchpoints; i++) {
2260 if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) {
2261 iotlb = io_mem_watch + paddr;
2262 /* TODO: The memory case can be optimized by not trapping
2263 reads of pages with a write breakpoint. */
2264 address |= TLB_MMIO;
2265 }
2266 }
2267
2268 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2269 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2270 te = &env->tlb_table[mmu_idx][index];
2271 te->addend = addend - vaddr;
2272 if (prot & PAGE_READ) {
2273 te->addr_read = address;
2274 } else {
2275 te->addr_read = -1;
2276 }
2277
2278 if (prot & PAGE_EXEC) {
2279 te->addr_code = code_address;
2280 } else {
2281 te->addr_code = -1;
2282 }
2283 if (prot & PAGE_WRITE) {
2284 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2285 (pd & IO_MEM_ROMD)) {
2286 /* Write access calls the I/O callback. */
2287 te->addr_write = address | TLB_MMIO;
2288 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2289 !cpu_physical_memory_is_dirty(pd)) {
2290 te->addr_write = address | TLB_NOTDIRTY;
2291 } else {
2292 te->addr_write = address;
2293 }
2294 } else {
2295 te->addr_write = -1;
2296 }
2297
2298#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2299 if (prot & PAGE_READ)
2300 te->addr_read |= read_mods;
2301 if (prot & PAGE_EXEC)
2302 te->addr_code |= code_mods;
2303 if (prot & PAGE_WRITE)
2304 te->addr_write |= write_mods;
2305
2306 env->phys_addends[mmu_idx][index] = (pd & TARGET_PAGE_MASK)- vaddr;
2307#endif
2308
2309#ifdef VBOX
2310 /* inform raw mode about TLB page change */
2311 remR3FlushPage(env, vaddr);
2312#endif
2313 return ret;
2314}
2315#if 0
2316/* called from signal handler: invalidate the code and unprotect the
2317 page. Return TRUE if the fault was succesfully handled. */
2318int page_unprotect(target_ulong addr, unsigned long pc, void *puc)
2319{
2320#if !defined(CONFIG_SOFTMMU)
2321 VirtPageDesc *vp;
2322
2323#if defined(DEBUG_TLB)
2324 printf("page_unprotect: addr=0x%08x\n", addr);
2325#endif
2326 addr &= TARGET_PAGE_MASK;
2327
2328 /* if it is not mapped, no need to worry here */
2329 if (addr >= MMAP_AREA_END)
2330 return 0;
2331 vp = virt_page_find(addr >> TARGET_PAGE_BITS);
2332 if (!vp)
2333 return 0;
2334 /* NOTE: in this case, validate_tag is _not_ tested as it
2335 validates only the code TLB */
2336 if (vp->valid_tag != virt_valid_tag)
2337 return 0;
2338 if (!(vp->prot & PAGE_WRITE))
2339 return 0;
2340#if defined(DEBUG_TLB)
2341 printf("page_unprotect: addr=0x%08x phys_addr=0x%08x prot=%x\n",
2342 addr, vp->phys_addr, vp->prot);
2343#endif
2344 if (mprotect((void *)addr, TARGET_PAGE_SIZE, vp->prot) < 0)
2345 cpu_abort(cpu_single_env, "error mprotect addr=0x%lx prot=%d\n",
2346 (unsigned long)addr, vp->prot);
2347 /* set the dirty bit */
2348 phys_ram_dirty[vp->phys_addr >> TARGET_PAGE_BITS] = 0xff;
2349 /* flush the code inside */
2350 tb_invalidate_phys_page(vp->phys_addr, pc, puc);
2351 return 1;
2352#elif defined(VBOX)
2353 addr &= TARGET_PAGE_MASK;
2354
2355 /* if it is not mapped, no need to worry here */
2356 if (addr >= MMAP_AREA_END)
2357 return 0;
2358 return 1;
2359#else
2360 return 0;
2361#endif
2362}
2363#endif /* 0 */
2364
2365#else
2366
2367void tlb_flush(CPUState *env, int flush_global)
2368{
2369}
2370
2371void tlb_flush_page(CPUState *env, target_ulong addr)
2372{
2373}
2374
2375int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2376 target_phys_addr_t paddr, int prot,
2377 int mmu_idx, int is_softmmu)
2378{
2379 return 0;
2380}
2381
2382#ifndef VBOX
2383/* dump memory mappings */
2384void page_dump(FILE *f)
2385{
2386 unsigned long start, end;
2387 int i, j, prot, prot1;
2388 PageDesc *p;
2389
2390 fprintf(f, "%-8s %-8s %-8s %s\n",
2391 "start", "end", "size", "prot");
2392 start = -1;
2393 end = -1;
2394 prot = 0;
2395 for(i = 0; i <= L1_SIZE; i++) {
2396 if (i < L1_SIZE)
2397 p = l1_map[i];
2398 else
2399 p = NULL;
2400 for(j = 0;j < L2_SIZE; j++) {
2401 if (!p)
2402 prot1 = 0;
2403 else
2404 prot1 = p[j].flags;
2405 if (prot1 != prot) {
2406 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2407 if (start != -1) {
2408 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
2409 start, end, end - start,
2410 prot & PAGE_READ ? 'r' : '-',
2411 prot & PAGE_WRITE ? 'w' : '-',
2412 prot & PAGE_EXEC ? 'x' : '-');
2413 }
2414 if (prot1 != 0)
2415 start = end;
2416 else
2417 start = -1;
2418 prot = prot1;
2419 }
2420 if (!p)
2421 break;
2422 }
2423 }
2424}
2425#endif /* !VBOX */
2426
2427int page_get_flags(target_ulong address)
2428{
2429 PageDesc *p;
2430
2431 p = page_find(address >> TARGET_PAGE_BITS);
2432 if (!p)
2433 return 0;
2434 return p->flags;
2435}
2436
2437/* modify the flags of a page and invalidate the code if
2438 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2439 depending on PAGE_WRITE */
2440void page_set_flags(target_ulong start, target_ulong end, int flags)
2441{
2442 PageDesc *p;
2443 target_ulong addr;
2444
2445 start = start & TARGET_PAGE_MASK;
2446 end = TARGET_PAGE_ALIGN(end);
2447 if (flags & PAGE_WRITE)
2448 flags |= PAGE_WRITE_ORG;
2449#ifdef VBOX
2450 AssertMsgFailed(("We shouldn't be here, and if we should, we must have an env to do the proper locking!\n"));
2451#endif
2452 spin_lock(&tb_lock);
2453 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2454 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
2455 /* if the write protection is set, then we invalidate the code
2456 inside */
2457 if (!(p->flags & PAGE_WRITE) &&
2458 (flags & PAGE_WRITE) &&
2459 p->first_tb) {
2460 tb_invalidate_phys_page(addr, 0, NULL);
2461 }
2462 p->flags = flags;
2463 }
2464 spin_unlock(&tb_lock);
2465}
2466
2467int page_check_range(target_ulong start, target_ulong len, int flags)
2468{
2469 PageDesc *p;
2470 target_ulong end;
2471 target_ulong addr;
2472
2473 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2474 start = start & TARGET_PAGE_MASK;
2475
2476 if( end < start )
2477 /* we've wrapped around */
2478 return -1;
2479 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2480 p = page_find(addr >> TARGET_PAGE_BITS);
2481 if( !p )
2482 return -1;
2483 if( !(p->flags & PAGE_VALID) )
2484 return -1;
2485
2486 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
2487 return -1;
2488 if (flags & PAGE_WRITE) {
2489 if (!(p->flags & PAGE_WRITE_ORG))
2490 return -1;
2491 /* unprotect the page if it was put read-only because it
2492 contains translated code */
2493 if (!(p->flags & PAGE_WRITE)) {
2494 if (!page_unprotect(addr, 0, NULL))
2495 return -1;
2496 }
2497 return 0;
2498 }
2499 }
2500 return 0;
2501}
2502
2503/* called from signal handler: invalidate the code and unprotect the
2504 page. Return TRUE if the fault was succesfully handled. */
2505int page_unprotect(target_ulong address, unsigned long pc, void *puc)
2506{
2507 unsigned int page_index, prot, pindex;
2508 PageDesc *p, *p1;
2509 target_ulong host_start, host_end, addr;
2510
2511 /* Technically this isn't safe inside a signal handler. However we
2512 know this only ever happens in a synchronous SEGV handler, so in
2513 practice it seems to be ok. */
2514 mmap_lock();
2515
2516 host_start = address & qemu_host_page_mask;
2517 page_index = host_start >> TARGET_PAGE_BITS;
2518 p1 = page_find(page_index);
2519 if (!p1) {
2520 mmap_unlock();
2521 return 0;
2522 }
2523 host_end = host_start + qemu_host_page_size;
2524 p = p1;
2525 prot = 0;
2526 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2527 prot |= p->flags;
2528 p++;
2529 }
2530 /* if the page was really writable, then we change its
2531 protection back to writable */
2532 if (prot & PAGE_WRITE_ORG) {
2533 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2534 if (!(p1[pindex].flags & PAGE_WRITE)) {
2535 mprotect((void *)g2h(host_start), qemu_host_page_size,
2536 (prot & PAGE_BITS) | PAGE_WRITE);
2537 p1[pindex].flags |= PAGE_WRITE;
2538 /* and since the content will be modified, we must invalidate
2539 the corresponding translated code. */
2540 tb_invalidate_phys_page(address, pc, puc);
2541#ifdef DEBUG_TB_CHECK
2542 tb_invalidate_check(address);
2543#endif
2544 mmap_unlock();
2545 return 1;
2546 }
2547 }
2548 mmap_unlock();
2549 return 0;
2550}
2551
2552static inline void tlb_set_dirty(CPUState *env,
2553 unsigned long addr, target_ulong vaddr)
2554{
2555}
2556#endif /* defined(CONFIG_USER_ONLY) */
2557
2558#if !defined(CONFIG_USER_ONLY)
2559static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2560 ram_addr_t memory);
2561static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2562 ram_addr_t orig_memory);
2563#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2564 need_subpage) \
2565 do { \
2566 if (addr > start_addr) \
2567 start_addr2 = 0; \
2568 else { \
2569 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2570 if (start_addr2 > 0) \
2571 need_subpage = 1; \
2572 } \
2573 \
2574 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
2575 end_addr2 = TARGET_PAGE_SIZE - 1; \
2576 else { \
2577 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2578 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2579 need_subpage = 1; \
2580 } \
2581 } while (0)
2582
2583
2584/* register physical memory. 'size' must be a multiple of the target
2585 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2586 io memory page */
2587void cpu_register_physical_memory(target_phys_addr_t start_addr,
2588 unsigned long size,
2589 unsigned long phys_offset)
2590{
2591 target_phys_addr_t addr, end_addr;
2592 PhysPageDesc *p;
2593 CPUState *env;
2594 ram_addr_t orig_size = size;
2595 void *subpage;
2596
2597#ifdef USE_KQEMU
2598 /* XXX: should not depend on cpu context */
2599 env = first_cpu;
2600 if (env->kqemu_enabled) {
2601 kqemu_set_phys_mem(start_addr, size, phys_offset);
2602 }
2603#endif
2604 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2605 end_addr = start_addr + (target_phys_addr_t)size;
2606 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
2607 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2608 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
2609 ram_addr_t orig_memory = p->phys_offset;
2610 target_phys_addr_t start_addr2, end_addr2;
2611 int need_subpage = 0;
2612
2613 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2614 need_subpage);
2615 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
2616 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2617 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2618 &p->phys_offset, orig_memory);
2619 } else {
2620 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2621 >> IO_MEM_SHIFT];
2622 }
2623 subpage_register(subpage, start_addr2, end_addr2, phys_offset);
2624 } else {
2625 p->phys_offset = phys_offset;
2626#if !defined(VBOX) || defined(VBOX_WITH_NEW_PHYS_CODE)
2627 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2628 (phys_offset & IO_MEM_ROMD))
2629#else
2630 if ( (phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM
2631 || (phys_offset & IO_MEM_ROMD)
2632 || (phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING)
2633#endif
2634 phys_offset += TARGET_PAGE_SIZE;
2635 }
2636 } else {
2637 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2638 p->phys_offset = phys_offset;
2639#if !defined(VBOX) || defined(VBOX_WITH_NEW_PHYS_CODE)
2640 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2641 (phys_offset & IO_MEM_ROMD))
2642#else
2643 if ( (phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM
2644 || (phys_offset & IO_MEM_ROMD)
2645 || (phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING)
2646#endif
2647 phys_offset += TARGET_PAGE_SIZE;
2648 else {
2649 target_phys_addr_t start_addr2, end_addr2;
2650 int need_subpage = 0;
2651
2652 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2653 end_addr2, need_subpage);
2654
2655 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
2656 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2657 &p->phys_offset, IO_MEM_UNASSIGNED);
2658 subpage_register(subpage, start_addr2, end_addr2,
2659 phys_offset);
2660 }
2661 }
2662 }
2663 }
2664 /* since each CPU stores ram addresses in its TLB cache, we must
2665 reset the modified entries */
2666 /* XXX: slow ! */
2667 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2668 tlb_flush(env, 1);
2669 }
2670}
2671
2672/* XXX: temporary until new memory mapping API */
2673uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
2674{
2675 PhysPageDesc *p;
2676
2677 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2678 if (!p)
2679 return IO_MEM_UNASSIGNED;
2680 return p->phys_offset;
2681}
2682
2683#ifndef VBOX
2684/* XXX: better than nothing */
2685ram_addr_t qemu_ram_alloc(ram_addr_t size)
2686{
2687 ram_addr_t addr;
2688 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
2689 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
2690 (uint64_t)size, (uint64_t)phys_ram_size);
2691 abort();
2692 }
2693 addr = phys_ram_alloc_offset;
2694 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2695 return addr;
2696}
2697
2698void qemu_ram_free(ram_addr_t addr)
2699{
2700}
2701#endif
2702
2703
2704static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
2705{
2706#ifdef DEBUG_UNASSIGNED
2707 printf("Unassigned mem read 0x%08x\n", (int)addr);
2708#endif
2709#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2710 do_unassigned_access(addr, 0, 0, 0, 1);
2711#endif
2712 return 0;
2713}
2714
2715static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2716{
2717#ifdef DEBUG_UNASSIGNED
2718 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2719#endif
2720#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2721 do_unassigned_access(addr, 0, 0, 0, 2);
2722#endif
2723 return 0;
2724}
2725
2726static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2727{
2728#ifdef DEBUG_UNASSIGNED
2729 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2730#endif
2731#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2732 do_unassigned_access(addr, 0, 0, 0, 4);
2733#endif
2734 return 0;
2735}
2736
2737static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2738{
2739#ifdef DEBUG_UNASSIGNED
2740 printf("Unassigned mem write 0x%08x = 0x%x\n", (int)addr, val);
2741#endif
2742}
2743
2744static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2745{
2746#ifdef DEBUG_UNASSIGNED
2747 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2748#endif
2749#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2750 do_unassigned_access(addr, 1, 0, 0, 2);
2751#endif
2752}
2753
2754static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2755{
2756#ifdef DEBUG_UNASSIGNED
2757 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2758#endif
2759#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2760 do_unassigned_access(addr, 1, 0, 0, 4);
2761#endif
2762}
2763static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2764 unassigned_mem_readb,
2765 unassigned_mem_readw,
2766 unassigned_mem_readl,
2767};
2768
2769static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2770 unassigned_mem_writeb,
2771 unassigned_mem_writew,
2772 unassigned_mem_writel,
2773};
2774
2775static void notdirty_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2776{
2777 unsigned long ram_addr;
2778 int dirty_flags;
2779#if defined(VBOX)
2780 ram_addr = addr;
2781#elif
2782 ram_addr = addr - (unsigned long)phys_ram_base;
2783#endif
2784#ifdef VBOX
2785 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2786 dirty_flags = 0xff;
2787 else
2788#endif /* VBOX */
2789 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2790 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2791#if !defined(CONFIG_USER_ONLY)
2792 tb_invalidate_phys_page_fast(ram_addr, 1);
2793# ifdef VBOX
2794 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2795 dirty_flags = 0xff;
2796 else
2797# endif /* VBOX */
2798 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2799#endif
2800 }
2801#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2802 remR3PhysWriteU8(addr, val);
2803#else
2804 stb_p((uint8_t *)(long)addr, val);
2805#endif
2806#ifdef USE_KQEMU
2807 if (cpu_single_env->kqemu_enabled &&
2808 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2809 kqemu_modify_page(cpu_single_env, ram_addr);
2810#endif
2811 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2812#ifdef VBOX
2813 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2814#endif /* !VBOX */
2815 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2816 /* we remove the notdirty callback only if the code has been
2817 flushed */
2818 if (dirty_flags == 0xff)
2819 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_io_vaddr);
2820}
2821
2822static void notdirty_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2823{
2824 unsigned long ram_addr;
2825 int dirty_flags;
2826#if defined(VBOX)
2827 ram_addr = addr;
2828#else
2829 ram_addr = addr - (unsigned long)phys_ram_base;
2830#endif
2831#ifdef VBOX
2832 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2833 dirty_flags = 0xff;
2834 else
2835#endif /* VBOX */
2836 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2837 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2838#if !defined(CONFIG_USER_ONLY)
2839 tb_invalidate_phys_page_fast(ram_addr, 2);
2840# ifdef VBOX
2841 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2842 dirty_flags = 0xff;
2843 else
2844# endif /* VBOX */
2845 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2846#endif
2847 }
2848#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2849 remR3PhysWriteU16(addr, val);
2850#else
2851 stw_p((uint8_t *)(long)addr, val);
2852#endif
2853
2854#ifdef USE_KQEMU
2855 if (cpu_single_env->kqemu_enabled &&
2856 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2857 kqemu_modify_page(cpu_single_env, ram_addr);
2858#endif
2859 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2860#ifdef VBOX
2861 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2862#endif
2863 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2864 /* we remove the notdirty callback only if the code has been
2865 flushed */
2866 if (dirty_flags == 0xff)
2867 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_io_vaddr);
2868}
2869
2870static void notdirty_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2871{
2872 unsigned long ram_addr;
2873 int dirty_flags;
2874#if defined(VBOX)
2875 ram_addr = addr;
2876#else
2877 ram_addr = addr - (unsigned long)phys_ram_base;
2878#endif
2879#ifdef VBOX
2880 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2881 dirty_flags = 0xff;
2882 else
2883#endif /* VBOX */
2884 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2885 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2886#if !defined(CONFIG_USER_ONLY)
2887 tb_invalidate_phys_page_fast(ram_addr, 4);
2888# ifdef VBOX
2889 if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
2890 dirty_flags = 0xff;
2891 else
2892# endif /* VBOX */
2893 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2894#endif
2895 }
2896#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
2897 remR3PhysWriteU32(addr, val);
2898#else
2899 stl_p((uint8_t *)(long)addr, val);
2900#endif
2901#ifdef USE_KQEMU
2902 if (cpu_single_env->kqemu_enabled &&
2903 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2904 kqemu_modify_page(cpu_single_env, ram_addr);
2905#endif
2906 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2907#ifdef VBOX
2908 if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
2909#endif
2910 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2911 /* we remove the notdirty callback only if the code has been
2912 flushed */
2913 if (dirty_flags == 0xff)
2914 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_io_vaddr);
2915}
2916
2917static CPUReadMemoryFunc *error_mem_read[3] = {
2918 NULL, /* never used */
2919 NULL, /* never used */
2920 NULL, /* never used */
2921};
2922
2923static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2924 notdirty_mem_writeb,
2925 notdirty_mem_writew,
2926 notdirty_mem_writel,
2927};
2928
2929
2930/* Generate a debug exception if a watchpoint has been hit. */
2931static void check_watchpoint(int offset, int flags)
2932{
2933 CPUState *env = cpu_single_env;
2934 target_ulong vaddr;
2935 int i;
2936
2937 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2938 for (i = 0; i < env->nb_watchpoints; i++) {
2939 if (vaddr == env->watchpoint[i].vaddr
2940 && (env->watchpoint[i].type & flags)) {
2941 env->watchpoint_hit = i + 1;
2942 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2943 break;
2944 }
2945 }
2946}
2947
2948/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2949 so these check for a hit then pass through to the normal out-of-line
2950 phys routines. */
2951static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2952{
2953 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
2954 return ldub_phys(addr);
2955}
2956
2957static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2958{
2959 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
2960 return lduw_phys(addr);
2961}
2962
2963static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2964{
2965 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
2966 return ldl_phys(addr);
2967}
2968
2969static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2970 uint32_t val)
2971{
2972 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
2973 stb_phys(addr, val);
2974}
2975
2976static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2977 uint32_t val)
2978{
2979 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
2980 stw_phys(addr, val);
2981}
2982
2983static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2984 uint32_t val)
2985{
2986 check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
2987 stl_phys(addr, val);
2988}
2989
2990static CPUReadMemoryFunc *watch_mem_read[3] = {
2991 watch_mem_readb,
2992 watch_mem_readw,
2993 watch_mem_readl,
2994};
2995
2996static CPUWriteMemoryFunc *watch_mem_write[3] = {
2997 watch_mem_writeb,
2998 watch_mem_writew,
2999 watch_mem_writel,
3000};
3001
3002static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
3003 unsigned int len)
3004{
3005 uint32_t ret;
3006 unsigned int idx;
3007
3008 idx = SUBPAGE_IDX(addr - mmio->base);
3009#if defined(DEBUG_SUBPAGE)
3010 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
3011 mmio, len, addr, idx);
3012#endif
3013 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
3014
3015 return ret;
3016}
3017
3018static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
3019 uint32_t value, unsigned int len)
3020{
3021 unsigned int idx;
3022
3023 idx = SUBPAGE_IDX(addr - mmio->base);
3024#if defined(DEBUG_SUBPAGE)
3025 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
3026 mmio, len, addr, idx, value);
3027#endif
3028 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
3029}
3030
3031static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
3032{
3033#if defined(DEBUG_SUBPAGE)
3034 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
3035#endif
3036
3037 return subpage_readlen(opaque, addr, 0);
3038}
3039
3040static void subpage_writeb (void *opaque, target_phys_addr_t addr,
3041 uint32_t value)
3042{
3043#if defined(DEBUG_SUBPAGE)
3044 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
3045#endif
3046 subpage_writelen(opaque, addr, value, 0);
3047}
3048
3049static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
3050{
3051#if defined(DEBUG_SUBPAGE)
3052 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
3053#endif
3054
3055 return subpage_readlen(opaque, addr, 1);
3056}
3057
3058static void subpage_writew (void *opaque, target_phys_addr_t addr,
3059 uint32_t value)
3060{
3061#if defined(DEBUG_SUBPAGE)
3062 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
3063#endif
3064 subpage_writelen(opaque, addr, value, 1);
3065}
3066
3067static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
3068{
3069#if defined(DEBUG_SUBPAGE)
3070 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
3071#endif
3072
3073 return subpage_readlen(opaque, addr, 2);
3074}
3075
3076static void subpage_writel (void *opaque,
3077 target_phys_addr_t addr, uint32_t value)
3078{
3079#if defined(DEBUG_SUBPAGE)
3080 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
3081#endif
3082 subpage_writelen(opaque, addr, value, 2);
3083}
3084
3085static CPUReadMemoryFunc *subpage_read[] = {
3086 &subpage_readb,
3087 &subpage_readw,
3088 &subpage_readl,
3089};
3090
3091static CPUWriteMemoryFunc *subpage_write[] = {
3092 &subpage_writeb,
3093 &subpage_writew,
3094 &subpage_writel,
3095};
3096
3097static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
3098 ram_addr_t memory)
3099{
3100 int idx, eidx;
3101 unsigned int i;
3102
3103 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
3104 return -1;
3105 idx = SUBPAGE_IDX(start);
3106 eidx = SUBPAGE_IDX(end);
3107#if defined(DEBUG_SUBPAGE)
3108 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
3109 mmio, start, end, idx, eidx, memory);
3110#endif
3111 memory >>= IO_MEM_SHIFT;
3112 for (; idx <= eidx; idx++) {
3113 for (i = 0; i < 4; i++) {
3114 if (io_mem_read[memory][i]) {
3115 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
3116 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
3117 }
3118 if (io_mem_write[memory][i]) {
3119 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
3120 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
3121 }
3122 }
3123 }
3124
3125 return 0;
3126}
3127
3128static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
3129 ram_addr_t orig_memory)
3130{
3131 subpage_t *mmio;
3132 int subpage_memory;
3133
3134 mmio = qemu_mallocz(sizeof(subpage_t));
3135 if (mmio != NULL) {
3136 mmio->base = base;
3137 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
3138#if defined(DEBUG_SUBPAGE)
3139 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
3140 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
3141#endif
3142 *phys = subpage_memory | IO_MEM_SUBPAGE;
3143 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
3144 }
3145
3146 return mmio;
3147}
3148
3149static void io_mem_init(void)
3150{
3151 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
3152 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
3153 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
3154#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
3155 cpu_register_io_memory(IO_MEM_RAM_MISSING >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
3156 io_mem_nb = 6;
3157#else
3158 io_mem_nb = 5;
3159#endif
3160
3161 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
3162 watch_mem_write, NULL);
3163
3164#ifndef VBOX /* VBOX: we do this later when the RAM is allocated. */
3165 /* alloc dirty bits array */
3166 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
3167 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
3168#endif /* !VBOX */
3169}
3170
3171/* mem_read and mem_write are arrays of functions containing the
3172 function to access byte (index 0), word (index 1) and dword (index
3173 2). Functions can be omitted with a NULL function pointer. The
3174 registered functions may be modified dynamically later.
3175 If io_index is non zero, the corresponding io zone is
3176 modified. If it is zero, a new io zone is allocated. The return
3177 value can be used with cpu_register_physical_memory(). (-1) is
3178 returned if error. */
3179int cpu_register_io_memory(int io_index,
3180 CPUReadMemoryFunc **mem_read,
3181 CPUWriteMemoryFunc **mem_write,
3182 void *opaque)
3183{
3184 int i, subwidth = 0;
3185
3186 if (io_index <= 0) {
3187 if (io_mem_nb >= IO_MEM_NB_ENTRIES)
3188 return -1;
3189 io_index = io_mem_nb++;
3190 } else {
3191 if (io_index >= IO_MEM_NB_ENTRIES)
3192 return -1;
3193 }
3194
3195 for(i = 0;i < 3; i++) {
3196 if (!mem_read[i] || !mem_write[i])
3197 subwidth = IO_MEM_SUBWIDTH;
3198 io_mem_read[io_index][i] = mem_read[i];
3199 io_mem_write[io_index][i] = mem_write[i];
3200 }
3201 io_mem_opaque[io_index] = opaque;
3202 return (io_index << IO_MEM_SHIFT) | subwidth;
3203}
3204
3205CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
3206{
3207 return io_mem_write[io_index >> IO_MEM_SHIFT];
3208}
3209
3210CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
3211{
3212 return io_mem_read[io_index >> IO_MEM_SHIFT];
3213}
3214#endif /* !defined(CONFIG_USER_ONLY) */
3215
3216/* physical memory access (slow version, mainly for debug) */
3217#if defined(CONFIG_USER_ONLY)
3218void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3219 int len, int is_write)
3220{
3221 int l, flags;
3222 target_ulong page;
3223 void * p;
3224
3225 while (len > 0) {
3226 page = addr & TARGET_PAGE_MASK;
3227 l = (page + TARGET_PAGE_SIZE) - addr;
3228 if (l > len)
3229 l = len;
3230 flags = page_get_flags(page);
3231 if (!(flags & PAGE_VALID))
3232 return;
3233 if (is_write) {
3234 if (!(flags & PAGE_WRITE))
3235 return;
3236 /* XXX: this code should not depend on lock_user */
3237 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3238 /* FIXME - should this return an error rather than just fail? */
3239 return;
3240 memcpy(p, buf, len);
3241 unlock_user(p, addr, len);
3242 } else {
3243 if (!(flags & PAGE_READ))
3244 return;
3245 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3246 /* FIXME - should this return an error rather than just fail? */
3247 return;
3248 memcpy(buf, p, len);
3249 unlock_user(p, addr, 0);
3250 }
3251 len -= l;
3252 buf += l;
3253 addr += l;
3254 }
3255}
3256
3257#else
3258void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3259 int len, int is_write)
3260{
3261 int l, io_index;
3262 uint8_t *ptr;
3263 uint32_t val;
3264 target_phys_addr_t page;
3265 unsigned long pd;
3266 PhysPageDesc *p;
3267
3268 while (len > 0) {
3269 page = addr & TARGET_PAGE_MASK;
3270 l = (page + TARGET_PAGE_SIZE) - addr;
3271 if (l > len)
3272 l = len;
3273 p = phys_page_find(page >> TARGET_PAGE_BITS);
3274 if (!p) {
3275 pd = IO_MEM_UNASSIGNED;
3276 } else {
3277 pd = p->phys_offset;
3278 }
3279
3280 if (is_write) {
3281 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3282 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3283 /* XXX: could force cpu_single_env to NULL to avoid
3284 potential bugs */
3285 if (l >= 4 && ((addr & 3) == 0)) {
3286 /* 32 bit write access */
3287#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3288 val = ldl_p(buf);
3289#else
3290 val = *(const uint32_t *)buf;
3291#endif
3292 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3293 l = 4;
3294 } else if (l >= 2 && ((addr & 1) == 0)) {
3295 /* 16 bit write access */
3296#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3297 val = lduw_p(buf);
3298#else
3299 val = *(const uint16_t *)buf;
3300#endif
3301 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
3302 l = 2;
3303 } else {
3304 /* 8 bit write access */
3305#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3306 val = ldub_p(buf);
3307#else
3308 val = *(const uint8_t *)buf;
3309#endif
3310 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
3311 l = 1;
3312 }
3313 } else {
3314 unsigned long addr1;
3315 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3316 /* RAM case */
3317#ifdef VBOX
3318 remR3PhysWrite(addr1, buf, l); NOREF(ptr);
3319#else
3320 ptr = phys_ram_base + addr1;
3321 memcpy(ptr, buf, l);
3322#endif
3323 if (!cpu_physical_memory_is_dirty(addr1)) {
3324 /* invalidate code */
3325 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3326 /* set dirty bit */
3327#ifdef VBOX
3328 if (RT_LIKELY((addr1 >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
3329#endif
3330 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3331 (0xff & ~CODE_DIRTY_FLAG);
3332 }
3333 }
3334 } else {
3335 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3336 !(pd & IO_MEM_ROMD)) {
3337 /* I/O case */
3338 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3339 if (l >= 4 && ((addr & 3) == 0)) {
3340 /* 32 bit read access */
3341 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3342#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3343 stl_p(buf, val);
3344#else
3345 *(uint32_t *)buf = val;
3346#endif
3347 l = 4;
3348 } else if (l >= 2 && ((addr & 1) == 0)) {
3349 /* 16 bit read access */
3350 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
3351#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3352 stw_p(buf, val);
3353#else
3354 *(uint16_t *)buf = val;
3355#endif
3356 l = 2;
3357 } else {
3358 /* 8 bit read access */
3359 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
3360#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
3361 stb_p(buf, val);
3362#else
3363 *(uint8_t *)buf = val;
3364#endif
3365 l = 1;
3366 }
3367 } else {
3368 /* RAM case */
3369#ifdef VBOX
3370 remR3PhysRead((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), buf, l); NOREF(ptr);
3371#else
3372 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3373 (addr & ~TARGET_PAGE_MASK);
3374 memcpy(buf, ptr, l);
3375#endif
3376 }
3377 }
3378 len -= l;
3379 buf += l;
3380 addr += l;
3381 }
3382}
3383
3384#ifndef VBOX
3385/* used for ROM loading : can write in RAM and ROM */
3386void cpu_physical_memory_write_rom(target_phys_addr_t addr,
3387 const uint8_t *buf, int len)
3388{
3389 int l;
3390 uint8_t *ptr;
3391 target_phys_addr_t page;
3392 unsigned long pd;
3393 PhysPageDesc *p;
3394
3395 while (len > 0) {
3396 page = addr & TARGET_PAGE_MASK;
3397 l = (page + TARGET_PAGE_SIZE) - addr;
3398 if (l > len)
3399 l = len;
3400 p = phys_page_find(page >> TARGET_PAGE_BITS);
3401 if (!p) {
3402 pd = IO_MEM_UNASSIGNED;
3403 } else {
3404 pd = p->phys_offset;
3405 }
3406
3407 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
3408 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3409 !(pd & IO_MEM_ROMD)) {
3410 /* do nothing */
3411 } else {
3412 unsigned long addr1;
3413 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3414 /* ROM/RAM case */
3415 ptr = phys_ram_base + addr1;
3416 memcpy(ptr, buf, l);
3417 }
3418 len -= l;
3419 buf += l;
3420 addr += l;
3421 }
3422}
3423#endif /* !VBOX */
3424
3425
3426/* warning: addr must be aligned */
3427uint32_t ldl_phys(target_phys_addr_t addr)
3428{
3429 int io_index;
3430 uint8_t *ptr;
3431 uint32_t val;
3432 unsigned long pd;
3433 PhysPageDesc *p;
3434
3435 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3436 if (!p) {
3437 pd = IO_MEM_UNASSIGNED;
3438 } else {
3439 pd = p->phys_offset;
3440 }
3441
3442 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3443 !(pd & IO_MEM_ROMD)) {
3444 /* I/O case */
3445 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3446 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3447 } else {
3448 /* RAM case */
3449#ifndef VBOX
3450 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3451 (addr & ~TARGET_PAGE_MASK);
3452 val = ldl_p(ptr);
3453#else
3454 val = remR3PhysReadU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
3455#endif
3456 }
3457 return val;
3458}
3459
3460/* warning: addr must be aligned */
3461uint64_t ldq_phys(target_phys_addr_t addr)
3462{
3463 int io_index;
3464 uint8_t *ptr;
3465 uint64_t val;
3466 unsigned long pd;
3467 PhysPageDesc *p;
3468
3469 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3470 if (!p) {
3471 pd = IO_MEM_UNASSIGNED;
3472 } else {
3473 pd = p->phys_offset;
3474 }
3475
3476 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3477 !(pd & IO_MEM_ROMD)) {
3478 /* I/O case */
3479 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3480#ifdef TARGET_WORDS_BIGENDIAN
3481 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3482 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3483#else
3484 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3485 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3486#endif
3487 } else {
3488 /* RAM case */
3489#ifndef VBOX
3490 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3491 (addr & ~TARGET_PAGE_MASK);
3492 val = ldq_p(ptr);
3493#else
3494 val = remR3PhysReadU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
3495#endif
3496 }
3497 return val;
3498}
3499
3500/* XXX: optimize */
3501uint32_t ldub_phys(target_phys_addr_t addr)
3502{
3503 uint8_t val;
3504 cpu_physical_memory_read(addr, &val, 1);
3505 return val;
3506}
3507
3508/* XXX: optimize */
3509uint32_t lduw_phys(target_phys_addr_t addr)
3510{
3511 uint16_t val;
3512 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3513 return tswap16(val);
3514}
3515
3516/* warning: addr must be aligned. The ram page is not masked as dirty
3517 and the code inside is not invalidated. It is useful if the dirty
3518 bits are used to track modified PTEs */
3519void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3520{
3521 int io_index;
3522 uint8_t *ptr;
3523 unsigned long pd;
3524 PhysPageDesc *p;
3525
3526 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3527 if (!p) {
3528 pd = IO_MEM_UNASSIGNED;
3529 } else {
3530 pd = p->phys_offset;
3531 }
3532
3533 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3534 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3535 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3536 } else {
3537#ifndef VBOX
3538 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3539 (addr & ~TARGET_PAGE_MASK);
3540 stl_p(ptr, val);
3541#else
3542 remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
3543#endif
3544#ifndef VBOX
3545 if (unlikely(in_migration)) {
3546 if (!cpu_physical_memory_is_dirty(addr1)) {
3547 /* invalidate code */
3548 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3549 /* set dirty bit */
3550 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3551 (0xff & ~CODE_DIRTY_FLAG);
3552 }
3553 }
3554#endif
3555 }
3556}
3557
3558void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3559{
3560 int io_index;
3561 uint8_t *ptr;
3562 unsigned long pd;
3563 PhysPageDesc *p;
3564
3565 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3566 if (!p) {
3567 pd = IO_MEM_UNASSIGNED;
3568 } else {
3569 pd = p->phys_offset;
3570 }
3571
3572 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3573 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3574#ifdef TARGET_WORDS_BIGENDIAN
3575 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3576 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3577#else
3578 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3579 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3580#endif
3581 } else {
3582#ifndef VBOX
3583 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3584 (addr & ~TARGET_PAGE_MASK);
3585 stq_p(ptr, val);
3586#else
3587 remR3PhysWriteU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
3588#endif
3589 }
3590}
3591
3592
3593/* warning: addr must be aligned */
3594void stl_phys(target_phys_addr_t addr, uint32_t val)
3595{
3596 int io_index;
3597 uint8_t *ptr;
3598 unsigned long pd;
3599 PhysPageDesc *p;
3600
3601 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3602 if (!p) {
3603 pd = IO_MEM_UNASSIGNED;
3604 } else {
3605 pd = p->phys_offset;
3606 }
3607
3608 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3609 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3610 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3611 } else {
3612 unsigned long addr1;
3613 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3614 /* RAM case */
3615#ifndef VBOX
3616 ptr = phys_ram_base + addr1;
3617 stl_p(ptr, val);
3618#else
3619 remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
3620#endif
3621 if (!cpu_physical_memory_is_dirty(addr1)) {
3622 /* invalidate code */
3623 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3624 /* set dirty bit */
3625#ifdef VBOX
3626 if (RT_LIKELY((addr1 >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
3627#endif
3628 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3629 (0xff & ~CODE_DIRTY_FLAG);
3630 }
3631 }
3632}
3633
3634/* XXX: optimize */
3635void stb_phys(target_phys_addr_t addr, uint32_t val)
3636{
3637 uint8_t v = val;
3638 cpu_physical_memory_write(addr, &v, 1);
3639}
3640
3641/* XXX: optimize */
3642void stw_phys(target_phys_addr_t addr, uint32_t val)
3643{
3644 uint16_t v = tswap16(val);
3645 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3646}
3647
3648/* XXX: optimize */
3649void stq_phys(target_phys_addr_t addr, uint64_t val)
3650{
3651 val = tswap64(val);
3652 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3653}
3654
3655#endif
3656
3657/* virtual memory access for debug */
3658int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3659 uint8_t *buf, int len, int is_write)
3660{
3661 int l;
3662 target_ulong page, phys_addr;
3663
3664 while (len > 0) {
3665 page = addr & TARGET_PAGE_MASK;
3666 phys_addr = cpu_get_phys_page_debug(env, page);
3667 /* if no physical page mapped, return an error */
3668 if (phys_addr == -1)
3669 return -1;
3670 l = (page + TARGET_PAGE_SIZE) - addr;
3671 if (l > len)
3672 l = len;
3673 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
3674 buf, l, is_write);
3675 len -= l;
3676 buf += l;
3677 addr += l;
3678 }
3679 return 0;
3680}
3681
3682/* in deterministic execution mode, instructions doing device I/Os
3683 must be at the end of the TB */
3684void cpu_io_recompile(CPUState *env, void *retaddr)
3685{
3686 TranslationBlock *tb;
3687 uint32_t n, cflags;
3688 target_ulong pc, cs_base;
3689 uint64_t flags;
3690
3691 tb = tb_find_pc((unsigned long)retaddr);
3692 if (!tb) {
3693 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3694 retaddr);
3695 }
3696 n = env->icount_decr.u16.low + tb->icount;
3697 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3698 /* Calculate how many instructions had been executed before the fault
3699 occurred. */
3700 n = n - env->icount_decr.u16.low;
3701 /* Generate a new TB ending on the I/O insn. */
3702 n++;
3703 /* On MIPS and SH, delay slot instructions can only be restarted if
3704 they were already the first instruction in the TB. If this is not
3705 the first instruction in a TB then re-execute the preceding
3706 branch. */
3707#if defined(TARGET_MIPS)
3708 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3709 env->active_tc.PC -= 4;
3710 env->icount_decr.u16.low++;
3711 env->hflags &= ~MIPS_HFLAG_BMASK;
3712 }
3713#elif defined(TARGET_SH4)
3714 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3715 && n > 1) {
3716 env->pc -= 2;
3717 env->icount_decr.u16.low++;
3718 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3719 }
3720#endif
3721 /* This should never happen. */
3722 if (n > CF_COUNT_MASK)
3723 cpu_abort(env, "TB too big during recompile");
3724
3725 cflags = n | CF_LAST_IO;
3726 pc = tb->pc;
3727 cs_base = tb->cs_base;
3728 flags = tb->flags;
3729 tb_phys_invalidate(tb, -1);
3730 /* FIXME: In theory this could raise an exception. In practice
3731 we have already translated the block once so it's probably ok. */
3732 tb_gen_code(env, pc, cs_base, flags, cflags);
3733 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
3734 the first in the TB) then we end up generating a whole new TB and
3735 repeating the fault, which is horribly inefficient.
3736 Better would be to execute just this insn uncached, or generate a
3737 second new TB. */
3738 cpu_resume_from_signal(env, NULL);
3739}
3740
3741#ifndef VBOX
3742void dump_exec_info(FILE *f,
3743 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3744{
3745 int i, target_code_size, max_target_code_size;
3746 int direct_jmp_count, direct_jmp2_count, cross_page;
3747 TranslationBlock *tb;
3748
3749 target_code_size = 0;
3750 max_target_code_size = 0;
3751 cross_page = 0;
3752 direct_jmp_count = 0;
3753 direct_jmp2_count = 0;
3754 for(i = 0; i < nb_tbs; i++) {
3755 tb = &tbs[i];
3756 target_code_size += tb->size;
3757 if (tb->size > max_target_code_size)
3758 max_target_code_size = tb->size;
3759 if (tb->page_addr[1] != -1)
3760 cross_page++;
3761 if (tb->tb_next_offset[0] != 0xffff) {
3762 direct_jmp_count++;
3763 if (tb->tb_next_offset[1] != 0xffff) {
3764 direct_jmp2_count++;
3765 }
3766 }
3767 }
3768 /* XXX: avoid using doubles ? */
3769 cpu_fprintf(f, "Translation buffer state:\n");
3770 cpu_fprintf(f, "gen code size %ld/%ld\n",
3771 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3772 cpu_fprintf(f, "TB count %d/%d\n",
3773 nb_tbs, code_gen_max_blocks);
3774 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
3775 nb_tbs ? target_code_size / nb_tbs : 0,
3776 max_target_code_size);
3777 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
3778 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3779 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
3780 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3781 cross_page,
3782 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3783 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
3784 direct_jmp_count,
3785 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3786 direct_jmp2_count,
3787 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
3788 cpu_fprintf(f, "\nStatistics:\n");
3789 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3790 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3791 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
3792 tcg_dump_info(f, cpu_fprintf);
3793}
3794#endif /* !VBOX */
3795
3796#if !defined(CONFIG_USER_ONLY)
3797
3798#define MMUSUFFIX _cmmu
3799#define GETPC() NULL
3800#define env cpu_single_env
3801#define SOFTMMU_CODE_ACCESS
3802
3803#define SHIFT 0
3804#include "softmmu_template.h"
3805
3806#define SHIFT 1
3807#include "softmmu_template.h"
3808
3809#define SHIFT 2
3810#include "softmmu_template.h"
3811
3812#define SHIFT 3
3813#include "softmmu_template.h"
3814
3815#undef env
3816
3817#endif
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