tcg-target.c@ 14542

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1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24	/*
25	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
26	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
27	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
28	* a choice of LGPL license versions is made available with the language indicating
29	* that LGPLv2 or any later version may be used, or where a choice of which version
30	* of the LGPL is applied is otherwise unspecified.
31	*/
32	#ifndef NDEBUG
33	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34	"%eax",
35	"%ecx",
36	"%edx",
37	"%ebx",
38	"%esp",
39	"%ebp",
40	"%esi",
41	"%edi",
42	};
43	#endif
44
45	static const int tcg_target_reg_alloc_order[] = {
46	TCG_REG_EAX,
47	TCG_REG_EDX,
48	TCG_REG_ECX,
49	TCG_REG_EBX,
50	#ifndef VBOX
51	TCG_REG_ESI,
52	#endif
53	TCG_REG_EDI,
54	TCG_REG_EBP,
55	};
56
57	static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
58	static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
59
60	static uint8_t *tb_ret_addr;
61
62	static void patch_reloc(uint8_t *code_ptr, int type,
63	tcg_target_long value, tcg_target_long addend)
64	{
65	value += addend;
66	switch(type) {
67	case R_386_32:
68	(uint32_t )code_ptr = value;
69	break;
70	case R_386_PC32:
71	(uint32_t )code_ptr = value - (long)code_ptr;
72	break;
73	default:
74	tcg_abort();
75	}
76	}
77
78	/* maximum number of register used for input function arguments */
79	#ifndef VBOX
80	static inline int tcg_target_get_call_iarg_regs_count(int flags)
81	#else /* VBOX */
82	DECLINLINE(int) tcg_target_get_call_iarg_regs_count(int flags)
83	#endif /* VBOX */
84	{
85	flags &= TCG_CALL_TYPE_MASK;
86	switch(flags) {
87	case TCG_CALL_TYPE_STD:
88	return 0;
89	case TCG_CALL_TYPE_REGPARM_1:
90	case TCG_CALL_TYPE_REGPARM_2:
91	case TCG_CALL_TYPE_REGPARM:
92	return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
93	default:
94	tcg_abort();
95	}
96	}
97
98	/* parse target specific constraints */
99	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
100	{
101	const char *ct_str;
102
103	ct_str = *pct_str;
104	switch(ct_str[0]) {
105	case 'a':
106	ct->ct \|= TCG_CT_REG;
107	tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
108	break;
109	case 'b':
110	ct->ct \|= TCG_CT_REG;
111	tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
112	break;
113	case 'c':
114	ct->ct \|= TCG_CT_REG;
115	tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
116	break;
117	case 'd':
118	ct->ct \|= TCG_CT_REG;
119	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
120	break;
121	case 'S':
122	ct->ct \|= TCG_CT_REG;
123	tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
124	break;
125	case 'D':
126	ct->ct \|= TCG_CT_REG;
127	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
128	break;
129	case 'q':
130	ct->ct \|= TCG_CT_REG;
131	tcg_regset_set32(ct->u.regs, 0, 0xf);
132	break;
133	case 'r':
134	ct->ct \|= TCG_CT_REG;
135	tcg_regset_set32(ct->u.regs, 0, 0xff);
136	break;
137
138	/* qemu_ld/st address constraint */
139	case 'L':
140	ct->ct \|= TCG_CT_REG;
141	tcg_regset_set32(ct->u.regs, 0, 0xff);
142	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
143	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
144	break;
145	default:
146	return -1;
147	}
148	ct_str++;
149	*pct_str = ct_str;
150	return 0;
151	}
152
153	/* test if a constant matches the constraint */
154	#ifndef VBOX
155	static inline int tcg_target_const_match(tcg_target_long val,
156	#else /* VBOX */
157	DECLINLINE(int) tcg_target_const_match(tcg_target_long val,
158	#endif /* VBOX */
159	const TCGArgConstraint *arg_ct)
160	{
161	int ct;
162	ct = arg_ct->ct;
163	if (ct & TCG_CT_CONST)
164	return 1;
165	else
166	return 0;
167	}
168
169	#define ARITH_ADD 0
170	#define ARITH_OR 1
171	#define ARITH_ADC 2
172	#define ARITH_SBB 3
173	#define ARITH_AND 4
174	#define ARITH_SUB 5
175	#define ARITH_XOR 6
176	#define ARITH_CMP 7
177
178	#define SHIFT_SHL 4
179	#define SHIFT_SHR 5
180	#define SHIFT_SAR 7
181
182	#define JCC_JMP (-1)
183	#define JCC_JO 0x0
184	#define JCC_JNO 0x1
185	#define JCC_JB 0x2
186	#define JCC_JAE 0x3
187	#define JCC_JE 0x4
188	#define JCC_JNE 0x5
189	#define JCC_JBE 0x6
190	#define JCC_JA 0x7
191	#define JCC_JS 0x8
192	#define JCC_JNS 0x9
193	#define JCC_JP 0xa
194	#define JCC_JNP 0xb
195	#define JCC_JL 0xc
196	#define JCC_JGE 0xd
197	#define JCC_JLE 0xe
198	#define JCC_JG 0xf
199
200	#define P_EXT 0x100 /* 0x0f opcode prefix */
201
202	#if !defined(VBOX) \|\| !defined(_MSC_VER)
203	static const uint8_t tcg_cond_to_jcc[10] = {
204	[TCG_COND_EQ] = JCC_JE,
205	[TCG_COND_NE] = JCC_JNE,
206	[TCG_COND_LT] = JCC_JL,
207	[TCG_COND_GE] = JCC_JGE,
208	[TCG_COND_LE] = JCC_JLE,
209	[TCG_COND_GT] = JCC_JG,
210	[TCG_COND_LTU] = JCC_JB,
211	[TCG_COND_GEU] = JCC_JAE,
212	[TCG_COND_LEU] = JCC_JBE,
213	[TCG_COND_GTU] = JCC_JA,
214	};
215	#else
216	/* Fortunately, ordering is right */
217	static const uint8_t tcg_cond_to_jcc[10] = {
218	JCC_JE,
219	JCC_JNE,
220	JCC_JL,
221	JCC_JGE,
222	JCC_JLE,
223	JCC_JG,
224	JCC_JB,
225	JCC_JAE,
226	JCC_JBE,
227	JCC_JA,
228	};
229	#endif
230
231	#ifndef VBOX
232	static inline void tcg_out_opc(TCGContext *s, int opc)
233	#else /* VBOX */
234	DECLINLINE(void) tcg_out_opc(TCGContext *s, int opc)
235	#endif /* VBOX */
236	{
237	if (opc & P_EXT)
238	tcg_out8(s, 0x0f);
239	tcg_out8(s, opc);
240	}
241
242	#ifndef VBOX
243	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
244	#else /* VBOX */
245	DECLINLINE(void) tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
246	#endif /* VBOX */
247	{
248	tcg_out_opc(s, opc);
249	tcg_out8(s, 0xc0 \| (r << 3) \| rm);
250	}
251
252	/* rm == -1 means no register index */
253	#ifndef VBOX
254	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
255	#else /* VBOX */
256	DECLINLINE(void) tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
257	#endif /* VBOX */
258	int32_t offset)
259	{
260	tcg_out_opc(s, opc);
261	if (rm == -1) {
262	tcg_out8(s, 0x05 \| (r << 3));
263	tcg_out32(s, offset);
264	} else if (offset == 0 && rm != TCG_REG_EBP) {
265	if (rm == TCG_REG_ESP) {
266	tcg_out8(s, 0x04 \| (r << 3));
267	tcg_out8(s, 0x24);
268	} else {
269	tcg_out8(s, 0x00 \| (r << 3) \| rm);
270	}
271	} else if ((int8_t)offset == offset) {
272	if (rm == TCG_REG_ESP) {
273	tcg_out8(s, 0x44 \| (r << 3));
274	tcg_out8(s, 0x24);
275	} else {
276	tcg_out8(s, 0x40 \| (r << 3) \| rm);
277	}
278	tcg_out8(s, offset);
279	} else {
280	if (rm == TCG_REG_ESP) {
281	tcg_out8(s, 0x84 \| (r << 3));
282	tcg_out8(s, 0x24);
283	} else {
284	tcg_out8(s, 0x80 \| (r << 3) \| rm);
285	}
286	tcg_out32(s, offset);
287	}
288	}
289
290	#ifndef VBOX
291	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
292	#else /* VBOX */
293	DECLINLINE(void) tcg_out_mov(TCGContext *s, int ret, int arg)
294	#endif /* VBOX */
295	{
296	if (arg != ret)
297	tcg_out_modrm(s, 0x8b, ret, arg);
298	}
299
300	#ifndef VBOX
301	static inline void tcg_out_movi(TCGContext *s, TCGType type,
302	#else /* VBOX */
303	DECLINLINE(void) tcg_out_movi(TCGContext *s, TCGType type,
304	#endif /* VBOX */
305	int ret, int32_t arg)
306	{
307	if (arg == 0) {
308	/* xor r0,r0 */
309	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret);
310	} else {
311	tcg_out8(s, 0xb8 + ret);
312	tcg_out32(s, arg);
313	}
314	}
315
316	#ifndef VBOX
317	static inline void tcg_out_push(TCGContext *s, int reg)
318	#else /* VBOX */
319	DECLINLINE(void) tcg_out_push(TCGContext *s, int reg)
320	#endif /* VBOX */
321	{
322	tcg_out_opc(s, 0x50 + reg);
323	}
324
325	#ifndef VBOX
326	static inline void tcg_out_pop(TCGContext *s, int reg)
327	#else /* VBOX */
328	DECLINLINE(void) tcg_out_pop(TCGContext *s, int reg)
329	#endif /* VBOX */
330	{
331	tcg_out_opc(s, 0x58 + reg);
332	}
333
334	#ifndef VBOX
335	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
336	#else /* VBOX */
337	DECLINLINE(void) tcg_out_ld(TCGContext *s, TCGType type, int ret,
338	#endif /* VBOX */
339	int arg1, tcg_target_long arg2)
340	{
341	/* movl */
342	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
343	}
344
345	#ifndef VBOX
346	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
347	#else /* VBOX */
348	DECLINLINE(void) tcg_out_st(TCGContext *s, TCGType type, int arg,
349	#endif /* VBOX */
350	int arg1, tcg_target_long arg2)
351	{
352	/* movl */
353	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
354	}
355
356	#ifndef VBOX
357	static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
358	#else /* VBOX */
359	DECLINLINE(void) tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
360	#endif /* VBOX */
361	{
362	if (val == (int8_t)val) {
363	tcg_out_modrm(s, 0x83, c, r0);
364	tcg_out8(s, val);
365	} else {
366	tcg_out_modrm(s, 0x81, c, r0);
367	tcg_out32(s, val);
368	}
369	}
370
371	void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
372	{
373	if (val != 0)
374	tgen_arithi(s, ARITH_ADD, reg, val);
375	}
376
377	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
378	{
379	int32_t val, val1;
380	TCGLabel *l = &s->labels[label_index];
381
382	if (l->has_value) {
383	val = l->u.value - (tcg_target_long)s->code_ptr;
384	val1 = val - 2;
385	if ((int8_t)val1 == val1) {
386	if (opc == -1)
387	tcg_out8(s, 0xeb);
388	else
389	tcg_out8(s, 0x70 + opc);
390	tcg_out8(s, val1);
391	} else {
392	if (opc == -1) {
393	tcg_out8(s, 0xe9);
394	tcg_out32(s, val - 5);
395	} else {
396	tcg_out8(s, 0x0f);
397	tcg_out8(s, 0x80 + opc);
398	tcg_out32(s, val - 6);
399	}
400	}
401	} else {
402	if (opc == -1) {
403	tcg_out8(s, 0xe9);
404	} else {
405	tcg_out8(s, 0x0f);
406	tcg_out8(s, 0x80 + opc);
407	}
408	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
409	s->code_ptr += 4;
410	}
411	}
412
413	static void tcg_out_brcond(TCGContext *s, int cond,
414	TCGArg arg1, TCGArg arg2, int const_arg2,
415	int label_index)
416	{
417	if (const_arg2) {
418	if (arg2 == 0) {
419	/* test r, r */
420	tcg_out_modrm(s, 0x85, arg1, arg1);
421	} else {
422	tgen_arithi(s, ARITH_CMP, arg1, arg2);
423	}
424	} else {
425	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3), arg2, arg1);
426	}
427	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
428	}
429
430	#ifdef VBOX
431	DECLINLINE(void) tcg_out_long_call(TCGContext *s, tcg_target_long dst)
432	{
433	intptr_t disp = dst - (tcg_target_long)s->code_ptr - 5;
434	tcg_out8(s, 0xe8); /* call disp32 */
435	tcg_out32(s, disp); /* disp32 */
436	}
437
438	#endif /* VBOX */
439
440
441	/* XXX: we implement it at the target level to avoid having to
442	handle cross basic blocks temporaries */
443	static void tcg_out_brcond2(TCGContext *s,
444	const TCGArg args, const int const_args)
445	{
446	int label_next;
447	label_next = gen_new_label();
448	switch(args[4]) {
449	case TCG_COND_EQ:
450	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
451	tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
452	break;
453	case TCG_COND_NE:
454	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
455	tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
456	break;
457	case TCG_COND_LT:
458	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
459	tcg_out_jxx(s, JCC_JNE, label_next);
460	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
461	break;
462	case TCG_COND_LE:
463	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
464	tcg_out_jxx(s, JCC_JNE, label_next);
465	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
466	break;
467	case TCG_COND_GT:
468	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
469	tcg_out_jxx(s, JCC_JNE, label_next);
470	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
471	break;
472	case TCG_COND_GE:
473	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
474	tcg_out_jxx(s, JCC_JNE, label_next);
475	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
476	break;
477	case TCG_COND_LTU:
478	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
479	tcg_out_jxx(s, JCC_JNE, label_next);
480	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
481	break;
482	case TCG_COND_LEU:
483	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
484	tcg_out_jxx(s, JCC_JNE, label_next);
485	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
486	break;
487	case TCG_COND_GTU:
488	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
489	tcg_out_jxx(s, JCC_JNE, label_next);
490	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
491	break;
492	case TCG_COND_GEU:
493	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
494	tcg_out_jxx(s, JCC_JNE, label_next);
495	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
496	break;
497	default:
498	tcg_abort();
499	}
500	tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
501	}
502
503	#if defined(CONFIG_SOFTMMU)
504
505	#include "../../softmmu_defs.h"
506
507	static void *qemu_ld_helpers[4] = {
508	__ldb_mmu,
509	__ldw_mmu,
510	__ldl_mmu,
511	__ldq_mmu,
512	};
513
514	static void *qemu_st_helpers[4] = {
515	__stb_mmu,
516	__stw_mmu,
517	__stl_mmu,
518	__stq_mmu,
519	};
520	#endif
521
522	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
523	static void *vbox_ld_helpers[] = {
524	remR3PhysReadU8,
525	remR3PhysReadU16,
526	remR3PhysReadU32,
527	remR3PhysReadU64,
528	remR3PhysReadS8,
529	remR3PhysReadS16,
530	remR3PhysReadS32,
531	remR3PhysReadS64,
532	};
533
534	static void *vbox_st_helpers[] = {
535	remR3PhysWriteU8,
536	remR3PhysWriteU16,
537	remR3PhysWriteU32,
538	remR3PhysWriteU64
539	};
540
541	static void tcg_out_vbox_phys_read(TCGContext *s, int index,
542	int addr_reg,
543	int data_reg, int data_reg2) {
544	int useReg2 = ((index & 3) == 3);
545
546	/** @todo: should we make phys addess accessors fastcalls - probably not a big deal */
547	/* out parameter (address), note that phys address is always 64-bit */
548	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
549	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
550	tcg_out_push(s, addr_reg);
551
552	tcg_out_long_call(s, (tcg_target_long)vbox_ld_helpers[index]);
553
554	/* mov %eax, data_reg */
555	tcg_out_mov(s, data_reg, TCG_REG_EAX);
556
557	/* returned 64-bit value */
558	if (useReg2)
559	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
560
561	/* clean stack after us */
562	tcg_out_addi(s, TCG_REG_ESP, 8);
563	}
564
565	static void tcg_out_vbox_phys_write(TCGContext *s, int index,
566	int addr_reg,
567	int val_reg, int val_reg2) {
568	int useReg2 = ((index & 3) == 3);
569
570	/** @todo: should we make phys addess accessors fastcalls - probably not a big deal */
571	/* out parameter (value2) */
572	if (useReg2)
573	tcg_out_push(s, val_reg2);
574	/* out parameter (value) */
575	tcg_out_push(s, val_reg);
576	/* out parameter (address), note that phys address is always 64-bit */
577	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
578	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
579	tcg_out_push(s, addr_reg);
580
581	/* call it */
582	tcg_out_long_call(s, (tcg_target_long)vbox_st_helpers[index]);
583
584	/* clean stack after us */
585	tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
586
587	}
588	#endif
589
590	/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
591	EAX. It will be useful once fixed registers globals are less
592	common. */
593	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
594	int opc)
595	{
596	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
597	#if defined(CONFIG_SOFTMMU)
598	uint8_t label1_ptr, label2_ptr;
599	#endif
600	#if TARGET_LONG_BITS == 64
601	#if defined(CONFIG_SOFTMMU)
602	uint8_t *label3_ptr;
603	#endif
604	int addr_reg2;
605	#endif
606
607	data_reg = *args++;
608	if (opc == 3)
609	data_reg2 = *args++;
610	else
611	data_reg2 = 0;
612	addr_reg = *args++;
613	#if TARGET_LONG_BITS == 64
614	addr_reg2 = *args++;
615	#endif
616	mem_index = *args;
617	s_bits = opc & 3;
618
619	r0 = TCG_REG_EAX;
620	r1 = TCG_REG_EDX;
621
622	#if defined(CONFIG_SOFTMMU)
623	tcg_out_mov(s, r1, addr_reg);
624
625	tcg_out_mov(s, r0, addr_reg);
626
627	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
628	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
629
630	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
631	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
632
633	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
634	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
635
636	#ifndef VBOX
637	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
638	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
639	tcg_out8(s, (5 << 3) \| r1);
640	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
641	#else
642	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
643	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
644	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
645	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
646	#endif
647
648	/* cmp 0(r1), r0 */
649	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
650
651	tcg_out_mov(s, r0, addr_reg);
652
653	#if TARGET_LONG_BITS == 32
654	/* je label1 */
655	tcg_out8(s, 0x70 + JCC_JE);
656	label1_ptr = s->code_ptr;
657	s->code_ptr++;
658	#else
659	/* jne label3 */
660	tcg_out8(s, 0x70 + JCC_JNE);
661	label3_ptr = s->code_ptr;
662	s->code_ptr++;
663
664	/* cmp 4(r1), addr_reg2 */
665	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
666
667	/* je label1 */
668	tcg_out8(s, 0x70 + JCC_JE);
669	label1_ptr = s->code_ptr;
670	s->code_ptr++;
671
672	/* label3: */
673	*label3_ptr = s->code_ptr - label3_ptr - 1;
674	#endif
675
676	/* XXX: move that code at the end of the TB */
677	#if TARGET_LONG_BITS == 32
678	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
679	#else
680	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
681	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
682	#endif
683	tcg_out8(s, 0xe8);
684	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
685	(tcg_target_long)s->code_ptr - 4);
686
687	switch(opc) {
688	case 0 \| 4:
689	/* movsbl */
690	tcg_out_modrm(s, 0xbe \| P_EXT, data_reg, TCG_REG_EAX);
691	break;
692	case 1 \| 4:
693	/* movswl */
694	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, TCG_REG_EAX);
695	break;
696	case 0:
697	case 1:
698	case 2:
699	default:
700	tcg_out_mov(s, data_reg, TCG_REG_EAX);
701	break;
702	case 3:
703	if (data_reg == TCG_REG_EDX) {
704	tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
705	tcg_out_mov(s, data_reg2, TCG_REG_EAX);
706	} else {
707	tcg_out_mov(s, data_reg, TCG_REG_EAX);
708	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
709	}
710	break;
711	}
712
713	/* jmp label2 */
714	tcg_out8(s, 0xeb);
715	label2_ptr = s->code_ptr;
716	s->code_ptr++;
717
718	/* label1: */
719	*label1_ptr = s->code_ptr - label1_ptr - 1;
720
721	/* add x(r1), r0 */
722	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
723	offsetof(CPUTLBEntry, addr_read));
724	#else
725	r0 = addr_reg;
726	#endif
727
728	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
729	#ifdef TARGET_WORDS_BIGENDIAN
730	bswap = 1;
731	#else
732	bswap = 0;
733	#endif
734	switch(opc) {
735	case 0:
736	/* movzbl */
737	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
738	break;
739	case 0 \| 4:
740	/* movsbl */
741	tcg_out_modrm_offset(s, 0xbe \| P_EXT, data_reg, r0, 0);
742	break;
743	case 1:
744	/* movzwl */
745	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
746	if (bswap) {
747	/* rolw $8, data_reg */
748	tcg_out8(s, 0x66);
749	tcg_out_modrm(s, 0xc1, 0, data_reg);
750	tcg_out8(s, 8);
751	}
752	break;
753	case 1 \| 4:
754	/* movswl */
755	tcg_out_modrm_offset(s, 0xbf \| P_EXT, data_reg, r0, 0);
756	if (bswap) {
757	/* rolw $8, data_reg */
758	tcg_out8(s, 0x66);
759	tcg_out_modrm(s, 0xc1, 0, data_reg);
760	tcg_out8(s, 8);
761
762	/* movswl data_reg, data_reg */
763	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, data_reg);
764	}
765	break;
766	case 2:
767	/* movl (r0), data_reg */
768	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
769	if (bswap) {
770	/* bswap */
771	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
772	}
773	break;
774	case 3:
775	/* XXX: could be nicer */
776	if (r0 == data_reg) {
777	r1 = TCG_REG_EDX;
778	if (r1 == data_reg)
779	r1 = TCG_REG_EAX;
780	tcg_out_mov(s, r1, r0);
781	r0 = r1;
782	}
783	if (!bswap) {
784	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
785	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
786	} else {
787	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
788	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
789
790	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
791	/* bswap */
792	tcg_out_opc(s, (0xc8 + data_reg2) \| P_EXT);
793	}
794	break;
795	default:
796	tcg_abort();
797	}
798	#else /* VBOX */
799	tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
800	#endif
801
802
803	#if defined(CONFIG_SOFTMMU)
804	/* label2: */
805	*label2_ptr = s->code_ptr - label2_ptr - 1;
806	#endif
807	}
808
809
810	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
811	int opc)
812	{
813	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
814	#if defined(CONFIG_SOFTMMU)
815	uint8_t label1_ptr, label2_ptr;
816	#endif
817	#if TARGET_LONG_BITS == 64
818	#if defined(CONFIG_SOFTMMU)
819	uint8_t *label3_ptr;
820	#endif
821	int addr_reg2;
822	#endif
823
824	data_reg = *args++;
825	if (opc == 3)
826	data_reg2 = *args++;
827	else
828	data_reg2 = 0;
829	addr_reg = *args++;
830	#if TARGET_LONG_BITS == 64
831	addr_reg2 = *args++;
832	#endif
833	mem_index = *args;
834
835	s_bits = opc;
836
837	r0 = TCG_REG_EAX;
838	r1 = TCG_REG_EDX;
839
840	#if defined(CONFIG_SOFTMMU)
841	tcg_out_mov(s, r1, addr_reg);
842
843	tcg_out_mov(s, r0, addr_reg);
844
845	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
846	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
847
848	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
849	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
850
851	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
852	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
853
854	#ifndef VBOX
855	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
856	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
857	tcg_out8(s, (5 << 3) \| r1);
858	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
859	#else
860	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
861	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
862	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
863	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
864	#endif
865
866	/* cmp 0(r1), r0 */
867	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
868
869	tcg_out_mov(s, r0, addr_reg);
870
871	#if TARGET_LONG_BITS == 32
872	/* je label1 */
873	tcg_out8(s, 0x70 + JCC_JE);
874	label1_ptr = s->code_ptr;
875	s->code_ptr++;
876	#else
877	/* jne label3 */
878	tcg_out8(s, 0x70 + JCC_JNE);
879	label3_ptr = s->code_ptr;
880	s->code_ptr++;
881
882	/* cmp 4(r1), addr_reg2 */
883	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
884
885	/* je label1 */
886	tcg_out8(s, 0x70 + JCC_JE);
887	label1_ptr = s->code_ptr;
888	s->code_ptr++;
889
890	/* label3: */
891	*label3_ptr = s->code_ptr - label3_ptr - 1;
892	#endif
893
894	/* XXX: move that code at the end of the TB */
895	#if TARGET_LONG_BITS == 32
896	if (opc == 3) {
897	tcg_out_mov(s, TCG_REG_EDX, data_reg);
898	tcg_out_mov(s, TCG_REG_ECX, data_reg2);
899	tcg_out8(s, 0x6a); /* push Ib */
900	tcg_out8(s, mem_index);
901	tcg_out8(s, 0xe8);
902	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
903	(tcg_target_long)s->code_ptr - 4);
904	tcg_out_addi(s, TCG_REG_ESP, 4);
905	} else {
906	switch(opc) {
907	case 0:
908	/* movzbl */
909	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_EDX, data_reg);
910	break;
911	case 1:
912	/* movzwl */
913	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_EDX, data_reg);
914	break;
915	case 2:
916	tcg_out_mov(s, TCG_REG_EDX, data_reg);
917	break;
918	}
919	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
920	tcg_out8(s, 0xe8);
921	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
922	(tcg_target_long)s->code_ptr - 4);
923	}
924	#else
925	if (opc == 3) {
926	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
927	tcg_out8(s, 0x6a); /* push Ib */
928	tcg_out8(s, mem_index);
929	tcg_out_opc(s, 0x50 + data_reg2); /* push */
930	tcg_out_opc(s, 0x50 + data_reg); /* push */
931	tcg_out8(s, 0xe8);
932	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
933	(tcg_target_long)s->code_ptr - 4);
934	tcg_out_addi(s, TCG_REG_ESP, 12);
935	} else {
936	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
937	switch(opc) {
938	case 0:
939	/* movzbl */
940	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_ECX, data_reg);
941	break;
942	case 1:
943	/* movzwl */
944	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_ECX, data_reg);
945	break;
946	case 2:
947	tcg_out_mov(s, TCG_REG_ECX, data_reg);
948	break;
949	}
950	tcg_out8(s, 0x6a); /* push Ib */
951	tcg_out8(s, mem_index);
952	tcg_out8(s, 0xe8);
953	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
954	(tcg_target_long)s->code_ptr - 4);
955	tcg_out_addi(s, TCG_REG_ESP, 4);
956	}
957	#endif
958
959	/* jmp label2 */
960	tcg_out8(s, 0xeb);
961	label2_ptr = s->code_ptr;
962	s->code_ptr++;
963
964	/* label1: */
965	*label1_ptr = s->code_ptr - label1_ptr - 1;
966
967	/* add x(r1), r0 */
968	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
969	offsetof(CPUTLBEntry, addr_write));
970	#else
971	r0 = addr_reg;
972	#endif
973
974	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
975	#ifdef TARGET_WORDS_BIGENDIAN
976	bswap = 1;
977	#else
978	bswap = 0;
979	#endif
980	switch(opc) {
981	case 0:
982	/* movb */
983	tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
984	break;
985	case 1:
986	if (bswap) {
987	tcg_out_mov(s, r1, data_reg);
988	tcg_out8(s, 0x66); /* rolw $8, %ecx */
989	tcg_out_modrm(s, 0xc1, 0, r1);
990	tcg_out8(s, 8);
991	data_reg = r1;
992	}
993	/* movw */
994	tcg_out8(s, 0x66);
995	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
996	break;
997	case 2:
998	if (bswap) {
999	tcg_out_mov(s, r1, data_reg);
1000	/* bswap data_reg */
1001	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1002	data_reg = r1;
1003	}
1004	/* movl */
1005	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1006	break;
1007	case 3:
1008	if (bswap) {
1009	tcg_out_mov(s, r1, data_reg2);
1010	/* bswap data_reg */
1011	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1012	tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1013	tcg_out_mov(s, r1, data_reg);
1014	/* bswap data_reg */
1015	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1016	tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1017	} else {
1018	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1019	tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1020	}
1021	break;
1022	default:
1023	tcg_abort();
1024	}
1025	#else
1026	tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1027	#endif
1028
1029	#if defined(CONFIG_SOFTMMU)
1030	/* label2: */
1031	*label2_ptr = s->code_ptr - label2_ptr - 1;
1032	#endif
1033	}
1034
1035	#ifndef VBOX
1036	static inline void tcg_out_op(TCGContext *s, int opc,
1037	#else /* VBOX */
1038	DECLINLINE(void) tcg_out_op(TCGContext *s, int opc,
1039	#endif /* VBOX */
1040	const TCGArg args, const int const_args)
1041	{
1042	int c;
1043
1044	switch(opc) {
1045	case INDEX_op_exit_tb:
1046	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1047	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1048	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1049	break;
1050	case INDEX_op_goto_tb:
1051	if (s->tb_jmp_offset) {
1052	/* direct jump method */
1053	tcg_out8(s, 0xe9); /* jmp im */
1054	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1055	tcg_out32(s, 0);
1056	} else {
1057	/* indirect jump method */
1058	/* jmp Ev */
1059	tcg_out_modrm_offset(s, 0xff, 4, -1,
1060	(tcg_target_long)(s->tb_next + args[0]));
1061	}
1062	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1063	break;
1064	case INDEX_op_call:
1065	if (const_args[0]) {
1066	tcg_out8(s, 0xe8);
1067	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1068	} else {
1069	tcg_out_modrm(s, 0xff, 2, args[0]);
1070	}
1071	break;
1072	case INDEX_op_jmp:
1073	if (const_args[0]) {
1074	tcg_out8(s, 0xe9);
1075	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1076	} else {
1077	tcg_out_modrm(s, 0xff, 4, args[0]);
1078	}
1079	break;
1080	case INDEX_op_br:
1081	tcg_out_jxx(s, JCC_JMP, args[0]);
1082	break;
1083	case INDEX_op_movi_i32:
1084	tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1085	break;
1086	case INDEX_op_ld8u_i32:
1087	/* movzbl */
1088	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1089	break;
1090	case INDEX_op_ld8s_i32:
1091	/* movsbl */
1092	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1093	break;
1094	case INDEX_op_ld16u_i32:
1095	/* movzwl */
1096	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1097	break;
1098	case INDEX_op_ld16s_i32:
1099	/* movswl */
1100	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1101	break;
1102	case INDEX_op_ld_i32:
1103	/* movl */
1104	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1105	break;
1106	case INDEX_op_st8_i32:
1107	/* movb */
1108	tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1109	break;
1110	case INDEX_op_st16_i32:
1111	/* movw */
1112	tcg_out8(s, 0x66);
1113	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1114	break;
1115	case INDEX_op_st_i32:
1116	/* movl */
1117	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1118	break;
1119	case INDEX_op_sub_i32:
1120	c = ARITH_SUB;
1121	goto gen_arith;
1122	case INDEX_op_and_i32:
1123	c = ARITH_AND;
1124	goto gen_arith;
1125	case INDEX_op_or_i32:
1126	c = ARITH_OR;
1127	goto gen_arith;
1128	case INDEX_op_xor_i32:
1129	c = ARITH_XOR;
1130	goto gen_arith;
1131	case INDEX_op_add_i32:
1132	c = ARITH_ADD;
1133	gen_arith:
1134	if (const_args[2]) {
1135	tgen_arithi(s, c, args[0], args[2]);
1136	} else {
1137	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1138	}
1139	break;
1140	case INDEX_op_mul_i32:
1141	if (const_args[2]) {
1142	int32_t val;
1143	val = args[2];
1144	if (val == (int8_t)val) {
1145	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1146	tcg_out8(s, val);
1147	} else {
1148	tcg_out_modrm(s, 0x69, args[0], args[0]);
1149	tcg_out32(s, val);
1150	}
1151	} else {
1152	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1153	}
1154	break;
1155	case INDEX_op_mulu2_i32:
1156	tcg_out_modrm(s, 0xf7, 4, args[3]);
1157	break;
1158	case INDEX_op_div2_i32:
1159	tcg_out_modrm(s, 0xf7, 7, args[4]);
1160	break;
1161	case INDEX_op_divu2_i32:
1162	tcg_out_modrm(s, 0xf7, 6, args[4]);
1163	break;
1164	case INDEX_op_shl_i32:
1165	c = SHIFT_SHL;
1166	gen_shift32:
1167	if (const_args[2]) {
1168	if (args[2] == 1) {
1169	tcg_out_modrm(s, 0xd1, c, args[0]);
1170	} else {
1171	tcg_out_modrm(s, 0xc1, c, args[0]);
1172	tcg_out8(s, args[2]);
1173	}
1174	} else {
1175	tcg_out_modrm(s, 0xd3, c, args[0]);
1176	}
1177	break;
1178	case INDEX_op_shr_i32:
1179	c = SHIFT_SHR;
1180	goto gen_shift32;
1181	case INDEX_op_sar_i32:
1182	c = SHIFT_SAR;
1183	goto gen_shift32;
1184
1185	case INDEX_op_add2_i32:
1186	if (const_args[4])
1187	tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1188	else
1189	tcg_out_modrm(s, 0x01 \| (ARITH_ADD << 3), args[4], args[0]);
1190	if (const_args[5])
1191	tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1192	else
1193	tcg_out_modrm(s, 0x01 \| (ARITH_ADC << 3), args[5], args[1]);
1194	break;
1195	case INDEX_op_sub2_i32:
1196	if (const_args[4])
1197	tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1198	else
1199	tcg_out_modrm(s, 0x01 \| (ARITH_SUB << 3), args[4], args[0]);
1200	if (const_args[5])
1201	tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1202	else
1203	tcg_out_modrm(s, 0x01 \| (ARITH_SBB << 3), args[5], args[1]);
1204	break;
1205	case INDEX_op_brcond_i32:
1206	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1207	break;
1208	case INDEX_op_brcond2_i32:
1209	tcg_out_brcond2(s, args, const_args);
1210	break;
1211
1212	case INDEX_op_qemu_ld8u:
1213	tcg_out_qemu_ld(s, args, 0);
1214	break;
1215	case INDEX_op_qemu_ld8s:
1216	tcg_out_qemu_ld(s, args, 0 \| 4);
1217	break;
1218	case INDEX_op_qemu_ld16u:
1219	tcg_out_qemu_ld(s, args, 1);
1220	break;
1221	case INDEX_op_qemu_ld16s:
1222	tcg_out_qemu_ld(s, args, 1 \| 4);
1223	break;
1224	case INDEX_op_qemu_ld32u:
1225	tcg_out_qemu_ld(s, args, 2);
1226	break;
1227	case INDEX_op_qemu_ld64:
1228	tcg_out_qemu_ld(s, args, 3);
1229	break;
1230
1231	case INDEX_op_qemu_st8:
1232	tcg_out_qemu_st(s, args, 0);
1233	break;
1234	case INDEX_op_qemu_st16:
1235	tcg_out_qemu_st(s, args, 1);
1236	break;
1237	case INDEX_op_qemu_st32:
1238	tcg_out_qemu_st(s, args, 2);
1239	break;
1240	case INDEX_op_qemu_st64:
1241	tcg_out_qemu_st(s, args, 3);
1242	break;
1243
1244	default:
1245	tcg_abort();
1246	}
1247	}
1248
1249	static const TCGTargetOpDef x86_op_defs[] = {
1250	{ INDEX_op_exit_tb, {"", "" } },
1251	{ INDEX_op_goto_tb, {"", "" } },
1252	{ INDEX_op_call, { "ri", "", } },
1253	{ INDEX_op_jmp, { "ri", ""} },
1254	{ INDEX_op_br, {"", "" } },
1255	{ INDEX_op_mov_i32, { "r", "r" } },
1256	{ INDEX_op_movi_i32, { "r" } },
1257	{ INDEX_op_ld8u_i32, { "r", "r" } },
1258	{ INDEX_op_ld8s_i32, { "r", "r" } },
1259	{ INDEX_op_ld16u_i32, { "r", "r" } },
1260	{ INDEX_op_ld16s_i32, { "r", "r" } },
1261	{ INDEX_op_ld_i32, { "r", "r" } },
1262	{ INDEX_op_st8_i32, { "q", "r" } },
1263	{ INDEX_op_st16_i32, { "r", "r" } },
1264	{ INDEX_op_st_i32, { "r", "r" } },
1265
1266	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1267	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1268	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1269	{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1270	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1271	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1272	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1273	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1274	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1275
1276	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1277	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1278	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1279
1280	{ INDEX_op_brcond_i32, { "r", "ri" } },
1281
1282	{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1283	{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1284	{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1285
1286	#if TARGET_LONG_BITS == 32
1287	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1288	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1289	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1290	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1291	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1292	{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
1293
1294	{ INDEX_op_qemu_st8, { "cb", "L" } },
1295	{ INDEX_op_qemu_st16, { "L", "L" } },
1296	{ INDEX_op_qemu_st32, { "L", "L" } },
1297	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1298	#else
1299	{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1300	{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1301	{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1302	{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1303	{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1304	{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1305
1306	{ INDEX_op_qemu_st8, { "cb", "L", "L" } },
1307	{ INDEX_op_qemu_st16, { "L", "L", "L" } },
1308	{ INDEX_op_qemu_st32, { "L", "L", "L" } },
1309	{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1310	#endif
1311	#ifndef VBOX
1312	{ -1 },
1313	#else
1314	{ -1, {"", "", "", ""} },
1315	#endif
1316	};
1317
1318	static int tcg_target_callee_save_regs[] = {
1319	#ifndef VBOX
1320	/* TCG_REG_EBP, / / currently used for the global env, so no
1321	need to save */
1322	TCG_REG_EBX,
1323	TCG_REG_ESI,
1324	TCG_REG_EDI,
1325	#else
1326	TCG_REG_EBP,
1327	TCG_REG_EBX,
1328	TCG_REG_ESI, /* currently used for the global env, so no
1329	need to save */
1330	TCG_REG_EDI,
1331	#endif
1332	};
1333
1334	/* Generate global QEMU prologue and epilogue code */
1335	void tcg_target_qemu_prologue(TCGContext *s)
1336	{
1337	int i, frame_size, push_size, stack_addend;
1338
1339	/* TB prologue */
1340	/* save all callee saved registers */
1341	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1342	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1343	}
1344	/* reserve some stack space */
1345	push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1346	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1347	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1348	~(TCG_TARGET_STACK_ALIGN - 1);
1349	stack_addend = frame_size - push_size;
1350	tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1351
1352	tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp %eax /
1353
1354	/* TB epilogue */
1355	tb_ret_addr = s->code_ptr;
1356	tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1357	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1358	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1359	}
1360	tcg_out8(s, 0xc3); /* ret */
1361	}
1362
1363	void tcg_target_init(TCGContext *s)
1364	{
1365	/* fail safe */
1366	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1367	tcg_abort();
1368
1369	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1370	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1371	(1 << TCG_REG_EAX) \|
1372	(1 << TCG_REG_EDX) \|
1373	(1 << TCG_REG_ECX));
1374
1375	tcg_regset_clear(s->reserved_regs);
1376	tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1377
1378	tcg_add_target_add_op_defs(x86_op_defs);
1379	}

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source: vbox/trunk/src/recompiler_new/tcg/i386/tcg-target.c@ 14542

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