tcg-target.c@ 17647

Last change on this file since 17647 was 15645, checked in by vboxsync, 16 years ago
tcg-target.c: restored the todo.
File size: 41.4 KB

Line
1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24	/*
25	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
26	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
27	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
28	* a choice of LGPL license versions is made available with the language indicating
29	* that LGPLv2 or any later version may be used, or where a choice of which version
30	* of the LGPL is applied is otherwise unspecified.
31	*/
32	#ifndef NDEBUG
33	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34	"%eax",
35	"%ecx",
36	"%edx",
37	"%ebx",
38	"%esp",
39	"%ebp",
40	"%esi",
41	"%edi",
42	};
43	#endif
44
45	static const int tcg_target_reg_alloc_order[] = {
46	TCG_REG_EAX,
47	TCG_REG_EDX,
48	TCG_REG_ECX,
49	TCG_REG_EBX,
50	TCG_REG_ESI,
51	TCG_REG_EDI,
52	TCG_REG_EBP,
53	};
54
55	static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
56	static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
57
58	static uint8_t *tb_ret_addr;
59
60	static void patch_reloc(uint8_t *code_ptr, int type,
61	tcg_target_long value, tcg_target_long addend)
62	{
63	value += addend;
64	switch(type) {
65	case R_386_32:
66	(uint32_t )code_ptr = value;
67	break;
68	case R_386_PC32:
69	(uint32_t )code_ptr = value - (long)code_ptr;
70	break;
71	default:
72	tcg_abort();
73	}
74	}
75
76	#ifdef VBOX
77	/* emits stack alignment checks for strict builds. */
78	DECLINLINE(void) tcg_gen_stack_alignment_check(TCGContext *s)
79	{
80	# if defined(RT_STRICT) && defined(RT_OS_DARWIN) /** @todo all OSes? */
81	tcg_out8(s, 0xf7); tcg_out8(s, 0xc4); /* test %esp, 1fh */
82	tcg_out32(s, TCG_TARGET_STACK_ALIGN - 1);
83	tcg_out8(s, 0x74); /* jz imm8 */
84	tcg_out8(s, 1); /* $+3 (over int3) */
85	tcg_out8(s, 0xcc); /* int3 */
86	# else
87	NOREF(s);
88	# endif
89	}
90	#endif /* VBOX */
91
92	/* maximum number of register used for input function arguments */
93	#ifndef VBOX
94	static inline int tcg_target_get_call_iarg_regs_count(int flags)
95	#else /* VBOX */
96	DECLINLINE(int) tcg_target_get_call_iarg_regs_count(int flags)
97	#endif /* VBOX */
98	{
99	flags &= TCG_CALL_TYPE_MASK;
100	switch(flags) {
101	case TCG_CALL_TYPE_STD:
102	return 0;
103	case TCG_CALL_TYPE_REGPARM_1:
104	case TCG_CALL_TYPE_REGPARM_2:
105	case TCG_CALL_TYPE_REGPARM:
106	return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
107	default:
108	tcg_abort();
109	}
110	}
111
112	/* parse target specific constraints */
113	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
114	{
115	const char *ct_str;
116
117	ct_str = *pct_str;
118	switch(ct_str[0]) {
119	case 'a':
120	ct->ct \|= TCG_CT_REG;
121	tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
122	break;
123	case 'b':
124	ct->ct \|= TCG_CT_REG;
125	tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
126	break;
127	case 'c':
128	ct->ct \|= TCG_CT_REG;
129	tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
130	break;
131	case 'd':
132	ct->ct \|= TCG_CT_REG;
133	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
134	break;
135	case 'S':
136	ct->ct \|= TCG_CT_REG;
137	tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
138	break;
139	case 'D':
140	ct->ct \|= TCG_CT_REG;
141	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
142	break;
143	case 'q':
144	ct->ct \|= TCG_CT_REG;
145	tcg_regset_set32(ct->u.regs, 0, 0xf);
146	break;
147	case 'r':
148	ct->ct \|= TCG_CT_REG;
149	tcg_regset_set32(ct->u.regs, 0, 0xff);
150	break;
151
152	/* qemu_ld/st address constraint */
153	case 'L':
154	ct->ct \|= TCG_CT_REG;
155	tcg_regset_set32(ct->u.regs, 0, 0xff);
156	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
157	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
158	break;
159	default:
160	return -1;
161	}
162	ct_str++;
163	*pct_str = ct_str;
164	return 0;
165	}
166
167	/* test if a constant matches the constraint */
168	#ifndef VBOX
169	static inline int tcg_target_const_match(tcg_target_long val,
170	#else /* VBOX */
171	DECLINLINE(int) tcg_target_const_match(tcg_target_long val,
172	#endif /* VBOX */
173	const TCGArgConstraint *arg_ct)
174	{
175	int ct;
176	ct = arg_ct->ct;
177	if (ct & TCG_CT_CONST)
178	return 1;
179	else
180	return 0;
181	}
182
183	#define ARITH_ADD 0
184	#define ARITH_OR 1
185	#define ARITH_ADC 2
186	#define ARITH_SBB 3
187	#define ARITH_AND 4
188	#define ARITH_SUB 5
189	#define ARITH_XOR 6
190	#define ARITH_CMP 7
191
192	#define SHIFT_SHL 4
193	#define SHIFT_SHR 5
194	#define SHIFT_SAR 7
195
196	#define JCC_JMP (-1)
197	#define JCC_JO 0x0
198	#define JCC_JNO 0x1
199	#define JCC_JB 0x2
200	#define JCC_JAE 0x3
201	#define JCC_JE 0x4
202	#define JCC_JNE 0x5
203	#define JCC_JBE 0x6
204	#define JCC_JA 0x7
205	#define JCC_JS 0x8
206	#define JCC_JNS 0x9
207	#define JCC_JP 0xa
208	#define JCC_JNP 0xb
209	#define JCC_JL 0xc
210	#define JCC_JGE 0xd
211	#define JCC_JLE 0xe
212	#define JCC_JG 0xf
213
214	#define P_EXT 0x100 /* 0x0f opcode prefix */
215
216	#if !defined(VBOX) \|\| !defined(_MSC_VER)
217	static const uint8_t tcg_cond_to_jcc[10] = {
218	[TCG_COND_EQ] = JCC_JE,
219	[TCG_COND_NE] = JCC_JNE,
220	[TCG_COND_LT] = JCC_JL,
221	[TCG_COND_GE] = JCC_JGE,
222	[TCG_COND_LE] = JCC_JLE,
223	[TCG_COND_GT] = JCC_JG,
224	[TCG_COND_LTU] = JCC_JB,
225	[TCG_COND_GEU] = JCC_JAE,
226	[TCG_COND_LEU] = JCC_JBE,
227	[TCG_COND_GTU] = JCC_JA,
228	};
229	#else
230	/* Fortunately, ordering is right */
231	static const uint8_t tcg_cond_to_jcc[10] = {
232	JCC_JE,
233	JCC_JNE,
234	JCC_JL,
235	JCC_JGE,
236	JCC_JLE,
237	JCC_JG,
238	JCC_JB,
239	JCC_JAE,
240	JCC_JBE,
241	JCC_JA,
242	};
243	#endif
244
245	#ifndef VBOX
246	static inline void tcg_out_opc(TCGContext *s, int opc)
247	#else /* VBOX */
248	DECLINLINE(void) tcg_out_opc(TCGContext *s, int opc)
249	#endif /* VBOX */
250	{
251	if (opc & P_EXT)
252	tcg_out8(s, 0x0f);
253	tcg_out8(s, opc);
254	}
255
256	#ifndef VBOX
257	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
258	#else /* VBOX */
259	DECLINLINE(void) tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
260	#endif /* VBOX */
261	{
262	tcg_out_opc(s, opc);
263	tcg_out8(s, 0xc0 \| (r << 3) \| rm);
264	}
265
266	/* rm == -1 means no register index */
267	#ifndef VBOX
268	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
269	#else /* VBOX */
270	DECLINLINE(void) tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
271	#endif /* VBOX */
272	int32_t offset)
273	{
274	tcg_out_opc(s, opc);
275	if (rm == -1) {
276	tcg_out8(s, 0x05 \| (r << 3));
277	tcg_out32(s, offset);
278	} else if (offset == 0 && rm != TCG_REG_EBP) {
279	if (rm == TCG_REG_ESP) {
280	tcg_out8(s, 0x04 \| (r << 3));
281	tcg_out8(s, 0x24);
282	} else {
283	tcg_out8(s, 0x00 \| (r << 3) \| rm);
284	}
285	} else if ((int8_t)offset == offset) {
286	if (rm == TCG_REG_ESP) {
287	tcg_out8(s, 0x44 \| (r << 3));
288	tcg_out8(s, 0x24);
289	} else {
290	tcg_out8(s, 0x40 \| (r << 3) \| rm);
291	}
292	tcg_out8(s, offset);
293	} else {
294	if (rm == TCG_REG_ESP) {
295	tcg_out8(s, 0x84 \| (r << 3));
296	tcg_out8(s, 0x24);
297	} else {
298	tcg_out8(s, 0x80 \| (r << 3) \| rm);
299	}
300	tcg_out32(s, offset);
301	}
302	}
303
304	#ifndef VBOX
305	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
306	#else /* VBOX */
307	DECLINLINE(void) tcg_out_mov(TCGContext *s, int ret, int arg)
308	#endif /* VBOX */
309	{
310	if (arg != ret)
311	tcg_out_modrm(s, 0x8b, ret, arg);
312	}
313
314	#ifndef VBOX
315	static inline void tcg_out_movi(TCGContext *s, TCGType type,
316	#else /* VBOX */
317	DECLINLINE(void) tcg_out_movi(TCGContext *s, TCGType type,
318	#endif /* VBOX */
319	int ret, int32_t arg)
320	{
321	if (arg == 0) {
322	/* xor r0,r0 */
323	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret);
324	} else {
325	tcg_out8(s, 0xb8 + ret);
326	tcg_out32(s, arg);
327	}
328	}
329
330	#ifndef VBOX
331	static inline void tcg_out_push(TCGContext *s, int reg)
332	#else /* VBOX */
333	DECLINLINE(void) tcg_out_push(TCGContext *s, int reg)
334	#endif /* VBOX */
335	{
336	tcg_out_opc(s, 0x50 + reg);
337	}
338
339	#ifndef VBOX
340	static inline void tcg_out_pop(TCGContext *s, int reg)
341	#else /* VBOX */
342	DECLINLINE(void) tcg_out_pop(TCGContext *s, int reg)
343	#endif /* VBOX */
344	{
345	tcg_out_opc(s, 0x58 + reg);
346	}
347
348	#ifndef VBOX
349	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
350	#else /* VBOX */
351	DECLINLINE(void) tcg_out_ld(TCGContext *s, TCGType type, int ret,
352	#endif /* VBOX */
353	int arg1, tcg_target_long arg2)
354	{
355	/* movl */
356	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
357	}
358
359	#ifndef VBOX
360	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
361	#else /* VBOX */
362	DECLINLINE(void) tcg_out_st(TCGContext *s, TCGType type, int arg,
363	#endif /* VBOX */
364	int arg1, tcg_target_long arg2)
365	{
366	/* movl */
367	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
368	}
369
370	#ifndef VBOX
371	static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
372	#else /* VBOX */
373	DECLINLINE(void) tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
374	#endif /* VBOX */
375	{
376	if (val == (int8_t)val) {
377	tcg_out_modrm(s, 0x83, c, r0);
378	tcg_out8(s, val);
379	} else {
380	tcg_out_modrm(s, 0x81, c, r0);
381	tcg_out32(s, val);
382	}
383	}
384
385	void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
386	{
387	if (val != 0)
388	tgen_arithi(s, ARITH_ADD, reg, val);
389	}
390
391	#ifdef VBOX
392	void tcg_out_subi(TCGContext *s, int reg, tcg_target_long val)
393	{
394	if (val != 0)
395	tgen_arithi(s, ARITH_SUB, reg, val);
396	}
397	#endif
398
399	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
400	{
401	int32_t val, val1;
402	TCGLabel *l = &s->labels[label_index];
403
404	if (l->has_value) {
405	val = l->u.value - (tcg_target_long)s->code_ptr;
406	val1 = val - 2;
407	if ((int8_t)val1 == val1) {
408	if (opc == -1)
409	tcg_out8(s, 0xeb);
410	else
411	tcg_out8(s, 0x70 + opc);
412	tcg_out8(s, val1);
413	} else {
414	if (opc == -1) {
415	tcg_out8(s, 0xe9);
416	tcg_out32(s, val - 5);
417	} else {
418	tcg_out8(s, 0x0f);
419	tcg_out8(s, 0x80 + opc);
420	tcg_out32(s, val - 6);
421	}
422	}
423	} else {
424	if (opc == -1) {
425	tcg_out8(s, 0xe9);
426	} else {
427	tcg_out8(s, 0x0f);
428	tcg_out8(s, 0x80 + opc);
429	}
430	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
431	s->code_ptr += 4;
432	}
433	}
434
435	static void tcg_out_brcond(TCGContext *s, int cond,
436	TCGArg arg1, TCGArg arg2, int const_arg2,
437	int label_index)
438	{
439	if (const_arg2) {
440	if (arg2 == 0) {
441	/* test r, r */
442	tcg_out_modrm(s, 0x85, arg1, arg1);
443	} else {
444	tgen_arithi(s, ARITH_CMP, arg1, arg2);
445	}
446	} else {
447	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3), arg2, arg1);
448	}
449	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
450	}
451
452	#ifdef VBOX
453	DECLINLINE(void)
454	tcg_out_long_call(TCGContext s, void dst)
455	{
456	intptr_t disp;
457	# ifdef VBOX
458	tcg_gen_stack_alignment_check(s);
459	# endif
460	disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
461	tcg_out8(s, 0xe8); /* call disp32 */
462	tcg_out32(s, disp); /* disp32 */
463	}
464	DECLINLINE(void)
465	tcg_out_long_jmp(TCGContext s, void dst)
466	{
467	intptr_t disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
468	tcg_out8(s, 0xe9); /* jmp disp32 */
469	tcg_out32(s, disp); /* disp32 */
470	}
471	#endif /* VBOX */
472
473
474	/* XXX: we implement it at the target level to avoid having to
475	handle cross basic blocks temporaries */
476	static void tcg_out_brcond2(TCGContext *s,
477	const TCGArg args, const int const_args)
478	{
479	int label_next;
480	label_next = gen_new_label();
481	switch(args[4]) {
482	case TCG_COND_EQ:
483	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
484	tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
485	break;
486	case TCG_COND_NE:
487	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
488	tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
489	break;
490	case TCG_COND_LT:
491	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
492	tcg_out_jxx(s, JCC_JNE, label_next);
493	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
494	break;
495	case TCG_COND_LE:
496	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
497	tcg_out_jxx(s, JCC_JNE, label_next);
498	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
499	break;
500	case TCG_COND_GT:
501	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
502	tcg_out_jxx(s, JCC_JNE, label_next);
503	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
504	break;
505	case TCG_COND_GE:
506	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
507	tcg_out_jxx(s, JCC_JNE, label_next);
508	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
509	break;
510	case TCG_COND_LTU:
511	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
512	tcg_out_jxx(s, JCC_JNE, label_next);
513	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
514	break;
515	case TCG_COND_LEU:
516	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
517	tcg_out_jxx(s, JCC_JNE, label_next);
518	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
519	break;
520	case TCG_COND_GTU:
521	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
522	tcg_out_jxx(s, JCC_JNE, label_next);
523	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
524	break;
525	case TCG_COND_GEU:
526	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
527	tcg_out_jxx(s, JCC_JNE, label_next);
528	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
529	break;
530	default:
531	tcg_abort();
532	}
533	tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
534	}
535
536	#if defined(CONFIG_SOFTMMU)
537
538	#include "../../softmmu_defs.h"
539
540	static void *qemu_ld_helpers[4] = {
541	__ldb_mmu,
542	__ldw_mmu,
543	__ldl_mmu,
544	__ldq_mmu,
545	};
546
547	static void *qemu_st_helpers[4] = {
548	__stb_mmu,
549	__stw_mmu,
550	__stl_mmu,
551	__stq_mmu,
552	};
553	#endif
554
555	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
556	static void *vbox_ld_helpers[] = {
557	__ldub_vbox_phys,
558	__lduw_vbox_phys,
559	__ldul_vbox_phys,
560	__ldq_vbox_phys,
561	__ldb_vbox_phys,
562	__ldw_vbox_phys,
563	__ldl_vbox_phys,
564	__ldq_vbox_phys,
565	};
566
567	static void *vbox_st_helpers[] = {
568	__stb_vbox_phys,
569	__stw_vbox_phys,
570	__stl_vbox_phys,
571	__stq_vbox_phys
572	};
573
574	static void tcg_out_vbox_phys_read(TCGContext *s, int index,
575	int addr_reg,
576	int data_reg, int data_reg2)
577	{
578	int useReg2 = ((index & 3) == 3);
579
580	/** @todo: should we make phys addess accessors fastcalls - probably not a big deal */
581	/* out parameter (address), note that phys address is always 64-bit */
582	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
583
584	#if 0
585	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
586	tcg_out_push(s, addr_reg);
587	#else
588	/* mov addr_reg, %eax */
589	tcg_out_mov(s, TCG_REG_EAX, addr_reg);
590	#endif
591
592	tcg_out_long_call(s, vbox_ld_helpers[index]);
593
594	/* mov %eax, data_reg */
595	tcg_out_mov(s, data_reg, TCG_REG_EAX);
596
597	/* returned 64-bit value */
598	if (useReg2)
599	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
600	}
601
602	static void tcg_out_vbox_phys_write(TCGContext *s, int index,
603	int addr_reg,
604	int val_reg, int val_reg2) {
605	int useReg2 = ((index & 3) == 3);
606
607	#if 0
608	/* out parameter (value2) */
609	if (useReg2)
610	tcg_out_push(s, val_reg2);
611	/* out parameter (value) */
612	tcg_out_push(s, val_reg);
613	/* out parameter (address), note that phys address is always 64-bit */
614	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
615	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
616	tcg_out_push(s, addr_reg);
617	#else
618	Assert(val_reg != TCG_REG_EAX && (!useReg2 \|\| (val_reg2 != TCG_REG_EAX)));
619	/* mov addr_reg, %eax */
620	tcg_out_mov(s, TCG_REG_EAX, addr_reg);
621	Assert(!useReg2 \|\| (val_reg2 != TCG_REG_EDX));
622	/* mov val_reg, %edx */
623	tcg_out_mov(s, TCG_REG_EDX, val_reg);
624	if (useReg2)
625	tcg_out_mov(s, TCG_REG_ECX, val_reg2);
626
627	#endif
628	/* call it */
629	tcg_out_long_call(s, vbox_st_helpers[index]);
630
631	/* clean stack after us */
632	#if 0
633	tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
634	# endif
635	}
636
637	#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
638
639	/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
640	EAX. It will be useful once fixed registers globals are less
641	common. */
642	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
643	int opc)
644	{
645	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
646	#if defined(CONFIG_SOFTMMU)
647	uint8_t label1_ptr, label2_ptr;
648	#endif
649	#if TARGET_LONG_BITS == 64
650	#if defined(CONFIG_SOFTMMU)
651	uint8_t *label3_ptr;
652	#endif
653	int addr_reg2;
654	#endif
655
656	data_reg = *args++;
657	if (opc == 3)
658	data_reg2 = *args++;
659	else
660	data_reg2 = 0;
661	addr_reg = *args++;
662	#if TARGET_LONG_BITS == 64
663	addr_reg2 = *args++;
664	#endif
665	mem_index = *args;
666	s_bits = opc & 3;
667
668	r0 = TCG_REG_EAX;
669	r1 = TCG_REG_EDX;
670
671	#if defined(CONFIG_SOFTMMU)
672	tcg_out_mov(s, r1, addr_reg);
673
674	tcg_out_mov(s, r0, addr_reg);
675
676	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
677	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
678
679	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
680	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
681
682	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
683	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
684
685	#ifndef VBOX
686	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
687	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
688	tcg_out8(s, (5 << 3) \| r1);
689	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
690	#else
691	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
692	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
693	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
694	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
695	#endif
696
697	/* cmp 0(r1), r0 */
698	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
699
700	tcg_out_mov(s, r0, addr_reg);
701
702	#if TARGET_LONG_BITS == 32
703	/* je label1 */
704	tcg_out8(s, 0x70 + JCC_JE);
705	label1_ptr = s->code_ptr;
706	s->code_ptr++;
707	#else
708	/* jne label3 */
709	tcg_out8(s, 0x70 + JCC_JNE);
710	label3_ptr = s->code_ptr;
711	s->code_ptr++;
712
713	/* cmp 4(r1), addr_reg2 */
714	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
715
716	/* je label1 */
717	tcg_out8(s, 0x70 + JCC_JE);
718	label1_ptr = s->code_ptr;
719	s->code_ptr++;
720
721	/* label3: */
722	*label3_ptr = s->code_ptr - label3_ptr - 1;
723	#endif
724
725	/* XXX: move that code at the end of the TB */
726	#if TARGET_LONG_BITS == 32
727	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
728	#else
729	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
730	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
731	#endif
732	#ifdef VBOX
733	tcg_gen_stack_alignment_check(s);
734	#endif
735	tcg_out8(s, 0xe8);
736	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
737	(tcg_target_long)s->code_ptr - 4);
738
739	switch(opc) {
740	case 0 \| 4:
741	/* movsbl */
742	tcg_out_modrm(s, 0xbe \| P_EXT, data_reg, TCG_REG_EAX);
743	break;
744	case 1 \| 4:
745	/* movswl */
746	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, TCG_REG_EAX);
747	break;
748	case 0:
749	case 1:
750	case 2:
751	default:
752	tcg_out_mov(s, data_reg, TCG_REG_EAX);
753	break;
754	case 3:
755	if (data_reg == TCG_REG_EDX) {
756	tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
757	tcg_out_mov(s, data_reg2, TCG_REG_EAX);
758	} else {
759	tcg_out_mov(s, data_reg, TCG_REG_EAX);
760	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
761	}
762	break;
763	}
764
765	/* jmp label2 */
766	tcg_out8(s, 0xeb);
767	label2_ptr = s->code_ptr;
768	s->code_ptr++;
769
770	/* label1: */
771	*label1_ptr = s->code_ptr - label1_ptr - 1;
772
773	/* add x(r1), r0 */
774	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
775	offsetof(CPUTLBEntry, addr_read));
776	#else
777	r0 = addr_reg;
778	#endif
779
780	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
781	#ifdef TARGET_WORDS_BIGENDIAN
782	bswap = 1;
783	#else
784	bswap = 0;
785	#endif
786	switch(opc) {
787	case 0:
788	/* movzbl */
789	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
790	break;
791	case 0 \| 4:
792	/* movsbl */
793	tcg_out_modrm_offset(s, 0xbe \| P_EXT, data_reg, r0, 0);
794	break;
795	case 1:
796	/* movzwl */
797	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
798	if (bswap) {
799	/* rolw $8, data_reg */
800	tcg_out8(s, 0x66);
801	tcg_out_modrm(s, 0xc1, 0, data_reg);
802	tcg_out8(s, 8);
803	}
804	break;
805	case 1 \| 4:
806	/* movswl */
807	tcg_out_modrm_offset(s, 0xbf \| P_EXT, data_reg, r0, 0);
808	if (bswap) {
809	/* rolw $8, data_reg */
810	tcg_out8(s, 0x66);
811	tcg_out_modrm(s, 0xc1, 0, data_reg);
812	tcg_out8(s, 8);
813
814	/* movswl data_reg, data_reg */
815	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, data_reg);
816	}
817	break;
818	case 2:
819	/* movl (r0), data_reg */
820	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
821	if (bswap) {
822	/* bswap */
823	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
824	}
825	break;
826	case 3:
827	/* XXX: could be nicer */
828	if (r0 == data_reg) {
829	r1 = TCG_REG_EDX;
830	if (r1 == data_reg)
831	r1 = TCG_REG_EAX;
832	tcg_out_mov(s, r1, r0);
833	r0 = r1;
834	}
835	if (!bswap) {
836	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
837	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
838	} else {
839	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
840	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
841
842	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
843	/* bswap */
844	tcg_out_opc(s, (0xc8 + data_reg2) \| P_EXT);
845	}
846	break;
847	default:
848	tcg_abort();
849	}
850	#else /* VBOX */
851	tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
852	#endif
853
854
855	#if defined(CONFIG_SOFTMMU)
856	/* label2: */
857	*label2_ptr = s->code_ptr - label2_ptr - 1;
858	# ifdef VBOX
859	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
860	# endif
861	#endif
862	}
863
864
865	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
866	int opc)
867	{
868	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
869	#if defined(CONFIG_SOFTMMU)
870	uint8_t label1_ptr, label2_ptr;
871	#endif
872	#if TARGET_LONG_BITS == 64
873	#if defined(CONFIG_SOFTMMU)
874	uint8_t *label3_ptr;
875	#endif
876	int addr_reg2;
877	#endif
878	#ifdef VBOX
879	# ifdef RT_OS_DARWIN
880	int bias1 = 12, bias3 = 4;/** @todo TCG_TARGET_STACK_ALIGN. */
881	# else
882	int bias1 = 0, bias3 = 0;
883	# endif
884	#endif
885
886	data_reg = *args++;
887	if (opc == 3)
888	data_reg2 = *args++;
889	else
890	data_reg2 = 0;
891	addr_reg = *args++;
892	#if TARGET_LONG_BITS == 64
893	addr_reg2 = *args++;
894	#endif
895	mem_index = *args;
896
897	s_bits = opc;
898
899	r0 = TCG_REG_EAX;
900	r1 = TCG_REG_EDX;
901
902	#if defined(CONFIG_SOFTMMU)
903	tcg_out_mov(s, r1, addr_reg);
904
905	tcg_out_mov(s, r0, addr_reg);
906
907	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
908	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
909
910	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
911	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
912
913	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
914	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
915
916	#ifndef VBOX
917	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
918	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
919	tcg_out8(s, (5 << 3) \| r1);
920	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
921	#else
922	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
923	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
924	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
925	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
926	#endif
927
928	/* cmp 0(r1), r0 */
929	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
930
931	tcg_out_mov(s, r0, addr_reg);
932
933	#if TARGET_LONG_BITS == 32
934	/* je label1 */
935	tcg_out8(s, 0x70 + JCC_JE);
936	label1_ptr = s->code_ptr;
937	s->code_ptr++;
938	#else
939	/* jne label3 */
940	tcg_out8(s, 0x70 + JCC_JNE);
941	label3_ptr = s->code_ptr;
942	s->code_ptr++;
943
944	/* cmp 4(r1), addr_reg2 */
945	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
946
947	/* je label1 */
948	tcg_out8(s, 0x70 + JCC_JE);
949	label1_ptr = s->code_ptr;
950	s->code_ptr++;
951
952	/* label3: */
953	*label3_ptr = s->code_ptr - label3_ptr - 1;
954	#endif
955
956	/* XXX: move that code at the end of the TB */
957	#if TARGET_LONG_BITS == 32
958	if (opc == 3) {
959	tcg_out_mov(s, TCG_REG_EDX, data_reg);
960	tcg_out_mov(s, TCG_REG_ECX, data_reg2);
961	#ifdef VBOX
962	tcg_out_subi(s, TCG_REG_ESP, bias1);
963	#endif
964	tcg_out8(s, 0x6a); /* push Ib */
965	tcg_out8(s, mem_index);
966	# ifdef VBOX
967	tcg_gen_stack_alignment_check(s);
968	# endif
969	tcg_out8(s, 0xe8);
970	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
971	(tcg_target_long)s->code_ptr - 4);
972	#ifdef VBOX
973	tcg_out_addi(s, TCG_REG_ESP, 4+bias1);
974	#else
975	tcg_out_addi(s, TCG_REG_ESP, 4);
976	#endif
977	} else {
978	switch(opc) {
979	case 0:
980	/* movzbl */
981	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_EDX, data_reg);
982	break;
983	case 1:
984	/* movzwl */
985	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_EDX, data_reg);
986	break;
987	case 2:
988	tcg_out_mov(s, TCG_REG_EDX, data_reg);
989	break;
990	}
991	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
992	# ifdef VBOX
993	tcg_gen_stack_alignment_check(s);
994	# endif
995	tcg_out8(s, 0xe8);
996	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
997	(tcg_target_long)s->code_ptr - 4);
998	}
999	#else
1000	if (opc == 3) {
1001	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
1002	# ifdef VBOX
1003	tcg_out_subi(s, TCG_REG_ESP, bias3);
1004	# endif
1005	tcg_out8(s, 0x6a); /* push Ib */
1006	tcg_out8(s, mem_index);
1007	tcg_out_opc(s, 0x50 + data_reg2); /* push */
1008	tcg_out_opc(s, 0x50 + data_reg); /* push */
1009	# ifdef VBOX
1010	tcg_gen_stack_alignment_check(s);
1011	# endif
1012	tcg_out8(s, 0xe8);
1013	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
1014	(tcg_target_long)s->code_ptr - 4);
1015	#ifdef VBOX
1016	tcg_out_addi(s, TCG_REG_ESP, 12+bias3);
1017	#else
1018	tcg_out_addi(s, TCG_REG_ESP, 12);
1019	#endif
1020	} else {
1021	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
1022	switch(opc) {
1023	case 0:
1024	/* movzbl */
1025	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_ECX, data_reg);
1026	break;
1027	case 1:
1028	/* movzwl */
1029	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_ECX, data_reg);
1030	break;
1031	case 2:
1032	tcg_out_mov(s, TCG_REG_ECX, data_reg);
1033	break;
1034	}
1035	# ifdef VBOX
1036	tcg_out_subi(s, TCG_REG_ESP, bias1);
1037	# endif
1038	tcg_out8(s, 0x6a); /* push Ib */
1039	tcg_out8(s, mem_index);
1040	# ifdef VBOX
1041	tcg_gen_stack_alignment_check(s);
1042	# endif
1043
1044	tcg_out8(s, 0xe8);
1045	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
1046	(tcg_target_long)s->code_ptr - 4);
1047	# if defined(VBOX)
1048	tcg_out_addi(s, TCG_REG_ESP, 4 + bias1);
1049	# else
1050	tcg_out_addi(s, TCG_REG_ESP, 4);
1051	# endif
1052	}
1053	#endif
1054
1055	/* jmp label2 */
1056	tcg_out8(s, 0xeb);
1057	label2_ptr = s->code_ptr;
1058	s->code_ptr++;
1059
1060	/* label1: */
1061	*label1_ptr = s->code_ptr - label1_ptr - 1;
1062
1063	/* add x(r1), r0 */
1064	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
1065	offsetof(CPUTLBEntry, addr_write));
1066	#else
1067	r0 = addr_reg;
1068	#endif
1069
1070	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
1071	#ifdef TARGET_WORDS_BIGENDIAN
1072	bswap = 1;
1073	#else
1074	bswap = 0;
1075	#endif
1076	switch(opc) {
1077	case 0:
1078	/* movb */
1079	tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
1080	break;
1081	case 1:
1082	if (bswap) {
1083	tcg_out_mov(s, r1, data_reg);
1084	tcg_out8(s, 0x66); /* rolw $8, %ecx */
1085	tcg_out_modrm(s, 0xc1, 0, r1);
1086	tcg_out8(s, 8);
1087	data_reg = r1;
1088	}
1089	/* movw */
1090	tcg_out8(s, 0x66);
1091	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1092	break;
1093	case 2:
1094	if (bswap) {
1095	tcg_out_mov(s, r1, data_reg);
1096	/* bswap data_reg */
1097	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1098	data_reg = r1;
1099	}
1100	/* movl */
1101	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1102	break;
1103	case 3:
1104	if (bswap) {
1105	tcg_out_mov(s, r1, data_reg2);
1106	/* bswap data_reg */
1107	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1108	tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1109	tcg_out_mov(s, r1, data_reg);
1110	/* bswap data_reg */
1111	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1112	tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1113	} else {
1114	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1115	tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1116	}
1117	break;
1118	default:
1119	tcg_abort();
1120	}
1121	#else
1122	tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1123	#endif
1124
1125	#if defined(CONFIG_SOFTMMU)
1126	/* label2: */
1127	*label2_ptr = s->code_ptr - label2_ptr - 1;
1128	# ifdef VBOX
1129	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
1130	# endif
1131	#endif
1132	}
1133
1134	#ifndef VBOX
1135	static inline void tcg_out_op(TCGContext *s, int opc,
1136	#else /* VBOX */
1137	DECLINLINE(void) tcg_out_op(TCGContext *s, int opc,
1138	#endif /* VBOX */
1139	const TCGArg args, const int const_args)
1140	{
1141	int c;
1142
1143	switch(opc) {
1144	case INDEX_op_exit_tb:
1145	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1146	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1147	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1148	break;
1149	case INDEX_op_goto_tb:
1150	if (s->tb_jmp_offset) {
1151	/* direct jump method */
1152	tcg_out8(s, 0xe9); /* jmp im */
1153	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1154	tcg_out32(s, 0);
1155	} else {
1156	/* indirect jump method */
1157	/* jmp Ev */
1158	tcg_out_modrm_offset(s, 0xff, 4, -1,
1159	(tcg_target_long)(s->tb_next + args[0]));
1160	}
1161	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1162	break;
1163	case INDEX_op_call:
1164	#ifdef VBOX
1165	tcg_gen_stack_alignment_check(s);
1166	#endif
1167	if (const_args[0]) {
1168	tcg_out8(s, 0xe8);
1169	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1170	} else {
1171	tcg_out_modrm(s, 0xff, 2, args[0]);
1172	}
1173	break;
1174	case INDEX_op_jmp:
1175	if (const_args[0]) {
1176	tcg_out8(s, 0xe9);
1177	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1178	} else {
1179	tcg_out_modrm(s, 0xff, 4, args[0]);
1180	}
1181	break;
1182	case INDEX_op_br:
1183	tcg_out_jxx(s, JCC_JMP, args[0]);
1184	break;
1185	case INDEX_op_movi_i32:
1186	tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1187	break;
1188	case INDEX_op_ld8u_i32:
1189	/* movzbl */
1190	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1191	break;
1192	case INDEX_op_ld8s_i32:
1193	/* movsbl */
1194	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1195	break;
1196	case INDEX_op_ld16u_i32:
1197	/* movzwl */
1198	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1199	break;
1200	case INDEX_op_ld16s_i32:
1201	/* movswl */
1202	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1203	break;
1204	case INDEX_op_ld_i32:
1205	/* movl */
1206	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1207	break;
1208	case INDEX_op_st8_i32:
1209	/* movb */
1210	tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1211	break;
1212	case INDEX_op_st16_i32:
1213	/* movw */
1214	tcg_out8(s, 0x66);
1215	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1216	break;
1217	case INDEX_op_st_i32:
1218	/* movl */
1219	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1220	break;
1221	case INDEX_op_sub_i32:
1222	c = ARITH_SUB;
1223	goto gen_arith;
1224	case INDEX_op_and_i32:
1225	c = ARITH_AND;
1226	goto gen_arith;
1227	case INDEX_op_or_i32:
1228	c = ARITH_OR;
1229	goto gen_arith;
1230	case INDEX_op_xor_i32:
1231	c = ARITH_XOR;
1232	goto gen_arith;
1233	case INDEX_op_add_i32:
1234	c = ARITH_ADD;
1235	gen_arith:
1236	if (const_args[2]) {
1237	tgen_arithi(s, c, args[0], args[2]);
1238	} else {
1239	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1240	}
1241	break;
1242	case INDEX_op_mul_i32:
1243	if (const_args[2]) {
1244	int32_t val;
1245	val = args[2];
1246	if (val == (int8_t)val) {
1247	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1248	tcg_out8(s, val);
1249	} else {
1250	tcg_out_modrm(s, 0x69, args[0], args[0]);
1251	tcg_out32(s, val);
1252	}
1253	} else {
1254	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1255	}
1256	break;
1257	case INDEX_op_mulu2_i32:
1258	tcg_out_modrm(s, 0xf7, 4, args[3]);
1259	break;
1260	case INDEX_op_div2_i32:
1261	tcg_out_modrm(s, 0xf7, 7, args[4]);
1262	break;
1263	case INDEX_op_divu2_i32:
1264	tcg_out_modrm(s, 0xf7, 6, args[4]);
1265	break;
1266	case INDEX_op_shl_i32:
1267	c = SHIFT_SHL;
1268	gen_shift32:
1269	if (const_args[2]) {
1270	if (args[2] == 1) {
1271	tcg_out_modrm(s, 0xd1, c, args[0]);
1272	} else {
1273	tcg_out_modrm(s, 0xc1, c, args[0]);
1274	tcg_out8(s, args[2]);
1275	}
1276	} else {
1277	tcg_out_modrm(s, 0xd3, c, args[0]);
1278	}
1279	break;
1280	case INDEX_op_shr_i32:
1281	c = SHIFT_SHR;
1282	goto gen_shift32;
1283	case INDEX_op_sar_i32:
1284	c = SHIFT_SAR;
1285	goto gen_shift32;
1286
1287	case INDEX_op_add2_i32:
1288	if (const_args[4])
1289	tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1290	else
1291	tcg_out_modrm(s, 0x01 \| (ARITH_ADD << 3), args[4], args[0]);
1292	if (const_args[5])
1293	tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1294	else
1295	tcg_out_modrm(s, 0x01 \| (ARITH_ADC << 3), args[5], args[1]);
1296	break;
1297	case INDEX_op_sub2_i32:
1298	if (const_args[4])
1299	tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1300	else
1301	tcg_out_modrm(s, 0x01 \| (ARITH_SUB << 3), args[4], args[0]);
1302	if (const_args[5])
1303	tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1304	else
1305	tcg_out_modrm(s, 0x01 \| (ARITH_SBB << 3), args[5], args[1]);
1306	break;
1307	case INDEX_op_brcond_i32:
1308	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1309	break;
1310	case INDEX_op_brcond2_i32:
1311	tcg_out_brcond2(s, args, const_args);
1312	break;
1313
1314	case INDEX_op_qemu_ld8u:
1315	tcg_out_qemu_ld(s, args, 0);
1316	break;
1317	case INDEX_op_qemu_ld8s:
1318	tcg_out_qemu_ld(s, args, 0 \| 4);
1319	break;
1320	case INDEX_op_qemu_ld16u:
1321	tcg_out_qemu_ld(s, args, 1);
1322	break;
1323	case INDEX_op_qemu_ld16s:
1324	tcg_out_qemu_ld(s, args, 1 \| 4);
1325	break;
1326	case INDEX_op_qemu_ld32u:
1327	tcg_out_qemu_ld(s, args, 2);
1328	break;
1329	case INDEX_op_qemu_ld64:
1330	tcg_out_qemu_ld(s, args, 3);
1331	break;
1332
1333	case INDEX_op_qemu_st8:
1334	tcg_out_qemu_st(s, args, 0);
1335	break;
1336	case INDEX_op_qemu_st16:
1337	tcg_out_qemu_st(s, args, 1);
1338	break;
1339	case INDEX_op_qemu_st32:
1340	tcg_out_qemu_st(s, args, 2);
1341	break;
1342	case INDEX_op_qemu_st64:
1343	tcg_out_qemu_st(s, args, 3);
1344	break;
1345
1346	default:
1347	tcg_abort();
1348	}
1349	}
1350
1351	static const TCGTargetOpDef x86_op_defs[] = {
1352	{ INDEX_op_exit_tb, {"", "" } },
1353	{ INDEX_op_goto_tb, {"", "" } },
1354	{ INDEX_op_call, { "ri", "", } },
1355	{ INDEX_op_jmp, { "ri", ""} },
1356	{ INDEX_op_br, {"", "" } },
1357	{ INDEX_op_mov_i32, { "r", "r" } },
1358	{ INDEX_op_movi_i32, { "r" } },
1359	{ INDEX_op_ld8u_i32, { "r", "r" } },
1360	{ INDEX_op_ld8s_i32, { "r", "r" } },
1361	{ INDEX_op_ld16u_i32, { "r", "r" } },
1362	{ INDEX_op_ld16s_i32, { "r", "r" } },
1363	{ INDEX_op_ld_i32, { "r", "r" } },
1364	{ INDEX_op_st8_i32, { "q", "r" } },
1365	{ INDEX_op_st16_i32, { "r", "r" } },
1366	{ INDEX_op_st_i32, { "r", "r" } },
1367
1368	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1369	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1370	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1371	{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1372	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1373	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1374	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1375	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1376	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1377
1378	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1379	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1380	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1381
1382	{ INDEX_op_brcond_i32, { "r", "ri" } },
1383
1384	{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1385	{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1386	{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1387
1388	#if TARGET_LONG_BITS == 32
1389	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1390	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1391	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1392	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1393	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1394	{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
1395
1396	{ INDEX_op_qemu_st8, { "cb", "L" } },
1397	{ INDEX_op_qemu_st16, { "L", "L" } },
1398	{ INDEX_op_qemu_st32, { "L", "L" } },
1399	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1400	#else
1401	{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1402	{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1403	{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1404	{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1405	{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1406	{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1407
1408	{ INDEX_op_qemu_st8, { "cb", "L", "L" } },
1409	{ INDEX_op_qemu_st16, { "L", "L", "L" } },
1410	{ INDEX_op_qemu_st32, { "L", "L", "L" } },
1411	{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1412	#endif
1413	#ifndef VBOX
1414	{ -1 },
1415	#else
1416	{ -1, {"", "", "", ""} },
1417	#endif
1418	};
1419
1420	static int tcg_target_callee_save_regs[] = {
1421	#ifndef VBOX
1422	/* TCG_REG_EBP, / / currently used for the global env, so no
1423	need to save */
1424	TCG_REG_EBX,
1425	TCG_REG_ESI,
1426	TCG_REG_EDI,
1427	#else
1428	TCG_REG_EBP,
1429	TCG_REG_EBX,
1430	/* TCG_REG_ESI, / / currently used for the global env, so no
1431	need to save */
1432	TCG_REG_EDI,
1433	#endif
1434	};
1435
1436	/* Generate global QEMU prologue and epilogue code */
1437	void tcg_target_qemu_prologue(TCGContext *s)
1438	{
1439	int i, frame_size, push_size, stack_addend;
1440
1441	/* TB prologue */
1442	/* save all callee saved registers */
1443	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1444	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1445	}
1446	/* reserve some stack space */
1447	push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1448	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1449	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1450	~(TCG_TARGET_STACK_ALIGN - 1);
1451	stack_addend = frame_size - push_size;
1452	tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1453	# ifdef VBOX
1454	tcg_gen_stack_alignment_check(s);
1455	# endif
1456
1457	tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp %eax /
1458
1459	/* TB epilogue */
1460	tb_ret_addr = s->code_ptr;
1461	tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1462	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1463	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1464	}
1465	tcg_out8(s, 0xc3); /* ret */
1466	}
1467
1468	void tcg_target_init(TCGContext *s)
1469	{
1470	/* fail safe */
1471	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1472	tcg_abort();
1473
1474	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1475	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1476	(1 << TCG_REG_EAX) \|
1477	(1 << TCG_REG_EDX) \|
1478	(1 << TCG_REG_ECX));
1479
1480	tcg_regset_clear(s->reserved_regs);
1481	tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1482
1483	tcg_add_target_add_op_defs(x86_op_defs);
1484	}

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source: vbox/trunk/src/recompiler_new/tcg/i386/tcg-target.c@ 17647

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