Changeset 100046 in vbox
- Timestamp:
- Jun 1, 2023 6:57:29 PM (18 months ago)
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 2 edited
- 1 moved
-
DisasmInternal-armv8.h (modified) (1 diff)
-
DisasmTables-armv8-a64.cpp (moved) (moved from trunk/src/VBox/Disassembler/DisasmTables-armv8.cpp ) (6 diffs)
-
Makefile.kmk (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
r99334 r100046 59 59 kDisParmParseCond, 60 60 kDisParmParsePState, 61 kDisParmParseCRnCRm, 62 kDisParmParseSysReg, 61 63 kDisParmParseMax 62 64 } DISPARMPARSEIDX; -
trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp
r100045 r100046 284 284 285 285 286 /* SYS */ 287 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Sys) 288 DIS_ARMV8_OP(0xfff80000, 0xd5080000, "sys %I, %Cn, %Cm, %I, %X", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS), 289 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Sys, DISARMV8INSNCLASS_F_FORCED_64BIT, 290 kDisArmV8OpcDecodeNop, 0, 0) 291 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3), 292 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8), 293 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3), 294 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5) 295 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 296 297 298 /* SYSL */ 299 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysL) 300 DIS_ARMV8_OP(0xfff80000, 0xd5280000, "sysl %X, %I, %Cn, %Cm, %I", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS), 301 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysL, DISARMV8INSNCLASS_F_FORCED_64BIT, 302 kDisArmV8OpcDecodeNop, 0, 0) 303 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 304 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3), 305 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8), 306 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3) 307 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 308 309 310 /* MSR */ 311 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Msr) 312 DIS_ARMV8_OP(0xfff00000, 0xd5080000, "msr %S, %X", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), 313 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Msr, DISARMV8INSNCLASS_F_FORCED_64BIT, 314 kDisArmV8OpcDecodeNop, 0, 0) 315 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15), 316 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 317 DIS_ARMV8_INSN_PARAM_NONE, 318 DIS_ARMV8_INSN_PARAM_NONE 319 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 320 321 322 /* MRS */ 323 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Mrs) 324 DIS_ARMV8_OP(0xfff00000, 0xd5280000, "mrs %X, %S", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), 325 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Mrs, DISARMV8INSNCLASS_F_FORCED_64BIT, 326 kDisArmV8OpcDecodeNop, 0, 0) 327 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 328 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15), 329 DIS_ARMV8_INSN_PARAM_NONE, 330 DIS_ARMV8_INSN_PARAM_NONE 331 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 332 333 334 /* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */ 335 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64UncondBrReg) 336 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 337 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 338 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 339 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 340 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 341 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 342 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 343 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 344 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 345 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 346 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 347 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 348 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 349 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 350 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 351 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY 352 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64UncondBrReg, RT_BIT_32(21) | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24), 21); 353 354 355 /* B/BL */ 356 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64UncondBrImm) 357 DIS_ARMV8_OP(0xfc000000, 0x14000000, "b %J", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 358 DIS_ARMV8_OP(0xfc000000, 0x94000000, "bl %J", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 359 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64UncondBrImm, 0 /*fClass*/, 360 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31) 361 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 0, 26), 362 DIS_ARMV8_INSN_PARAM_NONE, 363 DIS_ARMV8_INSN_PARAM_NONE, 364 DIS_ARMV8_INSN_PARAM_NONE 365 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 366 367 368 /* CBZ/CBNZ */ 369 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CmpBrImm) 370 DIS_ARMV8_OP(0x7f000000, 0x34000000, "cbz %X, %J", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 371 DIS_ARMV8_OP(0x7f000000, 0x35000000, "cbnz %X, %J", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 372 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CmpBrImm, DISARMV8INSNCLASS_F_SF, 373 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24) 374 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 375 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19), 376 DIS_ARMV8_INSN_PARAM_NONE, 377 DIS_ARMV8_INSN_PARAM_NONE 378 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 379 380 381 /* TBZ/TBNZ */ 382 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64TestBrImm) 383 DIS_ARMV8_OP(0x7f000000, 0x36000000, "tbz %X, %I, %J", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 384 DIS_ARMV8_OP(0x7f000000, 0x37000000, "tbnz %X, %I, %J", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 385 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64TestBrImm, DISARMV8INSNCLASS_F_SF, 386 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24) 387 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 388 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 19, 5), 389 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 14), 390 DIS_ARMV8_INSN_PARAM_NONE 391 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 392 393 286 394 DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(g_ArmV8A64BrExcpSys) 287 395 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30), g_ArmV8A64CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */ … … 291 399 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, g_ArmV8A64DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */ 292 400 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, g_ArmV8A64PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */ 293 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, g_ArmV8A64SysResult) /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */ 401 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, g_ArmV8A64SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */ 402 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, g_ArmV8A64Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */ 403 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, g_ArmV8A64SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */ 404 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, g_ArmV8A64Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */ 405 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, g_ArmV8A64Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */ 406 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, g_ArmV8A64UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */ 407 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, g_ArmV8A64UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */ 408 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, g_ArmV8A64CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */ 409 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, g_ArmV8A64TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */ 294 410 DIS_ARMV8_DECODE_TBL_DEFINE_END(g_ArmV8A64BrExcpSys); 411 412 413 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64LogicalAddSubReg) 414 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Logical (shifted register) */ 415 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Add/subtract (shifted/extended register) */ 416 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64LogicalAddSubReg, RT_BIT_32(24), 24); 417 418 419 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DataProcReg) 420 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 421 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DataProcReg, RT_BIT_32(24), 24); 295 422 296 423 … … 321 448 * 3 0 0 1 1 UNALLOC 322 449 * 4 0 1 0 0 Loads and stores 323 * 5 0 1 0 1 Data processing - register 450 * 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already) 324 451 * 6 0 1 1 0 Loads and stores 325 452 * 7 0 1 1 1 Data processing - SIMD and floating point … … 329 456 * 11 1 0 1 1 Branch, exception generation and system instructions 330 457 * 12 1 1 0 0 Loads and stores 331 * 13 1 1 0 1 Data processing - register 458 * 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already) 332 459 * 14 1 1 1 0 Loads and stores 333 460 * 15 1 1 1 1 Data processing - SIMD and floating point … … 339 466 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */ 340 467 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */ 341 DIS_ARMV8_DECODE_MAP_ INVALID_ENTRY, /* Data processing (register). */342 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Lo d/Stores */468 DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */ 469 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */ 343 470 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data processing (SIMD & FP) */ 344 471 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnDataProcessingImm), /* Data processing (immediate). */ … … 347 474 DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64BrExcpSys), /* Branches / Exception generation and system instructions. */ 348 475 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores. */ 349 DIS_ARMV8_DECODE_MAP_ INVALID_ENTRY, /* Data processing (register). */476 DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */ 350 477 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores. */ 351 478 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /* Data processing (SIMD & FP). */ -
trunk/src/VBox/Disassembler/Makefile.kmk
r99684 r100046 58 58 Disasm.cpp \ 59 59 DisasmCore-armv8.cpp \ 60 DisasmTables-armv8 .cpp \60 DisasmTables-armv8-a64.cpp \ 61 61 DisasmFormatBytes.cpp \ 62 62 DisasmFormatArmV8.cpp
Note:
See TracChangeset
for help on using the changeset viewer.
