Changeset 100072 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Jun 5, 2023 3:17:42 PM (19 months ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp
r100052 r100072 1473 1473 1474 1474 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga); 1475 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA)) 1475 if (!IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA)) 1476 { /* probable */ } 1477 else 1476 1478 { 1477 1479 Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage)); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructions3DNow.cpp.h
r98103 r100072 136 136 case 0xbf: return FNIEMOP_CALL(iemOp_3Dnow_pavgusb_PQ_Qq); 137 137 default: 138 return IEMOP_RAISE_INVALID_OPCODE();138 IEMOP_RAISE_INVALID_OPCODE_RET(); 139 139 } 140 140 } -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsCommon.cpp.h
r99309 r100072 712 712 { 713 713 IEMOP_MNEMONIC(Invalid, "Invalid"); 714 return IEMOP_RAISE_INVALID_OPCODE();714 IEMOP_RAISE_INVALID_OPCODE_RET(); 715 715 } 716 716 … … 721 721 RT_NOREF_PV(bRm); 722 722 IEMOP_MNEMONIC(InvalidWithRm, "InvalidWithRM"); 723 return IEMOP_RAISE_INVALID_OPCODE();723 IEMOP_RAISE_INVALID_OPCODE_RET(); 724 724 } 725 725 … … 743 743 } 744 744 IEMOP_HLP_DONE_DECODING(); 745 return IEMOP_RAISE_INVALID_OPCODE();745 IEMOP_RAISE_INVALID_OPCODE_RET(); 746 746 } 747 747 … … 762 762 #endif 763 763 IEMOP_HLP_DONE_DECODING(); 764 return IEMOP_RAISE_INVALID_OPCODE();764 IEMOP_RAISE_INVALID_OPCODE_RET(); 765 765 } 766 766 … … 785 785 } 786 786 IEMOP_HLP_DONE_DECODING(); 787 return IEMOP_RAISE_INVALID_OPCODE();787 IEMOP_RAISE_INVALID_OPCODE_RET(); 788 788 } 789 789 … … 805 805 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bRm); 806 806 IEMOP_HLP_DONE_DECODING(); 807 return IEMOP_RAISE_INVALID_OPCODE();807 IEMOP_RAISE_INVALID_OPCODE_RET(); 808 808 } 809 809 … … 827 827 } 828 828 IEMOP_HLP_DONE_DECODING(); 829 return IEMOP_RAISE_INVALID_OPCODE();829 IEMOP_RAISE_INVALID_OPCODE_RET(); 830 830 } 831 831 … … 846 846 #endif 847 847 IEMOP_HLP_DONE_DECODING(); 848 return IEMOP_RAISE_INVALID_OPCODE();848 IEMOP_RAISE_INVALID_OPCODE_RET(); 849 849 } 850 850 … … 870 870 } 871 871 IEMOP_HLP_DONE_DECODING(); 872 return IEMOP_RAISE_INVALID_OPCODE();872 IEMOP_RAISE_INVALID_OPCODE_RET(); 873 873 } 874 874 … … 894 894 } 895 895 IEMOP_HLP_DONE_DECODING(); 896 return IEMOP_RAISE_INVALID_OPCODE();896 IEMOP_RAISE_INVALID_OPCODE_RET(); 897 897 } 898 898 … … 919 919 IEMOP_HLP_DONE_DECODING(); 920 920 } 921 return IEMOP_RAISE_INVALID_OPCODE();922 } 923 921 IEMOP_RAISE_INVALID_OPCODE_RET(); 922 } 923 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r100052 r100072 119 119 #define IEMOP_BODY_BINARY_rm_r8_NO_LOCK() \ 120 120 IEMOP_HLP_DONE_DECODING(); \ 121 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \121 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 122 122 } \ 123 123 } \ … … 341 341 #define IEMOP_BODY_BINARY_rm_rv_NO_LOCK() \ 342 342 IEMOP_HLP_DONE_DECODING(); \ 343 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \343 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 344 344 } \ 345 345 } \ … … 624 624 IEMOP_HLP_NO_64BIT(); 625 625 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 626 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize);626 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize); 627 627 } 628 628 … … 791 791 IEMOP_HLP_NO_64BIT(); 792 792 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 793 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize); 793 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_END_TB/*?*/, 794 iemCImpl_pop_Sreg, X86_SREG_CS, pVCpu->iem.s.enmEffOpSize); 794 795 } 795 796 … … 910 911 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 911 912 IEMOP_HLP_NO_64BIT(); 912 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_SS, pVCpu->iem.s.enmEffOpSize);913 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, iemCImpl_pop_Sreg, X86_SREG_SS, pVCpu->iem.s.enmEffOpSize); 913 914 } 914 915 … … 1015 1016 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1016 1017 IEMOP_HLP_NO_64BIT(); 1017 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_DS, pVCpu->iem.s.enmEffOpSize);1018 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, iemCImpl_pop_Sreg, X86_SREG_DS, pVCpu->iem.s.enmEffOpSize); 1018 1019 } 1019 1020 … … 1143 1144 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1144 1145 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF); 1145 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_daa);1146 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_daa); 1146 1147 } 1147 1148 … … 1253 1254 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1254 1255 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF); 1255 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_das);1256 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_das); 1256 1257 } 1257 1258 … … 1414 1415 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF); 1415 1416 1416 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_aaa);1417 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aaa); 1417 1418 } 1418 1419 … … 1543 1544 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_OF); 1544 1545 1545 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_aas);1546 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aas); 1546 1547 } 1547 1548 … … 2282 2283 IEMOP_HLP_NO_64BIT(); 2283 2284 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT) 2284 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_pusha_16);2285 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_pusha_16); 2285 2286 Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_32BIT); 2286 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_pusha_32);2287 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_pusha_32); 2287 2288 } 2288 2289 … … 2299 2300 IEMOP_HLP_NO_64BIT(); 2300 2301 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT) 2301 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_popa_16);2302 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS, iemCImpl_popa_16); 2302 2303 Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_32BIT); 2303 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_popa_32);2304 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS, iemCImpl_popa_32); 2304 2305 } 2305 2306 IEMOP_MNEMONIC(mvex, "mvex"); 2306 2307 Log(("mvex prefix is not supported!\n")); 2307 return IEMOP_RAISE_INVALID_OPCODE();2308 IEMOP_RAISE_INVALID_OPCODE_RET(); 2308 2309 } 2309 2310 … … 2396 2397 IEM_MC_FETCH_MEM_U16_DISP(u16UpperBounds, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 2); 2397 2398 2398 IEM_MC_CALL_CIMPL_3( iemCImpl_bound_16, u16Index, u16LowerBounds, u16UpperBounds); /* returns */2399 IEM_MC_CALL_CIMPL_3(0, iemCImpl_bound_16, u16Index, u16LowerBounds, u16UpperBounds); /* returns */ 2399 2400 IEM_MC_END(); 2400 2401 } … … 2414 2415 IEM_MC_FETCH_MEM_U32_DISP(u32UpperBounds, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 4); 2415 2416 2416 IEM_MC_CALL_CIMPL_3( iemCImpl_bound_32, u32Index, u32LowerBounds, u32UpperBounds); /* returns */2417 IEM_MC_CALL_CIMPL_3(0, iemCImpl_bound_32, u32Index, u32LowerBounds, u32UpperBounds); /* returns */ 2417 2418 IEM_MC_END(); 2418 2419 } … … 2427 2428 here because MODRM.MOD == 3. */ 2428 2429 Log(("evex not supported by the guest CPU!\n")); 2429 return IEMOP_RAISE_INVALID_OPCODE();2430 IEMOP_RAISE_INVALID_OPCODE_RET(); 2430 2431 } 2431 2432 } … … 3069 3070 switch (pVCpu->iem.s.enmEffAddrMode) 3070 3071 { 3071 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op8_addr16, false);3072 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op8_addr32, false);3073 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op8_addr64, false);3072 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op8_addr16, false); 3073 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op8_addr32, false); 3074 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op8_addr64, false); 3074 3075 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3075 3076 } … … 3080 3081 switch (pVCpu->iem.s.enmEffAddrMode) 3081 3082 { 3082 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op8_addr16, false);3083 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op8_addr32, false);3084 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op8_addr64, false);3083 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op8_addr16, false); 3084 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op8_addr32, false); 3085 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op8_addr64, false); 3085 3086 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3086 3087 } … … 3104 3105 switch (pVCpu->iem.s.enmEffAddrMode) 3105 3106 { 3106 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op16_addr16, false);3107 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op16_addr32, false);3108 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op16_addr64, false);3107 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op16_addr16, false); 3108 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op16_addr32, false); 3109 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op16_addr64, false); 3109 3110 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3110 3111 } … … 3114 3115 switch (pVCpu->iem.s.enmEffAddrMode) 3115 3116 { 3116 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op32_addr16, false);3117 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op32_addr32, false);3118 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op32_addr64, false);3117 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op32_addr16, false); 3118 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op32_addr32, false); 3119 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op32_addr64, false); 3119 3120 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3120 3121 } … … 3131 3132 switch (pVCpu->iem.s.enmEffAddrMode) 3132 3133 { 3133 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op16_addr16, false);3134 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op16_addr32, false);3135 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op16_addr64, false);3134 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op16_addr16, false); 3135 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op16_addr32, false); 3136 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op16_addr64, false); 3136 3137 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3137 3138 } … … 3141 3142 switch (pVCpu->iem.s.enmEffAddrMode) 3142 3143 { 3143 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op32_addr16, false);3144 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op32_addr32, false);3145 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op32_addr64, false);3144 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op32_addr16, false); 3145 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op32_addr32, false); 3146 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op32_addr64, false); 3146 3147 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3147 3148 } … … 3165 3166 switch (pVCpu->iem.s.enmEffAddrMode) 3166 3167 { 3167 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false);3168 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false);3169 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false);3168 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3169 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3170 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3170 3171 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3171 3172 } … … 3176 3177 switch (pVCpu->iem.s.enmEffAddrMode) 3177 3178 { 3178 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false);3179 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false);3180 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false);3179 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3180 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3181 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3181 3182 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3182 3183 } … … 3200 3201 switch (pVCpu->iem.s.enmEffAddrMode) 3201 3202 { 3202 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false);3203 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false);3204 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false);3203 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3204 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3205 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3205 3206 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3206 3207 } … … 3210 3211 switch (pVCpu->iem.s.enmEffAddrMode) 3211 3212 { 3212 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false);3213 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false);3214 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false);3213 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3214 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3215 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3215 3216 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3216 3217 } … … 3227 3228 switch (pVCpu->iem.s.enmEffAddrMode) 3228 3229 { 3229 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false);3230 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false);3231 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false);3230 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3231 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3232 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3232 3233 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3233 3234 } … … 3237 3238 switch (pVCpu->iem.s.enmEffAddrMode) 3238 3239 { 3239 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false);3240 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false);3241 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false);3240 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3241 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3242 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3242 3243 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3243 3244 } … … 3620 3621 #define IEMOP_BODY_BINARY_Eb_Ib_NO_LOCK() \ 3621 3622 IEMOP_HLP_DONE_DECODING(); \ 3622 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \3623 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 3623 3624 } \ 3624 3625 } \ … … 3919 3920 #define IEMOP_BODY_BINARY_Ev_Iz_NO_LOCK() \ 3920 3921 IEMOP_HLP_DONE_DECODING(); \ 3921 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \3922 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 3922 3923 } \ 3923 3924 } \ … … 4286 4287 #define IEMOP_BODY_BINARY_Ev_Ib_NO_LOCK() \ 4287 4288 IEMOP_HLP_DONE_DECODING(); \ 4288 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \4289 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 4289 4290 } \ 4290 4291 } \ … … 5001 5002 uint8_t const iSegReg = IEM_GET_MODRM_REG_8(bRm); 5002 5003 if ( iSegReg > X86_SREG_GS) 5003 return IEMOP_RAISE_INVALID_OPCODE(); /** @todo should probably not be raised until we've fetched all the opcode bytes? */5004 IEMOP_RAISE_INVALID_OPCODE_RET(); /** @todo should probably not be raised until we've fetched all the opcode bytes? */ 5004 5005 5005 5006 /* … … 5075 5076 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 5076 5077 if (IEM_IS_MODRM_REG_MODE(bRm)) 5077 return IEMOP_RAISE_INVALID_OPCODE(); /* no register form */5078 IEMOP_RAISE_INVALID_OPCODE_RET(); /* no register form */ 5078 5079 5079 5080 switch (pVCpu->iem.s.enmEffOpSize) … … 5141 5142 if ( iSegReg == X86_SREG_CS 5142 5143 || iSegReg > X86_SREG_GS) 5143 return IEMOP_RAISE_INVALID_OPCODE(); /** @todo should probably not be raised until we've fetched all the opcode bytes? */5144 IEMOP_RAISE_INVALID_OPCODE_RET(); /** @todo should probably not be raised until we've fetched all the opcode bytes? */ 5144 5145 5145 5146 /* … … 5153 5154 IEM_MC_ARG(uint16_t, u16Value, 1); 5154 5155 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 5155 IEM_MC_CALL_CIMPL_2(iemCImpl_load_SReg, iSRegArg, u16Value); 5156 if (iSRegArg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu)) 5157 IEM_MC_CALL_CIMPL_2( 0, iemCImpl_load_SReg, iSRegArg, u16Value); 5158 else 5159 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE, iemCImpl_load_SReg, iSRegArg, u16Value); 5156 5160 IEM_MC_END(); 5157 5161 } … … 5169 5173 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5170 5174 IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 5171 IEM_MC_CALL_CIMPL_2(iemCImpl_load_SReg, iSRegArg, u16Value); 5175 if (iSRegArg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu)) 5176 IEM_MC_CALL_CIMPL_2( 0, iemCImpl_load_SReg, iSRegArg, u16Value); 5177 else 5178 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE, iemCImpl_load_SReg, iSRegArg, u16Value); 5172 5179 IEM_MC_END(); 5173 5180 } … … 5322 5329 default: 5323 5330 Log(("XOP: Invalid vvvv value: %#x!\n", bRm & 0x1f)); 5324 return IEMOP_RAISE_INVALID_OPCODE();5331 IEMOP_RAISE_INVALID_OPCODE_RET(); 5325 5332 } 5326 5333 } … … 5330 5337 else 5331 5338 Log(("XOP: XOP support disabled!\n")); 5332 return IEMOP_RAISE_INVALID_OPCODE();5339 IEMOP_RAISE_INVALID_OPCODE_RET(); 5333 5340 } 5334 5341 … … 5400 5407 { 5401 5408 IEMOP_MNEMONIC(pause, "pause"); 5409 /* ASSUMING that we keep the IEM_F_X86_CTX_IN_GUEST, IEM_F_X86_CTX_VMX 5410 and IEM_F_X86_CTX_SVM in the TB key, we can safely do the following: */ 5411 if (!IEM_IS_IN_GUEST(pVCpu)) 5412 { /* probable */ } 5402 5413 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 5403 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmx)5404 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmx_pause);5414 else if (pVCpu->iem.s.fExec & IEM_F_X86_CTX_VMX) 5415 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmx_pause); 5405 5416 #endif 5406 5417 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM 5407 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvm)5408 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_svm_pause);5418 else if (pVCpu->iem.s.fExec & IEM_F_X86_CTX_SVM) 5419 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_svm_pause); 5409 5420 #endif 5410 5421 } … … 5601 5612 uint16_t uSel; IEM_OPCODE_GET_NEXT_U16(&uSel); 5602 5613 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5603 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_callf, uSel, offSeg, pVCpu->iem.s.enmEffOpSize); 5614 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 5615 iemCImpl_callf, uSel, offSeg, pVCpu->iem.s.enmEffOpSize); 5604 5616 } 5605 5617 … … 5627 5639 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5628 5640 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 5629 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_pushf, pVCpu->iem.s.enmEffOpSize);5641 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_pushf, pVCpu->iem.s.enmEffOpSize); 5630 5642 } 5631 5643 … … 5639 5651 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5640 5652 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 5641 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_popf, pVCpu->iem.s.enmEffOpSize);5653 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, iemCImpl_popf, pVCpu->iem.s.enmEffOpSize); 5642 5654 } 5643 5655 … … 5652 5664 if ( IEM_IS_64BIT_CODE(pVCpu) 5653 5665 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf) 5654 return IEMOP_RAISE_INVALID_OPCODE();5666 IEMOP_RAISE_INVALID_OPCODE_RET(); 5655 5667 IEM_MC_BEGIN(0, 2); 5656 5668 IEM_MC_LOCAL(uint32_t, u32Flags); … … 5677 5689 if ( IEM_IS_64BIT_CODE(pVCpu) 5678 5690 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf) 5679 return IEMOP_RAISE_INVALID_OPCODE();5691 IEMOP_RAISE_INVALID_OPCODE_RET(); 5680 5692 IEM_MC_BEGIN(0, 1); 5681 5693 IEM_MC_LOCAL(uint8_t, u8Flags); … … 5891 5903 switch (pVCpu->iem.s.enmEffAddrMode) 5892 5904 { 5893 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op8_addr16, pVCpu->iem.s.iEffSeg);5894 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op8_addr32, pVCpu->iem.s.iEffSeg);5895 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op8_addr64, pVCpu->iem.s.iEffSeg);5905 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op8_addr16, pVCpu->iem.s.iEffSeg); 5906 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op8_addr32, pVCpu->iem.s.iEffSeg); 5907 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op8_addr64, pVCpu->iem.s.iEffSeg); 5896 5908 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 5897 5909 } … … 5930 5942 switch (pVCpu->iem.s.enmEffAddrMode) 5931 5943 { 5932 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op16_addr16, pVCpu->iem.s.iEffSeg);5933 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op16_addr32, pVCpu->iem.s.iEffSeg);5934 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op16_addr64, pVCpu->iem.s.iEffSeg);5944 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op16_addr16, pVCpu->iem.s.iEffSeg); 5945 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op16_addr32, pVCpu->iem.s.iEffSeg); 5946 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op16_addr64, pVCpu->iem.s.iEffSeg); 5935 5947 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 5936 5948 } … … 5939 5951 switch (pVCpu->iem.s.enmEffAddrMode) 5940 5952 { 5941 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op32_addr16, pVCpu->iem.s.iEffSeg);5942 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op32_addr32, pVCpu->iem.s.iEffSeg);5943 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op32_addr64, pVCpu->iem.s.iEffSeg);5953 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op32_addr16, pVCpu->iem.s.iEffSeg); 5954 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op32_addr32, pVCpu->iem.s.iEffSeg); 5955 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op32_addr64, pVCpu->iem.s.iEffSeg); 5944 5956 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 5945 5957 } … … 5948 5960 { 5949 5961 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_6); 5950 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op64_addr32, pVCpu->iem.s.iEffSeg);5951 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op64_addr64, pVCpu->iem.s.iEffSeg);5962 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op64_addr32, pVCpu->iem.s.iEffSeg); 5963 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op64_addr64, pVCpu->iem.s.iEffSeg); 5952 5964 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 5953 5965 } … … 6040 6052 switch (pVCpu->iem.s.enmEffAddrMode) 6041 6053 { 6042 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op8_addr16, pVCpu->iem.s.iEffSeg);6043 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op8_addr32, pVCpu->iem.s.iEffSeg);6044 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op8_addr64, pVCpu->iem.s.iEffSeg);6054 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op8_addr16, pVCpu->iem.s.iEffSeg); 6055 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op8_addr32, pVCpu->iem.s.iEffSeg); 6056 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op8_addr64, pVCpu->iem.s.iEffSeg); 6045 6057 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6046 6058 } … … 6051 6063 switch (pVCpu->iem.s.enmEffAddrMode) 6052 6064 { 6053 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op8_addr16, pVCpu->iem.s.iEffSeg);6054 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op8_addr32, pVCpu->iem.s.iEffSeg);6055 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op8_addr64, pVCpu->iem.s.iEffSeg);6065 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op8_addr16, pVCpu->iem.s.iEffSeg); 6066 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op8_addr32, pVCpu->iem.s.iEffSeg); 6067 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op8_addr64, pVCpu->iem.s.iEffSeg); 6056 6068 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6057 6069 } … … 6090 6102 switch (pVCpu->iem.s.enmEffAddrMode) 6091 6103 { 6092 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op16_addr16, pVCpu->iem.s.iEffSeg);6093 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op16_addr32, pVCpu->iem.s.iEffSeg);6094 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op16_addr64, pVCpu->iem.s.iEffSeg);6104 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op16_addr16, pVCpu->iem.s.iEffSeg); 6105 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op16_addr32, pVCpu->iem.s.iEffSeg); 6106 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op16_addr64, pVCpu->iem.s.iEffSeg); 6095 6107 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6096 6108 } … … 6099 6111 switch (pVCpu->iem.s.enmEffAddrMode) 6100 6112 { 6101 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op32_addr16, pVCpu->iem.s.iEffSeg);6102 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op32_addr32, pVCpu->iem.s.iEffSeg);6103 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op32_addr64, pVCpu->iem.s.iEffSeg);6113 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op32_addr16, pVCpu->iem.s.iEffSeg); 6114 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op32_addr32, pVCpu->iem.s.iEffSeg); 6115 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op32_addr64, pVCpu->iem.s.iEffSeg); 6104 6116 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6105 6117 } … … 6108 6120 { 6109 6121 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_4); 6110 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op64_addr32, pVCpu->iem.s.iEffSeg);6111 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op64_addr64, pVCpu->iem.s.iEffSeg);6122 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op64_addr32, pVCpu->iem.s.iEffSeg); 6123 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op64_addr64, pVCpu->iem.s.iEffSeg); 6112 6124 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6113 6125 } … … 6124 6136 switch (pVCpu->iem.s.enmEffAddrMode) 6125 6137 { 6126 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op16_addr16, pVCpu->iem.s.iEffSeg);6127 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op16_addr32, pVCpu->iem.s.iEffSeg);6128 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op16_addr64, pVCpu->iem.s.iEffSeg);6138 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op16_addr16, pVCpu->iem.s.iEffSeg); 6139 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op16_addr32, pVCpu->iem.s.iEffSeg); 6140 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op16_addr64, pVCpu->iem.s.iEffSeg); 6129 6141 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6130 6142 } … … 6133 6145 switch (pVCpu->iem.s.enmEffAddrMode) 6134 6146 { 6135 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op32_addr16, pVCpu->iem.s.iEffSeg);6136 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op32_addr32, pVCpu->iem.s.iEffSeg);6137 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op32_addr64, pVCpu->iem.s.iEffSeg);6147 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op32_addr16, pVCpu->iem.s.iEffSeg); 6148 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op32_addr32, pVCpu->iem.s.iEffSeg); 6149 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op32_addr64, pVCpu->iem.s.iEffSeg); 6138 6150 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6139 6151 } … … 6142 6154 { 6143 6155 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_2); 6144 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op64_addr32, pVCpu->iem.s.iEffSeg);6145 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op64_addr64, pVCpu->iem.s.iEffSeg);6156 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op64_addr32, pVCpu->iem.s.iEffSeg); 6157 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op64_addr64, pVCpu->iem.s.iEffSeg); 6146 6158 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6147 6159 } … … 6246 6258 switch (pVCpu->iem.s.enmEffAddrMode) 6247 6259 { 6248 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_al_m16);6249 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_al_m32);6250 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_al_m64);6260 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, iemCImpl_stos_al_m16); 6261 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, iemCImpl_stos_al_m32); 6262 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, iemCImpl_stos_al_m64); 6251 6263 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6252 6264 } … … 6285 6297 switch (pVCpu->iem.s.enmEffAddrMode) 6286 6298 { 6287 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_ax_m16);6288 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_ax_m32);6289 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_ax_m64);6299 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_ax_m16); 6300 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_ax_m32); 6301 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_ax_m64); 6290 6302 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6291 6303 } … … 6294 6306 switch (pVCpu->iem.s.enmEffAddrMode) 6295 6307 { 6296 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_eax_m16);6297 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_eax_m32);6298 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_eax_m64);6308 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_eax_m16); 6309 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_eax_m32); 6310 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_eax_m64); 6299 6311 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6300 6312 } … … 6303 6315 { 6304 6316 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_9); 6305 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_rax_m32);6306 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_rax_m64);6317 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_rax_m32); 6318 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_rax_m64); 6307 6319 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6308 6320 } … … 6384 6396 switch (pVCpu->iem.s.enmEffAddrMode) 6385 6397 { 6386 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_al_m16, pVCpu->iem.s.iEffSeg);6387 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_al_m32, pVCpu->iem.s.iEffSeg);6388 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_al_m64, pVCpu->iem.s.iEffSeg);6398 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_al_m16, pVCpu->iem.s.iEffSeg); 6399 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_al_m32, pVCpu->iem.s.iEffSeg); 6400 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_al_m64, pVCpu->iem.s.iEffSeg); 6389 6401 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6390 6402 } … … 6423 6435 switch (pVCpu->iem.s.enmEffAddrMode) 6424 6436 { 6425 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_ax_m16, pVCpu->iem.s.iEffSeg);6426 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_ax_m32, pVCpu->iem.s.iEffSeg);6427 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_ax_m64, pVCpu->iem.s.iEffSeg);6437 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_ax_m16, pVCpu->iem.s.iEffSeg); 6438 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_ax_m32, pVCpu->iem.s.iEffSeg); 6439 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_ax_m64, pVCpu->iem.s.iEffSeg); 6428 6440 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6429 6441 } … … 6432 6444 switch (pVCpu->iem.s.enmEffAddrMode) 6433 6445 { 6434 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_eax_m16, pVCpu->iem.s.iEffSeg);6435 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_eax_m32, pVCpu->iem.s.iEffSeg);6436 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_eax_m64, pVCpu->iem.s.iEffSeg);6446 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_eax_m16, pVCpu->iem.s.iEffSeg); 6447 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_eax_m32, pVCpu->iem.s.iEffSeg); 6448 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_eax_m64, pVCpu->iem.s.iEffSeg); 6437 6449 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6438 6450 } … … 6441 6453 { 6442 6454 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_7); 6443 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_rax_m32, pVCpu->iem.s.iEffSeg);6444 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_rax_m64, pVCpu->iem.s.iEffSeg);6455 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_rax_m32, pVCpu->iem.s.iEffSeg); 6456 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_rax_m64, pVCpu->iem.s.iEffSeg); 6445 6457 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6446 6458 } … … 6528 6540 switch (pVCpu->iem.s.enmEffAddrMode) 6529 6541 { 6530 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_al_m16);6531 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_al_m32);6532 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_al_m64);6542 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_al_m16); 6543 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_al_m32); 6544 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_al_m64); 6533 6545 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6534 6546 } … … 6539 6551 switch (pVCpu->iem.s.enmEffAddrMode) 6540 6552 { 6541 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_al_m16);6542 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_al_m32);6543 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_al_m64);6553 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_al_m16); 6554 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_al_m32); 6555 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_al_m64); 6544 6556 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6545 6557 } … … 6578 6590 switch (pVCpu->iem.s.enmEffAddrMode) 6579 6591 { 6580 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_ax_m16);6581 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_ax_m32);6582 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_ax_m64);6592 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_ax_m16); 6593 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_ax_m32); 6594 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_ax_m64); 6583 6595 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6584 6596 } … … 6587 6599 switch (pVCpu->iem.s.enmEffAddrMode) 6588 6600 { 6589 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_eax_m16);6590 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_eax_m32);6591 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_eax_m64);6601 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_eax_m16); 6602 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_eax_m32); 6603 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_eax_m64); 6592 6604 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6593 6605 } … … 6596 6608 { 6597 6609 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_6); /** @todo It's this wrong, we can do 16-bit addressing in 64-bit mode, but not 32-bit. right? */ 6598 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_rax_m32);6599 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_rax_m64);6610 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_rax_m32); 6611 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_rax_m64); 6600 6612 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6601 6613 } … … 6611 6623 switch (pVCpu->iem.s.enmEffAddrMode) 6612 6624 { 6613 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_ax_m16);6614 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_ax_m32);6615 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_ax_m64);6625 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_ax_m16); 6626 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_ax_m32); 6627 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_ax_m64); 6616 6628 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6617 6629 } … … 6620 6632 switch (pVCpu->iem.s.enmEffAddrMode) 6621 6633 { 6622 case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_eax_m16);6623 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_eax_m32);6624 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_eax_m64);6634 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_eax_m16); 6635 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_eax_m32); 6636 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_eax_m64); 6625 6637 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6626 6638 } … … 6629 6641 { 6630 6642 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_5); 6631 case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_rax_m32);6632 case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_rax_m64);6643 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_rax_m32); 6644 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_rax_m64); 6633 6645 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6634 6646 } … … 6921 6933 case 5: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shr_eflags); IEMOP_MNEMONIC(shr_Eb_Ib, "shr Eb,Ib"); break; 6922 6934 case 7: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_sar_eflags); IEMOP_MNEMONIC(sar_Eb_Ib, "sar Eb,Ib"); break; 6923 case 6: return IEMOP_RAISE_INVALID_OPCODE();6935 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 6924 6936 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe stupid */ 6925 6937 } … … 6983 6995 case 5: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shr_eflags); IEMOP_MNEMONIC(shr_Ev_Ib, "shr Ev,Ib"); break; 6984 6996 case 7: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_sar_eflags); IEMOP_MNEMONIC(sar_Ev_Ib, "sar Ev,Ib"); break; 6985 case 6: return IEMOP_RAISE_INVALID_OPCODE();6997 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 6986 6998 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe stupid */ 6987 6999 } … … 7121 7133 { 7122 7134 case IEMMODE_16BIT: 7123 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_retn_iw_16, u16Imm);7135 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH, iemCImpl_retn_iw_16, u16Imm); 7124 7136 case IEMMODE_32BIT: 7125 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_retn_iw_32, u16Imm);7137 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH, iemCImpl_retn_iw_32, u16Imm); 7126 7138 case IEMMODE_64BIT: 7127 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_retn_iw_64, u16Imm);7139 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH, iemCImpl_retn_iw_64, u16Imm); 7128 7140 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7129 7141 } … … 7142 7154 { 7143 7155 case IEMMODE_16BIT: 7144 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_retn_16);7156 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH, iemCImpl_retn_16); 7145 7157 case IEMMODE_32BIT: 7146 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_retn_32);7158 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH, iemCImpl_retn_32); 7147 7159 case IEMMODE_64BIT: 7148 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_retn_64);7160 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH, iemCImpl_retn_64); 7149 7161 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7150 7162 } … … 7211 7223 default: 7212 7224 Log(("VEX3: Invalid vvvv value: %#x!\n", bRm & 0x1f)); 7213 return IEMOP_RAISE_INVALID_OPCODE();7225 IEMOP_RAISE_INVALID_OPCODE_RET(); 7214 7226 } 7215 7227 } 7216 7228 Log(("VEX3: VEX support disabled!\n")); 7217 return IEMOP_RAISE_INVALID_OPCODE();7229 IEMOP_RAISE_INVALID_OPCODE_RET(); 7218 7230 } 7219 7231 … … 7260 7272 /** @todo does intel completely decode the sequence with SIB/disp before \#UD? */ 7261 7273 Log(("VEX2: VEX support disabled!\n")); 7262 return IEMOP_RAISE_INVALID_OPCODE();7274 IEMOP_RAISE_INVALID_OPCODE_RET(); 7263 7275 } 7264 7276 … … 7275 7287 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 7276 7288 if ((bRm & X86_MODRM_REG_MASK) != (0 << X86_MODRM_REG_SHIFT)) /* only mov Eb,Ib in this group. */ 7277 return IEMOP_RAISE_INVALID_OPCODE();7289 IEMOP_RAISE_INVALID_OPCODE_RET(); 7278 7290 IEMOP_MNEMONIC(mov_Eb_Ib, "mov Eb,Ib"); 7279 7291 … … 7310 7322 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 7311 7323 if ((bRm & X86_MODRM_REG_MASK) != (0 << X86_MODRM_REG_SHIFT)) /* only mov Eb,Ib in this group. */ 7312 return IEMOP_RAISE_INVALID_OPCODE();7324 IEMOP_RAISE_INVALID_OPCODE_RET(); 7313 7325 IEMOP_MNEMONIC(mov_Ev_Iz, "mov Ev,Iz"); 7314 7326 … … 7405 7417 uint8_t u8NestingLevel; IEM_OPCODE_GET_NEXT_U8(&u8NestingLevel); 7406 7418 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7407 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_enter, pVCpu->iem.s.enmEffOpSize, cbFrame, u8NestingLevel);7419 IEM_MC_DEFER_TO_CIMPL_3_RET(0, iemCImpl_enter, pVCpu->iem.s.enmEffOpSize, cbFrame, u8NestingLevel); 7408 7420 } 7409 7421 … … 7418 7430 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 7419 7431 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7420 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_leave, pVCpu->iem.s.enmEffOpSize);7432 IEM_MC_DEFER_TO_CIMPL_1_RET(0, iemCImpl_leave, pVCpu->iem.s.enmEffOpSize); 7421 7433 } 7422 7434 … … 7430 7442 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); 7431 7443 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7432 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, u16Imm);7444 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH, iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, u16Imm); 7433 7445 } 7434 7446 … … 7441 7453 IEMOP_MNEMONIC(retf, "retf"); 7442 7454 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7443 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, 0);7455 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH, iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, 0); 7444 7456 } 7445 7457 … … 7452 7464 IEMOP_MNEMONIC(int3, "int3"); 7453 7465 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7454 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_int, X86_XCPT_BP, IEMINT_INT3); 7466 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 7467 iemCImpl_int, X86_XCPT_BP, IEMINT_INT3); 7455 7468 } 7456 7469 … … 7464 7477 uint8_t u8Int; IEM_OPCODE_GET_NEXT_U8(&u8Int); 7465 7478 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7466 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_int, u8Int, IEMINT_INTN); 7479 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 7480 iemCImpl_int, u8Int, IEMINT_INTN); 7467 7481 } 7468 7482 … … 7475 7489 IEMOP_MNEMONIC(into, "into"); 7476 7490 IEMOP_HLP_NO_64BIT(); 7477 7478 IEM_MC_BEGIN(2, 0); 7479 IEM_MC_ARG_CONST(uint8_t, u8Int, /*=*/ X86_XCPT_OF, 0); 7480 IEM_MC_ARG_CONST(IEMINT, enmInt, /*=*/ IEMINT_INTO, 1); 7481 IEM_MC_CALL_CIMPL_2(iemCImpl_int, u8Int, enmInt); 7482 IEM_MC_END(); 7491 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 7492 iemCImpl_int, X86_XCPT_OF, IEMINT_INTO); 7483 7493 } 7484 7494 … … 7491 7501 IEMOP_MNEMONIC(iret, "iret"); 7492 7502 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7493 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_iret, pVCpu->iem.s.enmEffOpSize); 7503 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 7504 iemCImpl_iret, pVCpu->iem.s.enmEffOpSize); 7494 7505 } 7495 7506 … … 7511 7522 case 5: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shr_eflags); IEMOP_MNEMONIC(shr_Eb_1, "shr Eb,1"); break; 7512 7523 case 7: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_sar_eflags); IEMOP_MNEMONIC(sar_Eb_1, "sar Eb,1"); break; 7513 case 6: return IEMOP_RAISE_INVALID_OPCODE();7524 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 7514 7525 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe, well... */ 7515 7526 } … … 7570 7581 case 5: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shr_eflags); IEMOP_MNEMONIC(shr_Ev_1, "shr Ev,1"); break; 7571 7582 case 7: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_sar_eflags); IEMOP_MNEMONIC(sar_Ev_1, "sar Ev,1"); break; 7572 case 6: return IEMOP_RAISE_INVALID_OPCODE();7583 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 7573 7584 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe, well... */ 7574 7585 } … … 7705 7716 case 5: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shr_eflags); IEMOP_MNEMONIC(shr_Eb_CL, "shr Eb,CL"); break; 7706 7717 case 7: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_sar_eflags); IEMOP_MNEMONIC(sar_Eb_CL, "sar Eb,CL"); break; 7707 case 6: return IEMOP_RAISE_INVALID_OPCODE();7718 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 7708 7719 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc, grr. */ 7709 7720 } … … 7765 7776 case 5: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shr_eflags); IEMOP_MNEMONIC(shr_Ev_CL, "shr Ev,CL"); break; 7766 7777 case 7: pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_sar_eflags); IEMOP_MNEMONIC(sar_Ev_CL, "sar Ev,CL"); break; 7767 case 6: return IEMOP_RAISE_INVALID_OPCODE();7778 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 7768 7779 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe stupid */ 7769 7780 } … … 7899 7910 IEMOP_HLP_NO_64BIT(); 7900 7911 if (!bImm) 7901 return IEMOP_RAISE_DIVIDE_ERROR();7902 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_aam, bImm);7912 IEMOP_RAISE_DIVIDE_ERROR_RET(); 7913 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aam, bImm); 7903 7914 } 7904 7915 … … 7913 7924 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7914 7925 IEMOP_HLP_NO_64BIT(); 7915 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_aad, bImm);7926 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aad, bImm); 7916 7927 } 7917 7928 … … 8455 8466 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 8456 8467 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 8457 IEM_MC_CALL_CIMPL_3( iemCImpl_fldenv, enmEffOpSize, iEffSeg, GCPtrEffSrc);8468 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_fldenv, enmEffOpSize, iEffSeg, GCPtrEffSrc); 8458 8469 IEM_MC_END(); 8459 8470 } … … 8472 8483 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 8473 8484 IEM_MC_FETCH_MEM_U16(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 8474 IEM_MC_CALL_CIMPL_1( iemCImpl_fldcw, u16Fsw);8485 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_FPU, iemCImpl_fldcw, u16Fsw); 8475 8486 IEM_MC_END(); 8476 8487 } … … 8490 8501 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 8491 8502 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 8492 IEM_MC_CALL_CIMPL_3( iemCImpl_fnstenv, enmEffOpSize, iEffSeg, GCPtrEffDst);8503 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_fnstenv, enmEffOpSize, iEffSeg, GCPtrEffDst); 8493 8504 IEM_MC_END(); 8494 8505 } … … 8581 8592 IEM_MC_STORE_FPU_RESULT(FpuRes, 0); 8582 8593 } IEM_MC_ELSE() { 8583 IEM_MC_CALL_CIMPL_2( iemCImpl_fxch_underflow, iStReg, uFpuOpcode);8594 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, iemCImpl_fxch_underflow, iStReg, uFpuOpcode); 8584 8595 } IEM_MC_ENDIF(); 8585 8596 … … 9096 9107 if (bRm == 0xd0) 9097 9108 return FNIEMOP_CALL(iemOp_fnop); 9098 return IEMOP_RAISE_INVALID_OPCODE();9109 IEMOP_RAISE_INVALID_OPCODE_RET(); 9099 9110 case 3: return FNIEMOP_CALL_1(iemOp_fstp_stN, bRm); /* Reserved. Intel behavior seems to be FSTP ST(i) though. */ 9100 9111 case 4: … … 9112 9123 { 9113 9124 case 0: return FNIEMOP_CALL_1(iemOp_fld_m32r, bRm); 9114 case 1: return IEMOP_RAISE_INVALID_OPCODE();9125 case 1: IEMOP_RAISE_INVALID_OPCODE_RET(); 9115 9126 case 2: return FNIEMOP_CALL_1(iemOp_fst_m32r, bRm); 9116 9127 case 3: return FNIEMOP_CALL_1(iemOp_fstp_m32r, bRm); … … 9439 9450 case 2: return FNIEMOP_CALL_1(iemOp_fcmovbe_stN, bRm); 9440 9451 case 3: return FNIEMOP_CALL_1(iemOp_fcmovu_stN, bRm); 9441 case 4: return IEMOP_RAISE_INVALID_OPCODE();9452 case 4: IEMOP_RAISE_INVALID_OPCODE_RET(); 9442 9453 case 5: 9443 9454 if (bRm == 0xe9) 9444 9455 return FNIEMOP_CALL(iemOp_fucompp); 9445 return IEMOP_RAISE_INVALID_OPCODE();9446 case 6: return IEMOP_RAISE_INVALID_OPCODE();9447 case 7: return IEMOP_RAISE_INVALID_OPCODE();9456 IEMOP_RAISE_INVALID_OPCODE_RET(); 9457 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 9458 case 7: IEMOP_RAISE_INVALID_OPCODE_RET(); 9448 9459 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 9449 9460 } … … 9823 9834 IEMOP_MNEMONIC(fninit, "fninit"); 9824 9835 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9825 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_finit, false /*fCheckXcpts*/);9836 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, iemCImpl_finit, false /*fCheckXcpts*/); 9826 9837 } 9827 9838 … … 9851 9862 return VINF_SUCCESS; 9852 9863 #else 9853 return IEMOP_RAISE_INVALID_OPCODE();9864 IEMOP_RAISE_INVALID_OPCODE_RET(); 9854 9865 #endif 9855 9866 } … … 9860 9871 { 9861 9872 IEMOP_MNEMONIC(fucomi_st0_stN, "fucomi st0,stN"); 9862 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fucomi_r80_by_r80, 9863 0 /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 9873 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 9874 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fucomi_r80_by_r80, 9875 0 /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 9864 9876 } 9865 9877 … … 9869 9881 { 9870 9882 IEMOP_MNEMONIC(fcomi_st0_stN, "fcomi st0,stN"); 9871 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 9872 false /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 9883 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 9884 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 9885 false /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 9873 9886 } 9874 9887 … … 9898 9911 case 0xe4: return FNIEMOP_CALL(iemOp_fnsetpm); 9899 9912 case 0xe5: return FNIEMOP_CALL(iemOp_frstpm); 9900 case 0xe6: return IEMOP_RAISE_INVALID_OPCODE();9901 case 0xe7: return IEMOP_RAISE_INVALID_OPCODE();9913 case 0xe6: IEMOP_RAISE_INVALID_OPCODE_RET(); 9914 case 0xe7: IEMOP_RAISE_INVALID_OPCODE_RET(); 9902 9915 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 9903 9916 } … … 9905 9918 case 5: return FNIEMOP_CALL_1(iemOp_fucomi_stN, bRm); 9906 9919 case 6: return FNIEMOP_CALL_1(iemOp_fcomi_stN, bRm); 9907 case 7: return IEMOP_RAISE_INVALID_OPCODE();9920 case 7: IEMOP_RAISE_INVALID_OPCODE_RET(); 9908 9921 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 9909 9922 } … … 9917 9930 case 2: return FNIEMOP_CALL_1(iemOp_fist_m32i, bRm); 9918 9931 case 3: return FNIEMOP_CALL_1(iemOp_fistp_m32i, bRm); 9919 case 4: return IEMOP_RAISE_INVALID_OPCODE();9932 case 4: IEMOP_RAISE_INVALID_OPCODE_RET(); 9920 9933 case 5: return FNIEMOP_CALL_1(iemOp_fld_m80r, bRm); 9921 case 6: return IEMOP_RAISE_INVALID_OPCODE();9934 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 9922 9935 case 7: return FNIEMOP_CALL_1(iemOp_fstp_m80r, bRm); 9923 9936 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 10350 10363 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 10351 10364 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 10352 IEM_MC_CALL_CIMPL_3( iemCImpl_frstor, enmEffOpSize, iEffSeg, GCPtrEffSrc);10365 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_frstor, enmEffOpSize, iEffSeg, GCPtrEffSrc); 10353 10366 IEM_MC_END(); 10354 10367 } … … 10368 10381 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); /* Note! Implicit fninit after the save, do not use FOR_READ here! */ 10369 10382 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 10370 IEM_MC_CALL_CIMPL_3( iemCImpl_fnsave, enmEffOpSize, iEffSeg, GCPtrEffDst);10383 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_fnsave, enmEffOpSize, iEffSeg, GCPtrEffDst); 10371 10384 IEM_MC_END(); 10372 10385 } … … 10477 10490 case 4: return FNIEMOP_CALL_1(iemOp_fucom_stN_st0,bRm); 10478 10491 case 5: return FNIEMOP_CALL_1(iemOp_fucomp_stN, bRm); 10479 case 6: return IEMOP_RAISE_INVALID_OPCODE();10480 case 7: return IEMOP_RAISE_INVALID_OPCODE();10492 case 6: IEMOP_RAISE_INVALID_OPCODE_RET(); 10493 case 7: IEMOP_RAISE_INVALID_OPCODE_RET(); 10481 10494 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 10482 10495 } … … 10491 10504 case 3: return FNIEMOP_CALL_1(iemOp_fstp_m64r, bRm); 10492 10505 case 4: return FNIEMOP_CALL_1(iemOp_frstor, bRm); 10493 case 5: return IEMOP_RAISE_INVALID_OPCODE();10506 case 5: IEMOP_RAISE_INVALID_OPCODE_RET(); 10494 10507 case 6: return FNIEMOP_CALL_1(iemOp_fnsave, bRm); 10495 10508 case 7: return FNIEMOP_CALL_1(iemOp_fnstsw, bRm); … … 10723 10736 case 3: if (bRm == 0xd9) 10724 10737 return FNIEMOP_CALL(iemOp_fcompp); 10725 return IEMOP_RAISE_INVALID_OPCODE();10738 IEMOP_RAISE_INVALID_OPCODE_RET(); 10726 10739 case 4: return FNIEMOP_CALL_1(iemOp_fsubrp_stN_st0, bRm); 10727 10740 case 5: return FNIEMOP_CALL_1(iemOp_fsubp_stN_st0, bRm); … … 10792 10805 { 10793 10806 IEMOP_MNEMONIC(fucomip_st0_stN, "fucomip st0,stN"); 10794 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 10795 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 10807 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 10808 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 10809 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 10796 10810 } 10797 10811 … … 10801 10815 { 10802 10816 IEMOP_MNEMONIC(fcomip_st0_stN, "fcomip st0,stN"); 10803 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 10804 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 10817 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 10818 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 10819 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 10805 10820 } 10806 10821 … … 11093 11108 case 4: if (bRm == 0xe0) 11094 11109 return FNIEMOP_CALL(iemOp_fnstsw_ax); 11095 return IEMOP_RAISE_INVALID_OPCODE();11110 IEMOP_RAISE_INVALID_OPCODE_RET(); 11096 11111 case 5: return FNIEMOP_CALL_1(iemOp_fucomip_st0_stN, bRm); 11097 11112 case 6: return FNIEMOP_CALL_1(iemOp_fcomip_st0_stN, bRm); 11098 case 7: return IEMOP_RAISE_INVALID_OPCODE();11113 case 7: IEMOP_RAISE_INVALID_OPCODE_RET(); 11099 11114 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 11100 11115 } … … 11359 11374 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11360 11375 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11361 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_in, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode);11376 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_in, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11362 11377 } 11363 11378 … … 11369 11384 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11370 11385 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11371 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4,11372 11386 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11387 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11373 11388 } 11374 11389 … … 11380 11395 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11381 11396 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11382 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_out, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode);11397 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_out, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11383 11398 } 11384 11399 … … 11390 11405 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11391 11406 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11392 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4,11393 11407 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11408 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11394 11409 } 11395 11410 … … 11407 11422 { 11408 11423 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); 11409 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_call_rel_16, (int16_t)u16Imm);11424 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH, iemCImpl_call_rel_16, (int16_t)u16Imm); 11410 11425 } 11411 11426 … … 11413 11428 { 11414 11429 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); 11415 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_call_rel_32, (int32_t)u32Imm);11430 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH, iemCImpl_call_rel_32, (int32_t)u32Imm); 11416 11431 } 11417 11432 … … 11419 11434 { 11420 11435 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); 11421 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_call_rel_64, u64Imm);11436 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH, iemCImpl_call_rel_64, u64Imm); 11422 11437 } 11423 11438 … … 11476 11491 uint16_t uSel; IEM_OPCODE_GET_NEXT_U16(&uSel); 11477 11492 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11478 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_FarJmp, uSel, offSeg, pVCpu->iem.s.enmEffOpSize); 11493 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 11494 iemCImpl_FarJmp, uSel, offSeg, pVCpu->iem.s.enmEffOpSize); 11479 11495 } 11480 11496 … … 11501 11517 IEMOP_MNEMONIC(in_AL_DX, "in AL,DX"); 11502 11518 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11503 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_in_eAX_DX, 1, pVCpu->iem.s.enmEffAddrMode);11519 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_in_eAX_DX, 1, pVCpu->iem.s.enmEffAddrMode); 11504 11520 } 11505 11521 … … 11510 11526 IEMOP_MNEMONIC(in_eAX_DX, "in eAX,DX"); 11511 11527 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11512 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11513 pVCpu->iem.s.enmEffAddrMode); 11528 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 11529 iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11530 pVCpu->iem.s.enmEffAddrMode); 11514 11531 } 11515 11532 … … 11520 11537 IEMOP_MNEMONIC(out_DX_AL, "out DX,AL"); 11521 11538 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11522 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_out_DX_eAX, 1, pVCpu->iem.s.enmEffAddrMode);11539 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_out_DX_eAX, 1, pVCpu->iem.s.enmEffAddrMode); 11523 11540 } 11524 11541 … … 11529 11546 IEMOP_MNEMONIC(out_DX_eAX, "out DX,eAX"); 11530 11547 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11531 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11532 pVCpu->iem.s.enmEffAddrMode); 11548 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 11549 iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11550 pVCpu->iem.s.enmEffAddrMode); 11533 11551 } 11534 11552 … … 11559 11577 IEMOP_HLP_MIN_386(); 11560 11578 /** @todo testcase! */ 11561 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_int, X86_XCPT_DB, IEMINT_INT1); 11579 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 11580 iemCImpl_int, X86_XCPT_DB, IEMINT_INT1); 11562 11581 } 11563 11582 … … 11608 11627 IEMOP_MNEMONIC(hlt, "hlt"); 11609 11628 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11610 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_hlt);11629 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_END_TB | IEM_CIMPL_F_VMEXIT, iemCImpl_hlt); 11611 11630 } 11612 11631 … … 12433 12452 IEMOP_MNEMONIC(cli, "cli"); 12434 12453 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12435 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_cli);12454 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, iemCImpl_cli); 12436 12455 } 12437 12456 … … 12441 12460 IEMOP_MNEMONIC(sti, "sti"); 12442 12461 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12443 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_sti);12462 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, iemCImpl_sti); 12444 12463 } 12445 12464 … … 12508 12527 /** @todo is the eff-addr decoded? */ 12509 12528 IEMOP_MNEMONIC(grp4_ud, "grp4-ud"); 12510 return IEMOP_RAISE_INVALID_OPCODE();12529 IEMOP_RAISE_INVALID_OPCODE_RET(); 12511 12530 } 12512 12531 } … … 12549 12568 IEM_MC_ARG(uint16_t, u16Target, 0); 12550 12569 IEM_MC_FETCH_GREG_U16(u16Target, IEM_GET_MODRM_RM(pVCpu, bRm)); 12551 IEM_MC_CALL_CIMPL_1( iemCImpl_call_16, u16Target);12570 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH, iemCImpl_call_16, u16Target); 12552 12571 IEM_MC_END(); 12553 12572 break; … … 12557 12576 IEM_MC_ARG(uint32_t, u32Target, 0); 12558 12577 IEM_MC_FETCH_GREG_U32(u32Target, IEM_GET_MODRM_RM(pVCpu, bRm)); 12559 IEM_MC_CALL_CIMPL_1( iemCImpl_call_32, u32Target);12578 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH, iemCImpl_call_32, u32Target); 12560 12579 IEM_MC_END(); 12561 12580 break; … … 12565 12584 IEM_MC_ARG(uint64_t, u64Target, 0); 12566 12585 IEM_MC_FETCH_GREG_U64(u64Target, IEM_GET_MODRM_RM(pVCpu, bRm)); 12567 IEM_MC_CALL_CIMPL_1( iemCImpl_call_64, u64Target);12586 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH, iemCImpl_call_64, u64Target); 12568 12587 IEM_MC_END(); 12569 12588 break; … … 12584 12603 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12585 12604 IEM_MC_FETCH_MEM_U16(u16Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12586 IEM_MC_CALL_CIMPL_1( iemCImpl_call_16, u16Target);12605 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH, iemCImpl_call_16, u16Target); 12587 12606 IEM_MC_END(); 12588 12607 break; … … 12595 12614 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12596 12615 IEM_MC_FETCH_MEM_U32(u32Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12597 IEM_MC_CALL_CIMPL_1( iemCImpl_call_32, u32Target);12616 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH, iemCImpl_call_32, u32Target); 12598 12617 IEM_MC_END(); 12599 12618 break; … … 12606 12625 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12607 12626 IEM_MC_FETCH_MEM_U64(u64Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12608 IEM_MC_CALL_CIMPL_1( iemCImpl_call_64, u64Target);12627 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH, iemCImpl_call_64, u64Target); 12609 12628 IEM_MC_END(); 12610 12629 break; … … 12615 12634 } 12616 12635 12617 FNIEMOP_DEF_2(iemOpHlp_Grp5_far_Ep, uint8_t, bRm, PFNIEMCIMPLFARBRANCH, pfnCImpl) 12618 { 12619 /* Registers? How?? */ 12620 if (RT_LIKELY(IEM_IS_MODRM_MEM_MODE(bRm))) 12621 { /* likely */ } 12622 else 12623 return IEMOP_RAISE_INVALID_OPCODE(); /* callf eax is not legal */ 12624 12625 /* 64-bit mode: Default is 32-bit, but only intel respects a REX.W prefix. */ 12626 /** @todo what does VIA do? */ 12627 if (!IEM_IS_64BIT_CODE(pVCpu) || pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT || IEM_IS_GUEST_CPU_INTEL(pVCpu)) 12628 { /* likely */ } 12629 else 12630 pVCpu->iem.s.enmEffOpSize = IEMMODE_32BIT; 12631 12632 /* Far pointer loaded from memory. */ 12633 switch (pVCpu->iem.s.enmEffOpSize) 12634 { 12635 case IEMMODE_16BIT: 12636 IEM_MC_BEGIN(3, 1); 12637 IEM_MC_ARG(uint16_t, u16Sel, 0); 12638 IEM_MC_ARG(uint16_t, offSeg, 1); 12639 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_16BIT, 2); 12640 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 12641 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 12642 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12643 IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12644 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 2); 12645 IEM_MC_CALL_CIMPL_3(pfnCImpl, u16Sel, offSeg, enmEffOpSize); 12646 IEM_MC_END(); 12647 break; 12648 12649 case IEMMODE_32BIT: 12650 IEM_MC_BEGIN(3, 1); 12651 IEM_MC_ARG(uint16_t, u16Sel, 0); 12652 IEM_MC_ARG(uint32_t, offSeg, 1); 12653 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_32BIT, 2); 12654 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 12655 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 12656 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12657 IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12658 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 4); 12659 IEM_MC_CALL_CIMPL_3(pfnCImpl, u16Sel, offSeg, enmEffOpSize); 12660 IEM_MC_END(); 12661 break; 12662 12663 case IEMMODE_64BIT: 12664 Assert(!IEM_IS_GUEST_CPU_AMD(pVCpu)); 12665 IEM_MC_BEGIN(3, 1); 12666 IEM_MC_ARG(uint16_t, u16Sel, 0); 12667 IEM_MC_ARG(uint64_t, offSeg, 1); 12668 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_64BIT, 2); 12669 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 12670 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 12671 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12672 IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12673 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 8); 12674 IEM_MC_CALL_CIMPL_3(pfnCImpl, u16Sel, offSeg, enmEffOpSize); 12675 IEM_MC_END(); 12676 break; 12677 12678 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 12679 } 12680 } 12636 #define IEMOP_BODY_GRP5_FAR_EP(a_bRm, a_fnCImpl) \ 12637 /* Registers? How?? */ \ 12638 if (RT_LIKELY(IEM_IS_MODRM_MEM_MODE(a_bRm))) \ 12639 { /* likely */ } \ 12640 else \ 12641 IEMOP_RAISE_INVALID_OPCODE_RET(); /* callf eax is not legal */ \ 12642 \ 12643 /* 64-bit mode: Default is 32-bit, but only intel respects a REX.W prefix. */ \ 12644 /** @todo what does VIA do? */ \ 12645 if (!IEM_IS_64BIT_CODE(pVCpu) || pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT || IEM_IS_GUEST_CPU_INTEL(pVCpu)) \ 12646 { /* likely */ } \ 12647 else \ 12648 pVCpu->iem.s.enmEffOpSize = IEMMODE_32BIT; \ 12649 \ 12650 /* Far pointer loaded from memory. */ \ 12651 switch (pVCpu->iem.s.enmEffOpSize) \ 12652 { \ 12653 case IEMMODE_16BIT: \ 12654 IEM_MC_BEGIN(3, 1); \ 12655 IEM_MC_ARG(uint16_t, u16Sel, 0); \ 12656 IEM_MC_ARG(uint16_t, offSeg, 1); \ 12657 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_16BIT, 2); \ 12658 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \ 12659 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, a_bRm, 0); \ 12660 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 12661 IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \ 12662 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 2); \ 12663 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, \ 12664 a_fnCImpl, u16Sel, offSeg, enmEffOpSize); \ 12665 IEM_MC_END(); \ 12666 break; \ 12667 \ 12668 case IEMMODE_32BIT: \ 12669 IEM_MC_BEGIN(3, 1); \ 12670 IEM_MC_ARG(uint16_t, u16Sel, 0); \ 12671 IEM_MC_ARG(uint32_t, offSeg, 1); \ 12672 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_32BIT, 2); \ 12673 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \ 12674 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, a_bRm, 0); \ 12675 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 12676 IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \ 12677 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 4); \ 12678 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, \ 12679 a_fnCImpl, u16Sel, offSeg, enmEffOpSize); \ 12680 IEM_MC_END(); \ 12681 break; \ 12682 \ 12683 case IEMMODE_64BIT: \ 12684 Assert(!IEM_IS_GUEST_CPU_AMD(pVCpu)); \ 12685 IEM_MC_BEGIN(3, 1); \ 12686 IEM_MC_ARG(uint16_t, u16Sel, 0); \ 12687 IEM_MC_ARG(uint64_t, offSeg, 1); \ 12688 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_64BIT, 2); \ 12689 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \ 12690 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, a_bRm, 0); \ 12691 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 12692 IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \ 12693 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 8); \ 12694 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_MODE /* no gates */, \ 12695 a_fnCImpl, u16Sel, offSeg, enmEffOpSize); \ 12696 IEM_MC_END(); \ 12697 break; \ 12698 \ 12699 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 12700 } do {} while (0) 12681 12701 12682 12702 … … 12688 12708 { 12689 12709 IEMOP_MNEMONIC(callf_Ep, "callf Ep"); 12690 return FNIEMOP_CALL_2(iemOpHlp_Grp5_far_Ep,bRm, iemCImpl_callf);12710 IEMOP_BODY_GRP5_FAR_EP(bRm, iemCImpl_callf); 12691 12711 } 12692 12712 … … 12785 12805 { 12786 12806 IEMOP_MNEMONIC(jmpf_Ep, "jmpf Ep"); 12787 return FNIEMOP_CALL_2(iemOpHlp_Grp5_far_Ep,bRm, iemCImpl_FarJmp);12807 IEMOP_BODY_GRP5_FAR_EP(bRm, iemCImpl_FarJmp); 12788 12808 } 12789 12809 … … 12870 12890 case 7: 12871 12891 IEMOP_MNEMONIC(grp5_ud, "grp5-ud"); 12872 return IEMOP_RAISE_INVALID_OPCODE();12892 IEMOP_RAISE_INVALID_OPCODE_RET(); 12873 12893 } 12874 12894 AssertFailedReturn(VERR_IEM_IPE_3); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThreadedRecompiler.cpp
r100061 r100072 243 243 * IEMOP_RAISE_INVALID_OPCODE and their users. 244 244 */ 245 #undef IEM_MC_DEFER_TO_CIMPL_0 246 #define IEM_MC_DEFER_TO_CIMPL_0 (a_pfnCImpl)iemThreadedRecompilerMcDeferToCImpl0(pVCpu, a_pfnCImpl)245 #undef IEM_MC_DEFER_TO_CIMPL_0_RET 246 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) return iemThreadedRecompilerMcDeferToCImpl0(pVCpu, a_pfnCImpl) 247 247 248 248 typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h
r99342 r100072 1066 1066 */ 1067 1067 else 1068 return IEMOP_RAISE_INVALID_OPCODE();1068 IEMOP_RAISE_INVALID_OPCODE_RET(); 1069 1069 } 1070 1070 … … 1326 1326 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0); 1327 1327 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1328 IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType); 1328 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 1329 iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType); 1329 1330 IEM_MC_END(); 1330 1331 } … … 1338 1339 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0); 1339 1340 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1340 IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType); 1341 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 1342 iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType); 1341 1343 IEM_MC_END(); 1342 1344 } 1343 1345 } 1344 1346 Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n")); 1345 return IEMOP_RAISE_INVALID_OPCODE();1347 IEMOP_RAISE_INVALID_OPCODE_RET(); 1346 1348 } 1347 1349 #else … … 1370 1372 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0); 1371 1373 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1372 IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType); 1374 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 1375 iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType); 1373 1376 IEM_MC_END(); 1374 1377 } … … 1382 1385 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0); 1383 1386 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1384 IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType); 1387 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 1388 iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType); 1385 1389 IEM_MC_END(); 1386 1390 } 1387 1391 } 1388 1392 Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n")); 1389 return IEMOP_RAISE_INVALID_OPCODE();1393 IEMOP_RAISE_INVALID_OPCODE_RET(); 1390 1394 } 1391 1395 #else … … 1411 1415 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0); 1412 1416 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1413 IEM_MC_CALL_CIMPL_3( iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);1417 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType); 1414 1418 IEM_MC_END(); 1415 1419 } … … 1423 1427 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0); 1424 1428 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1425 IEM_MC_CALL_CIMPL_3( iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);1429 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType); 1426 1430 IEM_MC_END(); 1427 1431 } 1428 1432 } 1429 1433 Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n")); 1430 return IEMOP_RAISE_INVALID_OPCODE();1434 IEMOP_RAISE_INVALID_OPCODE_RET(); 1431 1435 } 1432 1436 … … 1779 1783 { 1780 1784 /* Reg/reg not supported. */ 1781 return IEMOP_RAISE_INVALID_OPCODE();1785 IEMOP_RAISE_INVALID_OPCODE_RET(); 1782 1786 } 1783 1787 } … … 1895 1899 { 1896 1900 /* Reg/reg not supported. */ 1897 return IEMOP_RAISE_INVALID_OPCODE();1901 IEMOP_RAISE_INVALID_OPCODE_RET(); 1898 1902 } 1899 1903 } -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r100052 r100072 1200 1200 { 1201 1201 IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1202 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_sldt_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize);1202 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_sldt_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1203 1203 } 1204 1204 … … 1210 1210 IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1211 1211 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1212 IEM_MC_CALL_CIMPL_2( iemCImpl_sldt_mem, iEffSeg, GCPtrEffDst);1212 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_sldt_mem, iEffSeg, GCPtrEffDst); 1213 1213 IEM_MC_END(); 1214 1214 } … … 1226 1226 { 1227 1227 IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1228 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_str_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize);1228 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_str_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1229 1229 } 1230 1230 … … 1236 1236 IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1237 1237 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1238 IEM_MC_CALL_CIMPL_2( iemCImpl_str_mem, iEffSeg, GCPtrEffDst);1238 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_str_mem, iEffSeg, GCPtrEffDst); 1239 1239 IEM_MC_END(); 1240 1240 } … … 1254 1254 IEM_MC_ARG(uint16_t, u16Sel, 0); 1255 1255 IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm)); 1256 IEM_MC_CALL_CIMPL_1( iemCImpl_lldt, u16Sel);1256 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_VMEXIT, iemCImpl_lldt, u16Sel); 1257 1257 IEM_MC_END(); 1258 1258 } … … 1266 1266 IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test order */ 1267 1267 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1268 IEM_MC_CALL_CIMPL_1( iemCImpl_lldt, u16Sel);1268 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_VMEXIT, iemCImpl_lldt, u16Sel); 1269 1269 IEM_MC_END(); 1270 1270 } … … 1285 1285 IEM_MC_ARG(uint16_t, u16Sel, 0); 1286 1286 IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm)); 1287 IEM_MC_CALL_CIMPL_1( iemCImpl_ltr, u16Sel);1287 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_VMEXIT, iemCImpl_ltr, u16Sel); 1288 1288 IEM_MC_END(); 1289 1289 } … … 1297 1297 IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test order */ 1298 1298 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1299 IEM_MC_CALL_CIMPL_1( iemCImpl_ltr, u16Sel);1299 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_VMEXIT, iemCImpl_ltr, u16Sel); 1300 1300 IEM_MC_END(); 1301 1301 } … … 1316 1316 IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1); 1317 1317 IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm)); 1318 IEM_MC_CALL_CIMPL_2( iemCImpl_VerX, u16Sel, fWriteArg);1318 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_VerX, u16Sel, fWriteArg); 1319 1319 IEM_MC_END(); 1320 1320 } … … 1328 1328 IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1329 1329 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1330 IEM_MC_CALL_CIMPL_2( iemCImpl_VerX, u16Sel, fWriteArg);1330 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_VerX, u16Sel, fWriteArg); 1331 1331 IEM_MC_END(); 1332 1332 } … … 1387 1387 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1388 1388 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1389 IEM_MC_CALL_CIMPL_2( iemCImpl_sgdt, iEffSeg, GCPtrEffSrc);1389 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_sgdt, iEffSeg, GCPtrEffSrc); 1390 1390 IEM_MC_END(); 1391 1391 } … … 1402 1402 hypercall isn't handled by GIM or HMSvm will raise an #UD. 1403 1403 (NEM/win makes ASSUMPTIONS about this behavior.) */ 1404 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmcall);1404 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, iemCImpl_vmcall); 1405 1405 } 1406 1406 … … 1414 1414 IEMOP_HLP_VMX_INSTR("vmlaunch", kVmxVDiag_Vmentry); 1415 1415 IEMOP_HLP_DONE_DECODING(); 1416 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmlaunch); 1416 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 1417 iemCImpl_vmlaunch); 1417 1418 } 1418 1419 #else … … 1420 1421 { 1421 1422 IEMOP_BITCH_ABOUT_STUB(); 1422 return IEMOP_RAISE_INVALID_OPCODE();1423 IEMOP_RAISE_INVALID_OPCODE_RET(); 1423 1424 } 1424 1425 #endif … … 1433 1434 IEMOP_HLP_VMX_INSTR("vmresume", kVmxVDiag_Vmentry); 1434 1435 IEMOP_HLP_DONE_DECODING(); 1435 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmresume); 1436 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 1437 iemCImpl_vmresume); 1436 1438 } 1437 1439 #else … … 1439 1441 { 1440 1442 IEMOP_BITCH_ABOUT_STUB(); 1441 return IEMOP_RAISE_INVALID_OPCODE();1443 IEMOP_RAISE_INVALID_OPCODE_RET(); 1442 1444 } 1443 1445 #endif … … 1452 1454 IEMOP_HLP_VMX_INSTR("vmxoff", kVmxVDiag_Vmxoff); 1453 1455 IEMOP_HLP_DONE_DECODING(); 1454 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmxoff);1456 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmxoff); 1455 1457 } 1456 1458 #else … … 1458 1460 { 1459 1461 IEMOP_BITCH_ABOUT_STUB(); 1460 return IEMOP_RAISE_INVALID_OPCODE();1462 IEMOP_RAISE_INVALID_OPCODE_RET(); 1461 1463 } 1462 1464 #endif … … 1475 1477 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1476 1478 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1477 IEM_MC_CALL_CIMPL_2( iemCImpl_sidt, iEffSeg, GCPtrEffSrc);1479 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_sidt, iEffSeg, GCPtrEffSrc); 1478 1480 IEM_MC_END(); 1479 1481 } … … 1485 1487 IEMOP_MNEMONIC(monitor, "monitor"); 1486 1488 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo Verify that monitor is allergic to lock prefixes. */ 1487 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_monitor, pVCpu->iem.s.iEffSeg);1489 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_monitor, pVCpu->iem.s.iEffSeg); 1488 1490 } 1489 1491 … … 1494 1496 IEMOP_MNEMONIC(mwait, "mwait"); /** @todo Verify that mwait is allergic to lock prefixes. */ 1495 1497 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1496 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_mwait);1498 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_END_TB | IEM_CIMPL_F_VMEXIT, iemCImpl_mwait); 1497 1499 } 1498 1500 … … 1510 1512 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1511 1513 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1512 IEM_MC_CALL_CIMPL_3( iemCImpl_lgdt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);1514 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, iemCImpl_lgdt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg); 1513 1515 IEM_MC_END(); 1514 1516 } … … 1525 1527 * IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES here. */ 1526 1528 IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); 1527 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xgetbv);1528 } 1529 return IEMOP_RAISE_INVALID_OPCODE();1529 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_xgetbv); 1530 } 1531 IEMOP_RAISE_INVALID_OPCODE_RET(); 1530 1532 } 1531 1533 … … 1541 1543 * IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES here. */ 1542 1544 IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); 1543 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xsetbv);1544 } 1545 return IEMOP_RAISE_INVALID_OPCODE();1545 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_xsetbv); 1546 } 1547 IEMOP_RAISE_INVALID_OPCODE_RET(); 1546 1548 } 1547 1549 … … 1559 1561 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1560 1562 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1561 IEM_MC_CALL_CIMPL_3( iemCImpl_lidt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);1563 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, iemCImpl_lidt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg); 1562 1564 IEM_MC_END(); 1563 1565 } … … 1570 1572 IEMOP_MNEMONIC(vmrun, "vmrun"); 1571 1573 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1572 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmrun); 1574 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 1575 iemCImpl_vmrun); 1573 1576 } 1574 1577 #else … … 1586 1589 hypercall isn't handled by GIM or HMSvm will raise an #UD. 1587 1590 (NEM/win makes ASSUMPTIONS about this behavior.) */ 1588 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmmcall);1591 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmmcall); 1589 1592 } 1590 1593 … … 1595 1598 IEMOP_MNEMONIC(vmload, "vmload"); 1596 1599 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1597 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmload);1600 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmload); 1598 1601 } 1599 1602 #else … … 1608 1611 IEMOP_MNEMONIC(vmsave, "vmsave"); 1609 1612 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1610 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmsave);1613 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmsave); 1611 1614 } 1612 1615 #else … … 1621 1624 IEMOP_MNEMONIC(stgi, "stgi"); 1622 1625 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1623 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stgi);1626 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_stgi); 1624 1627 } 1625 1628 #else … … 1634 1637 IEMOP_MNEMONIC(clgi, "clgi"); 1635 1638 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1636 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clgi);1639 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_clgi); 1637 1640 } 1638 1641 #else … … 1647 1650 IEMOP_MNEMONIC(invlpga, "invlpga"); 1648 1651 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1649 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_invlpga);1652 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_invlpga); 1650 1653 } 1651 1654 #else … … 1660 1663 IEMOP_MNEMONIC(skinit, "skinit"); 1661 1664 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1662 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_skinit);1665 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_skinit); 1663 1666 } 1664 1667 #else … … 1675 1678 { 1676 1679 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1677 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_smsw_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize);1680 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_smsw_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1678 1681 } 1679 1682 … … 1685 1688 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1686 1689 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 1687 IEM_MC_CALL_CIMPL_2( iemCImpl_smsw_mem, iEffSeg, GCPtrEffDst);1690 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_smsw_mem, iEffSeg, GCPtrEffDst); 1688 1691 IEM_MC_END(); 1689 1692 } … … 1704 1707 IEM_MC_ARG_CONST(RTGCPTR, GCPtrEffDst, NIL_RTGCPTR, 1); 1705 1708 IEM_MC_FETCH_GREG_U16(u16Tmp, IEM_GET_MODRM_RM(pVCpu, bRm)); 1706 IEM_MC_CALL_CIMPL_2( iemCImpl_lmsw, u16Tmp, GCPtrEffDst);1709 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, iemCImpl_lmsw, u16Tmp, GCPtrEffDst); 1707 1710 IEM_MC_END(); 1708 1711 } … … 1715 1718 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1716 1719 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1717 IEM_MC_CALL_CIMPL_2( iemCImpl_lmsw, u16Tmp, GCPtrEffDst);1720 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, iemCImpl_lmsw, u16Tmp, GCPtrEffDst); 1718 1721 IEM_MC_END(); 1719 1722 } … … 1730 1733 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 0); 1731 1734 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1732 IEM_MC_CALL_CIMPL_1( iemCImpl_invlpg, GCPtrEffDst);1735 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_VMEXIT, iemCImpl_invlpg, GCPtrEffDst); 1733 1736 IEM_MC_END(); 1734 1737 } … … 1741 1744 IEMOP_HLP_ONLY_64BIT(); 1742 1745 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1743 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_swapgs);1746 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_swapgs); 1744 1747 } 1745 1748 … … 1750 1753 IEMOP_MNEMONIC(rdtscp, "rdtscp"); 1751 1754 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1752 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdtscp);1755 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdtscp); 1753 1756 } 1754 1757 … … 1787 1790 case 4: return FNIEMOP_CALL(iemOp_Grp7_vmxoff); 1788 1791 } 1789 return IEMOP_RAISE_INVALID_OPCODE();1792 IEMOP_RAISE_INVALID_OPCODE_RET(); 1790 1793 1791 1794 case 1: … … 1795 1798 case 1: return FNIEMOP_CALL(iemOp_Grp7_mwait); 1796 1799 } 1797 return IEMOP_RAISE_INVALID_OPCODE();1800 IEMOP_RAISE_INVALID_OPCODE_RET(); 1798 1801 1799 1802 case 2: … … 1803 1806 case 1: return FNIEMOP_CALL(iemOp_Grp7_xsetbv); 1804 1807 } 1805 return IEMOP_RAISE_INVALID_OPCODE();1808 IEMOP_RAISE_INVALID_OPCODE_RET(); 1806 1809 1807 1810 case 3: … … 1823 1826 1824 1827 case 5: 1825 return IEMOP_RAISE_INVALID_OPCODE();1828 IEMOP_RAISE_INVALID_OPCODE_RET(); 1826 1829 1827 1830 case 6: … … 1834 1837 case 1: return FNIEMOP_CALL(iemOp_Grp7_rdtscp); 1835 1838 } 1836 return IEMOP_RAISE_INVALID_OPCODE();1839 IEMOP_RAISE_INVALID_OPCODE_RET(); 1837 1840 1838 1841 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 1860 1863 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1861 1864 IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm)); 1862 IEM_MC_CALL_CIMPL_3( iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg);1865 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg); 1863 1866 1864 1867 IEM_MC_END(); … … 1875 1878 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1876 1879 IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm)); 1877 IEM_MC_CALL_CIMPL_3( iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg);1880 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg); 1878 1881 1879 1882 IEM_MC_END(); … … 1900 1903 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1901 1904 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1902 IEM_MC_CALL_CIMPL_3( iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg);1905 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg); 1903 1906 1904 1907 IEM_MC_END(); … … 1920 1923 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1921 1924 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1922 IEM_MC_CALL_CIMPL_3( iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg);1925 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg); 1923 1926 1924 1927 IEM_MC_END(); … … 1953 1956 IEMOP_MNEMONIC(syscall, "syscall"); /** @todo 286 LOADALL */ 1954 1957 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1955 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_syscall); 1958 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 1959 iemCImpl_syscall); 1956 1960 } 1957 1961 … … 1962 1966 IEMOP_MNEMONIC(clts, "clts"); 1963 1967 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1964 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clts);1968 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_clts); 1965 1969 } 1966 1970 … … 1971 1975 IEMOP_MNEMONIC(sysret, "sysret"); /** @todo 386 LOADALL */ 1972 1976 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1973 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_sysret, pVCpu->iem.s.enmEffOpSize); 1977 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 1978 iemCImpl_sysret, pVCpu->iem.s.enmEffOpSize); 1974 1979 } 1975 1980 … … 1981 1986 IEMOP_HLP_MIN_486(); 1982 1987 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1983 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_invd);1988 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_invd); 1984 1989 } 1985 1990 … … 1991 1996 IEMOP_HLP_MIN_486(); 1992 1997 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1993 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_wbinvd);1998 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_wbinvd); 1994 1999 } 1995 2000 … … 1999 2004 { 2000 2005 IEMOP_MNEMONIC(ud2, "ud2"); 2001 return IEMOP_RAISE_INVALID_OPCODE();2006 IEMOP_RAISE_INVALID_OPCODE_RET(); 2002 2007 } 2003 2008 … … 2009 2014 { 2010 2015 IEMOP_MNEMONIC(GrpPNotSupported, "GrpP"); 2011 return IEMOP_RAISE_INVALID_OPCODE();2016 IEMOP_RAISE_INVALID_OPCODE_RET(); 2012 2017 } 2013 2018 … … 2016 2021 { 2017 2022 IEMOP_MNEMONIC(GrpPInvalid, "GrpP"); 2018 return IEMOP_RAISE_INVALID_OPCODE();2023 IEMOP_RAISE_INVALID_OPCODE_RET(); 2019 2024 } 2020 2025 … … 2065 2070 { 2066 2071 IEMOP_MNEMONIC(Inv3Dnow, "3Dnow"); 2067 return IEMOP_RAISE_INVALID_OPCODE();2072 IEMOP_RAISE_INVALID_OPCODE_RET(); 2068 2073 } 2069 2074 … … 2599 2604 */ 2600 2605 else 2601 return IEMOP_RAISE_INVALID_OPCODE();2606 IEMOP_RAISE_INVALID_OPCODE_RET(); 2602 2607 } 2603 2608 … … 2763 2768 */ 2764 2769 else 2765 return IEMOP_RAISE_INVALID_OPCODE();2770 IEMOP_RAISE_INVALID_OPCODE_RET(); 2766 2771 } 2767 2772 … … 2810 2815 */ 2811 2816 else 2812 return IEMOP_RAISE_INVALID_OPCODE();2817 IEMOP_RAISE_INVALID_OPCODE_RET(); 2813 2818 } 2814 2819 … … 3017 3022 */ 3018 3023 else 3019 return IEMOP_RAISE_INVALID_OPCODE();3024 IEMOP_RAISE_INVALID_OPCODE_RET(); 3020 3025 } 3021 3026 … … 3136 3141 */ 3137 3142 else 3138 return IEMOP_RAISE_INVALID_OPCODE();3143 IEMOP_RAISE_INVALID_OPCODE_RET(); 3139 3144 } 3140 3145 … … 3184 3189 */ 3185 3190 else 3186 return IEMOP_RAISE_INVALID_OPCODE();3191 IEMOP_RAISE_INVALID_OPCODE_RET(); 3187 3192 } 3188 3193 … … 3239 3244 } 3240 3245 else 3241 return IEMOP_RAISE_INVALID_OPCODE();3246 IEMOP_RAISE_INVALID_OPCODE_RET(); 3242 3247 } 3243 3248 … … 3286 3291 /* The lock prefix can be used to encode CR8 accesses on some CPUs. */ 3287 3292 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit) 3288 return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */3293 IEMOP_RAISE_INVALID_OPCODE_RET(); /* #UD takes precedence over #GP(), see test. */ 3289 3294 iCrReg |= 8; 3290 3295 } … … 3294 3299 break; 3295 3300 default: 3296 return IEMOP_RAISE_INVALID_OPCODE();3301 IEMOP_RAISE_INVALID_OPCODE_RET(); 3297 3302 } 3298 3303 IEMOP_HLP_DONE_DECODING(); 3299 3304 3300 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Cd, IEM_GET_MODRM_RM(pVCpu, bRm), iCrReg);3305 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_mov_Rd_Cd, IEM_GET_MODRM_RM(pVCpu, bRm), iCrReg); 3301 3306 } 3302 3307 … … 3310 3315 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3311 3316 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R) 3312 return IEMOP_RAISE_INVALID_OPCODE(); 3313 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Dd, 3314 IEM_GET_MODRM_RM(pVCpu, bRm), 3315 IEM_GET_MODRM_REG_8(bRm)); 3317 IEMOP_RAISE_INVALID_OPCODE_RET(); 3318 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_mov_Rd_Dd, IEM_GET_MODRM_RM(pVCpu, bRm), IEM_GET_MODRM_REG_8(bRm)); 3316 3319 } 3317 3320 … … 3334 3337 /* The lock prefix can be used to encode CR8 accesses on some CPUs. */ 3335 3338 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit) 3336 return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */3339 IEMOP_RAISE_INVALID_OPCODE_RET(); /* #UD takes precedence over #GP(), see test. */ 3337 3340 iCrReg |= 8; 3338 3341 } … … 3342 3345 break; 3343 3346 default: 3344 return IEMOP_RAISE_INVALID_OPCODE();3347 IEMOP_RAISE_INVALID_OPCODE_RET(); 3345 3348 } 3346 3349 IEMOP_HLP_DONE_DECODING(); 3347 3350 3348 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3351 if (iCrReg & (2 | 8)) 3352 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 3353 iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3354 else 3355 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 3356 iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3349 3357 } 3350 3358 … … 3358 3366 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3359 3367 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R) 3360 return IEMOP_RAISE_INVALID_OPCODE(); 3361 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Dd_Rd, 3362 IEM_GET_MODRM_REG_8(bRm), 3363 IEM_GET_MODRM_RM(pVCpu, bRm)); 3368 IEMOP_RAISE_INVALID_OPCODE_RET(); 3369 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_mov_Dd_Rd, IEM_GET_MODRM_REG_8(bRm), IEM_GET_MODRM_RM(pVCpu, bRm)); 3364 3370 } 3365 3371 … … 3373 3379 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3374 3380 if (RT_LIKELY(IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_PENTIUM)) 3375 return IEMOP_RAISE_INVALID_OPCODE(); 3376 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Td, 3377 IEM_GET_MODRM_RM(pVCpu, bRm), 3378 IEM_GET_MODRM_REG_8(bRm)); 3381 IEMOP_RAISE_INVALID_OPCODE_RET(); 3382 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_mov_Rd_Td, IEM_GET_MODRM_RM(pVCpu, bRm), IEM_GET_MODRM_REG_8(bRm)); 3379 3383 } 3380 3384 … … 3388 3392 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3389 3393 if (RT_LIKELY(IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_PENTIUM)) 3390 return IEMOP_RAISE_INVALID_OPCODE(); 3391 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Td_Rd, 3392 IEM_GET_MODRM_REG_8(bRm), 3393 IEM_GET_MODRM_RM(pVCpu, bRm)); 3394 IEMOP_RAISE_INVALID_OPCODE_RET(); 3395 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_mov_Td_Rd, IEM_GET_MODRM_REG_8(bRm), IEM_GET_MODRM_RM(pVCpu, bRm)); 3394 3396 } 3395 3397 … … 4025 4027 /* The register, register encoding is invalid. */ 4026 4028 else 4027 return IEMOP_RAISE_INVALID_OPCODE();4029 IEMOP_RAISE_INVALID_OPCODE_RET(); 4028 4030 } 4029 4031 … … 4064 4066 /* The register, register encoding is invalid. */ 4065 4067 else 4066 return IEMOP_RAISE_INVALID_OPCODE();4068 IEMOP_RAISE_INVALID_OPCODE_RET(); 4067 4069 } 4068 4070 /* Opcode 0xf3 0x0f 0x2b - invalid */ … … 5136 5138 IEMOP_MNEMONIC(wrmsr, "wrmsr"); 5137 5139 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5138 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_wrmsr);5140 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_wrmsr); 5139 5141 } 5140 5142 … … 5145 5147 IEMOP_MNEMONIC(rdtsc, "rdtsc"); 5146 5148 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5147 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdtsc);5149 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdtsc); 5148 5150 } 5149 5151 … … 5154 5156 IEMOP_MNEMONIC(rdmsr, "rdmsr"); 5155 5157 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5156 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdmsr);5158 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdmsr); 5157 5159 } 5158 5160 … … 5163 5165 IEMOP_MNEMONIC(rdpmc, "rdpmc"); 5164 5166 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5165 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdpmc);5167 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdpmc); 5166 5168 } 5167 5169 … … 5172 5174 IEMOP_MNEMONIC0(FIXED, SYSENTER, sysenter, DISOPTYPE_CONTROLFLOW | DISOPTYPE_UNCOND_CONTROLFLOW, 0); 5173 5175 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5174 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_sysenter); 5176 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 5177 iemCImpl_sysenter); 5175 5178 } 5176 5179 … … 5180 5183 IEMOP_MNEMONIC0(FIXED, SYSEXIT, sysexit, DISOPTYPE_CONTROLFLOW | DISOPTYPE_UNCOND_CONTROLFLOW, 0); 5181 5184 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5182 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_sysexit, pVCpu->iem.s.enmEffOpSize); 5185 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 5186 iemCImpl_sysexit, pVCpu->iem.s.enmEffOpSize); 5183 5187 } 5184 5188 … … 5470 5474 /* No memory operand. */ 5471 5475 else 5472 return IEMOP_RAISE_INVALID_OPCODE();5476 IEMOP_RAISE_INVALID_OPCODE_RET(); 5473 5477 } 5474 5478 … … 5499 5503 /* No memory operand. */ 5500 5504 else 5501 return IEMOP_RAISE_INVALID_OPCODE();5505 IEMOP_RAISE_INVALID_OPCODE_RET(); 5502 5506 5503 5507 } … … 7100 7104 IEM_MC_FETCH_GREG_U64(u64Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7101 7105 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 7102 IEM_MC_CALL_CIMPL_2( iemCImpl_vmread_reg64, pu64Dst, u64Enc);7106 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmread_reg64, pu64Dst, u64Enc); 7103 7107 IEM_MC_END(); 7104 7108 } … … 7110 7114 IEM_MC_FETCH_GREG_U32(u32Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7111 7115 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 7112 IEM_MC_CALL_CIMPL_2( iemCImpl_vmread_reg32, pu64Dst, u32Enc);7116 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmread_reg32, pu64Dst, u32Enc); 7113 7117 IEM_MC_END(); 7114 7118 } … … 7129 7133 IEM_MC_FETCH_GREG_U64(u64Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7130 7134 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 7131 IEM_MC_CALL_CIMPL_3(iemCImpl_vmread_mem_reg64, iEffSeg, GCPtrVal, u64Enc); 7135 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 7136 iemCImpl_vmread_mem_reg64, iEffSeg, GCPtrVal, u64Enc); 7132 7137 IEM_MC_END(); 7133 7138 } … … 7142 7147 IEM_MC_FETCH_GREG_U32(u32Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7143 7148 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 7144 IEM_MC_CALL_CIMPL_3(iemCImpl_vmread_mem_reg32, iEffSeg, GCPtrVal, u32Enc); 7149 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 7150 iemCImpl_vmread_mem_reg32, iEffSeg, GCPtrVal, u32Enc); 7145 7151 IEM_MC_END(); 7146 7152 } … … 7179 7185 IEM_MC_FETCH_GREG_U64(u64Val, IEM_GET_MODRM_RM(pVCpu, bRm)); 7180 7186 IEM_MC_FETCH_GREG_U64(u64Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7181 IEM_MC_CALL_CIMPL_2( iemCImpl_vmwrite_reg, u64Val, u64Enc);7187 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmwrite_reg, u64Val, u64Enc); 7182 7188 IEM_MC_END(); 7183 7189 } … … 7189 7195 IEM_MC_FETCH_GREG_U32(u32Val, IEM_GET_MODRM_RM(pVCpu, bRm)); 7190 7196 IEM_MC_FETCH_GREG_U32(u32Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7191 IEM_MC_CALL_CIMPL_2( iemCImpl_vmwrite_reg, u32Val, u32Enc);7197 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmwrite_reg, u32Val, u32Enc); 7192 7198 IEM_MC_END(); 7193 7199 } … … 7208 7214 IEM_MC_FETCH_GREG_U64(u64Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7209 7215 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 7210 IEM_MC_CALL_CIMPL_3(iemCImpl_vmwrite_mem, iEffSeg, GCPtrVal, u64Enc); 7216 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 7217 iemCImpl_vmwrite_mem, iEffSeg, GCPtrVal, u64Enc); 7211 7218 IEM_MC_END(); 7212 7219 } … … 7221 7228 IEM_MC_FETCH_GREG_U32(u32Enc, IEM_GET_MODRM_REG(pVCpu, bRm)); 7222 7229 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 7223 IEM_MC_CALL_CIMPL_3(iemCImpl_vmwrite_mem, iEffSeg, GCPtrVal, u32Enc); 7230 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 7231 iemCImpl_vmwrite_mem, iEffSeg, GCPtrVal, u32Enc); 7224 7232 IEM_MC_END(); 7225 7233 } … … 8964 8972 IEMOP_HLP_MIN_386(); 8965 8973 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8966 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize);8974 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize); 8967 8975 } 8968 8976 … … 8974 8982 IEMOP_HLP_MIN_486(); /* not all 486es. */ 8975 8983 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8976 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_cpuid);8984 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_cpuid); 8977 8985 } 8978 8986 … … 9142 9150 #define IEMOP_BODY_BIT_Ev_Gv_NO_LOCK() \ 9143 9151 IEMOP_HLP_DONE_DECODING(); \ 9144 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \9152 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 9145 9153 } \ 9146 9154 } \ … … 9574 9582 IEMOP_HLP_MIN_386(); 9575 9583 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9576 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize);9584 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize); 9577 9585 } 9578 9586 … … 9584 9592 IEMOP_HLP_MIN_386(); /* 386SL and later. */ 9585 9593 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9586 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rsm); 9594 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 9595 iemCImpl_rsm); 9587 9596 } 9588 9597 … … 9622 9631 IEMOP_MNEMONIC(fxsave, "fxsave m512"); 9623 9632 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor) 9624 return IEMOP_RAISE_INVALID_OPCODE();9633 IEMOP_RAISE_INVALID_OPCODE_RET(); 9625 9634 9626 9635 IEM_MC_BEGIN(3, 1); … … 9632 9641 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 9633 9642 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9634 IEM_MC_CALL_CIMPL_3( iemCImpl_fxsave, iEffSeg, GCPtrEff, enmEffOpSize);9643 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_fxsave, iEffSeg, GCPtrEff, enmEffOpSize); 9635 9644 IEM_MC_END(); 9636 9645 } … … 9642 9651 IEMOP_MNEMONIC(fxrstor, "fxrstor m512"); 9643 9652 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor) 9644 return IEMOP_RAISE_INVALID_OPCODE();9653 IEMOP_RAISE_INVALID_OPCODE_RET(); 9645 9654 9646 9655 IEM_MC_BEGIN(3, 1); … … 9652 9661 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 9653 9662 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9654 IEM_MC_CALL_CIMPL_3( iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize);9663 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize); 9655 9664 IEM_MC_END(); 9656 9665 } … … 9680 9689 IEMOP_MNEMONIC1(M_MEM, LDMXCSR, ldmxcsr, Md_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 9681 9690 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) 9682 return IEMOP_RAISE_INVALID_OPCODE();9691 IEMOP_RAISE_INVALID_OPCODE_RET(); 9683 9692 9684 9693 IEM_MC_BEGIN(2, 0); … … 9689 9698 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 9690 9699 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9691 IEM_MC_CALL_CIMPL_2( iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);9700 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, iemCImpl_ldmxcsr, iEffSeg, GCPtrEff); 9692 9701 IEM_MC_END(); 9693 9702 } … … 9716 9725 IEMOP_MNEMONIC1(M_MEM, STMXCSR, stmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 9717 9726 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) 9718 return IEMOP_RAISE_INVALID_OPCODE();9727 IEMOP_RAISE_INVALID_OPCODE_RET(); 9719 9728 9720 9729 IEM_MC_BEGIN(2, 0); … … 9725 9734 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 9726 9735 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9727 IEM_MC_CALL_CIMPL_2( iemCImpl_stmxcsr, iEffSeg, GCPtrEff);9736 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, iemCImpl_stmxcsr, iEffSeg, GCPtrEff); 9728 9737 IEM_MC_END(); 9729 9738 } … … 9742 9751 IEMOP_MNEMONIC1(M_MEM, XSAVE, xsave, M_RW, DISOPTYPE_HARMLESS, 0); 9743 9752 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor) 9744 return IEMOP_RAISE_INVALID_OPCODE();9753 IEMOP_RAISE_INVALID_OPCODE_RET(); 9745 9754 9746 9755 IEM_MC_BEGIN(3, 0); … … 9752 9761 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 9753 9762 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9754 IEM_MC_CALL_CIMPL_3( iemCImpl_xsave, iEffSeg, GCPtrEff, enmEffOpSize);9763 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_xsave, iEffSeg, GCPtrEff, enmEffOpSize); 9755 9764 IEM_MC_END(); 9756 9765 } … … 9769 9778 IEMOP_MNEMONIC1(M_MEM, XRSTOR, xrstor, M_RO, DISOPTYPE_HARMLESS, 0); 9770 9779 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor) 9771 return IEMOP_RAISE_INVALID_OPCODE();9780 IEMOP_RAISE_INVALID_OPCODE_RET(); 9772 9781 9773 9782 IEM_MC_BEGIN(3, 0); … … 9779 9788 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ(); 9780 9789 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9781 IEM_MC_CALL_CIMPL_3( iemCImpl_xrstor, iEffSeg, GCPtrEff, enmEffOpSize);9790 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, iemCImpl_xrstor, iEffSeg, GCPtrEff, enmEffOpSize); 9782 9791 IEM_MC_END(); 9783 9792 } … … 9806 9815 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9807 9816 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9808 IEM_MC_CALL_CIMPL_2( iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);9817 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff); 9809 9818 IEM_MC_END(); 9810 9819 } … … 9830 9839 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9831 9840 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 9832 IEM_MC_CALL_CIMPL_2( iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);9841 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT, iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff); 9833 9842 IEM_MC_END(); 9834 9843 } … … 9842 9851 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9843 9852 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) 9844 return IEMOP_RAISE_INVALID_OPCODE();9853 IEMOP_RAISE_INVALID_OPCODE_RET(); 9845 9854 9846 9855 IEM_MC_BEGIN(0, 0); … … 9865 9874 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9866 9875 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) 9867 return IEMOP_RAISE_INVALID_OPCODE();9876 IEMOP_RAISE_INVALID_OPCODE_RET(); 9868 9877 9869 9878 IEM_MC_BEGIN(0, 0); … … 9888 9897 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9889 9898 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) 9890 return IEMOP_RAISE_INVALID_OPCODE();9899 IEMOP_RAISE_INVALID_OPCODE_RET(); 9891 9900 9892 9901 IEM_MC_BEGIN(0, 0); … … 10358 10367 IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff); 10359 10368 IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 2); 10360 IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10369 if (iSegReg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu)) 10370 IEM_MC_CALL_CIMPL_5( 0, iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10371 else 10372 IEM_MC_CALL_CIMPL_5(IEM_CIMPL_F_MODE, iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10361 10373 IEM_MC_END(); 10362 10374 … … 10373 10385 IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff); 10374 10386 IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 4); 10375 IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10387 if (iSegReg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu)) 10388 IEM_MC_CALL_CIMPL_5( 0, iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10389 else 10390 IEM_MC_CALL_CIMPL_5(IEM_CIMPL_F_MODE, iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10376 10391 IEM_MC_END(); 10377 10392 … … 10391 10406 IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff); 10392 10407 IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 8); 10393 IEM_MC_CALL_CIMPL_5( iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);10408 IEM_MC_CALL_CIMPL_5(0, iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize); 10394 10409 IEM_MC_END(); 10395 10410 … … 10406 10421 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10407 10422 if (IEM_IS_MODRM_REG_MODE(bRm)) 10408 return IEMOP_RAISE_INVALID_OPCODE();10423 IEMOP_RAISE_INVALID_OPCODE_RET(); 10409 10424 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_SS, bRm); 10410 10425 } … … 10428 10443 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10429 10444 if (IEM_IS_MODRM_REG_MODE(bRm)) 10430 return IEMOP_RAISE_INVALID_OPCODE();10445 IEMOP_RAISE_INVALID_OPCODE_RET(); 10431 10446 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_FS, bRm); 10432 10447 } … … 10440 10455 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10441 10456 if (IEM_IS_MODRM_REG_MODE(bRm)) 10442 return IEMOP_RAISE_INVALID_OPCODE();10457 IEMOP_RAISE_INVALID_OPCODE_RET(); 10443 10458 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_GS, bRm); 10444 10459 } … … 10789 10804 #define IEMOP_BODY_BIT_Ev_Ib_NO_LOCK() \ 10790 10805 IEMOP_HLP_DONE_DECODING(); \ 10791 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \10806 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 10792 10807 } \ 10793 10808 } \ … … 11854 11869 case IEMMODE_16BIT: 11855 11870 /** @todo check this form. */ 11856 return IEMOP_RAISE_INVALID_OPCODE();11871 IEMOP_RAISE_INVALID_OPCODE_RET(); 11857 11872 11858 11873 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 11860 11875 } 11861 11876 else 11862 return IEMOP_RAISE_INVALID_OPCODE();11877 IEMOP_RAISE_INVALID_OPCODE_RET(); 11863 11878 } 11864 11879 … … 12005 12020 /* No memory operand. */ 12006 12021 else 12007 return IEMOP_RAISE_INVALID_OPCODE();12022 IEMOP_RAISE_INVALID_OPCODE_RET(); 12008 12023 } 12009 12024 … … 12036 12051 /* No memory operand. */ 12037 12052 else 12038 return IEMOP_RAISE_INVALID_OPCODE();12053 IEMOP_RAISE_INVALID_OPCODE_RET(); 12039 12054 } 12040 12055 … … 12239 12254 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b_fallback, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags); 12240 12255 else 12241 IEM_MC_CALL_CIMPL_4(iemCImpl_cmpxchg16b_fallback_rendezvous, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags); 12256 IEM_MC_CALL_CIMPL_4(IEM_CIMPL_F_STATUS_FLAGS, 12257 iemCImpl_cmpxchg16b_fallback_rendezvous, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags); 12242 12258 } 12243 12259 … … 12258 12274 else 12259 12275 { 12260 IEM_MC_CALL_CIMPL_4(iemCImpl_cmpxchg16b_fallback_rendezvous, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags); 12276 IEM_MC_CALL_CIMPL_4(IEM_CIMPL_F_STATUS_FLAGS, 12277 iemCImpl_cmpxchg16b_fallback_rendezvous, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags); 12261 12278 /* Does not get here, tail code is duplicated in iemCImpl_cmpxchg16b_fallback_rendezvous. */ 12262 12279 } … … 12274 12291 } 12275 12292 Log(("cmpxchg16b -> #UD\n")); 12276 return IEMOP_RAISE_INVALID_OPCODE();12293 IEMOP_RAISE_INVALID_OPCODE_RET(); 12277 12294 } 12278 12295 … … 12289 12306 { 12290 12307 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdRand) 12291 return IEMOP_RAISE_INVALID_OPCODE();12308 IEMOP_RAISE_INVALID_OPCODE_RET(); 12292 12309 12293 12310 if (IEM_IS_MODRM_REG_MODE(bRm)) … … 12345 12362 /* Register only. */ 12346 12363 else 12347 return IEMOP_RAISE_INVALID_OPCODE();12364 IEMOP_RAISE_INVALID_OPCODE_RET(); 12348 12365 } 12349 12366 … … 12361 12378 IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES(); 12362 12379 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 12363 IEM_MC_CALL_CIMPL_2( iemCImpl_vmptrld, iEffSeg, GCPtrEffSrc);12380 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmptrld, iEffSeg, GCPtrEffSrc); 12364 12381 IEM_MC_END(); 12365 12382 } … … 12381 12398 IEMOP_HLP_DONE_DECODING(); 12382 12399 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 12383 IEM_MC_CALL_CIMPL_2( iemCImpl_vmclear, iEffSeg, GCPtrEffDst);12400 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmclear, iEffSeg, GCPtrEffDst); 12384 12401 IEM_MC_END(); 12385 12402 } … … 12400 12417 IEMOP_HLP_DONE_DECODING(); 12401 12418 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 12402 IEM_MC_CALL_CIMPL_2( iemCImpl_vmxon, iEffSeg, GCPtrEffSrc);12419 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmxon, iEffSeg, GCPtrEffSrc); 12403 12420 IEM_MC_END(); 12404 12421 } … … 12420 12437 IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES(); 12421 12438 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 12422 IEM_MC_CALL_CIMPL_2( iemCImpl_vmptrst, iEffSeg, GCPtrEffDst);12439 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_vmptrst, iEffSeg, GCPtrEffDst); 12423 12440 IEM_MC_END(); 12424 12441 } … … 12431 12448 { 12432 12449 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdSeed) 12433 return IEMOP_RAISE_INVALID_OPCODE();12450 IEMOP_RAISE_INVALID_OPCODE_RET(); 12434 12451 12435 12452 if (IEM_IS_MODRM_REG_MODE(bRm)) … … 12487 12504 /* Register only. */ 12488 12505 else 12489 return IEMOP_RAISE_INVALID_OPCODE();12506 IEMOP_RAISE_INVALID_OPCODE_RET(); 12490 12507 } 12491 12508 … … 12951 12968 } 12952 12969 else 12953 return IEMOP_RAISE_INVALID_OPCODE();12970 IEMOP_RAISE_INVALID_OPCODE_RET(); 12954 12971 } 12955 12972 … … 12977 12994 } 12978 12995 else 12979 return IEMOP_RAISE_INVALID_OPCODE();12996 IEMOP_RAISE_INVALID_OPCODE_RET(); 12980 12997 } 12981 12998 … … 13320 13337 */ 13321 13338 else 13322 return IEMOP_RAISE_INVALID_OPCODE();13339 IEMOP_RAISE_INVALID_OPCODE_RET(); 13323 13340 } 13324 13341 … … 13367 13384 */ 13368 13385 else 13369 return IEMOP_RAISE_INVALID_OPCODE();13386 IEMOP_RAISE_INVALID_OPCODE_RET(); 13370 13387 } 13371 13388 … … 13544 13561 * Register, register - (not implemented, assuming it raises \#UD). 13545 13562 */ 13546 return IEMOP_RAISE_INVALID_OPCODE();13563 IEMOP_RAISE_INVALID_OPCODE_RET(); 13547 13564 } 13548 13565 else … … 13832 13849 IEMOP_HLP_DONE_DECODING(); 13833 13850 } 13834 return IEMOP_RAISE_INVALID_OPCODE();13851 IEMOP_RAISE_INVALID_OPCODE_RET(); 13835 13852 } 13836 13853 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r99336 r100072 404 404 { 405 405 IEMOP_MNEMONIC(vud2, "vud2"); 406 return IEMOP_RAISE_INVALID_OPCODE();406 IEMOP_RAISE_INVALID_OPCODE_RET(); 407 407 } 408 408 … … 1085 1085 */ 1086 1086 else 1087 return IEMOP_RAISE_INVALID_OPCODE();1087 IEMOP_RAISE_INVALID_OPCODE_RET(); 1088 1088 } 1089 1089 … … 1339 1339 */ 1340 1340 else 1341 return IEMOP_RAISE_INVALID_OPCODE();1341 IEMOP_RAISE_INVALID_OPCODE_RET(); 1342 1342 } 1343 1343 … … 1386 1386 */ 1387 1387 else 1388 return IEMOP_RAISE_INVALID_OPCODE();1388 IEMOP_RAISE_INVALID_OPCODE_RET(); 1389 1389 } 1390 1390 … … 1541 1541 */ 1542 1542 else 1543 return IEMOP_RAISE_INVALID_OPCODE();1543 IEMOP_RAISE_INVALID_OPCODE_RET(); 1544 1544 } 1545 1545 … … 1692 1692 */ 1693 1693 else 1694 return IEMOP_RAISE_INVALID_OPCODE();1694 IEMOP_RAISE_INVALID_OPCODE_RET(); 1695 1695 } 1696 1696 … … 1737 1737 */ 1738 1738 else 1739 return IEMOP_RAISE_INVALID_OPCODE();1739 IEMOP_RAISE_INVALID_OPCODE_RET(); 1740 1740 } 1741 1741 … … 2176 2176 /* The register, register encoding is invalid. */ 2177 2177 else 2178 return IEMOP_RAISE_INVALID_OPCODE();2178 IEMOP_RAISE_INVALID_OPCODE_RET(); 2179 2179 } 2180 2180 … … 2237 2237 /* The register, register encoding is invalid. */ 2238 2238 else 2239 return IEMOP_RAISE_INVALID_OPCODE();2239 IEMOP_RAISE_INVALID_OPCODE_RET(); 2240 2240 } 2241 2241 … … 2647 2647 /* No memory operand. */ 2648 2648 else 2649 return IEMOP_RAISE_INVALID_OPCODE();2649 IEMOP_RAISE_INVALID_OPCODE_RET(); 2650 2650 } 2651 2651 … … 2698 2698 /* No memory operand. */ 2699 2699 else 2700 return IEMOP_RAISE_INVALID_OPCODE();2700 IEMOP_RAISE_INVALID_OPCODE_RET(); 2701 2701 } 2702 2702 … … 4293 4293 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ(); 4294 4294 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg); 4295 IEM_MC_CALL_CIMPL_2( iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);4295 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, iemCImpl_vstmxcsr, iEffSeg, GCPtrEff); 4296 4296 IEM_MC_END(); 4297 4297 } … … 4482 4482 /* No memory operand. */ 4483 4483 else 4484 return IEMOP_RAISE_INVALID_OPCODE();4484 IEMOP_RAISE_INVALID_OPCODE_RET(); 4485 4485 } 4486 4486 … … 4785 4785 } 4786 4786 else 4787 return IEMOP_RAISE_INVALID_OPCODE();4787 IEMOP_RAISE_INVALID_OPCODE_RET(); 4788 4788 } 4789 4789 … … 5029 5029 */ 5030 5030 else 5031 return IEMOP_RAISE_INVALID_OPCODE();5031 IEMOP_RAISE_INVALID_OPCODE_RET(); 5032 5032 } 5033 5033 … … 5137 5137 * Register, register - (not implemented, assuming it raises \#UD). 5138 5138 */ 5139 return IEMOP_RAISE_INVALID_OPCODE();5139 IEMOP_RAISE_INVALID_OPCODE_RET(); 5140 5140 } 5141 5141 else if (pVCpu->iem.s.uVexLength == 0) … … 5349 5349 IEMOP_HLP_DONE_DECODING(); 5350 5350 } 5351 return IEMOP_RAISE_INVALID_OPCODE();5351 IEMOP_RAISE_INVALID_OPCODE_RET(); 5352 5352 } 5353 5353 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h
r99958 r100072 606 606 */ 607 607 else 608 return IEMOP_RAISE_INVALID_OPCODE();608 IEMOP_RAISE_INVALID_OPCODE_RET(); 609 609 } 610 610 -
trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp
r99301 r100072 135 135 136 136 /** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */ 137 #define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_ pfnCImpl, a0) \137 #define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0) \ 138 138 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0) 139 139 #undef IEM_MC_CALL_CIMPL_1 140 140 141 141 /** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */ 142 #define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_ pfnCImpl, a0, a1) \142 #define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1) \ 143 143 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1) 144 144 #undef IEM_MC_CALL_CIMPL_2 145 145 146 146 /** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */ 147 #define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_ pfnCImpl, a0, a1, a2) \147 #define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2) \ 148 148 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2) 149 149 #undef IEM_MC_CALL_CIMPL_3 150 150 151 151 /** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */ 152 #define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_ pfnCImpl, a0, a1, a2, a3) \152 #define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \ 153 153 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3) 154 154 #undef IEM_MC_CALL_CIMPL_4 155 155 156 156 /** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */ 157 #define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_ pfnCImpl, a0, a1, a2, a3, a4) \157 #define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \ 158 158 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4) 159 159 #undef IEM_MC_CALL_CIMPL_5
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