Changeset 100084 in vbox for trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

Timestamp:

Jun 6, 2023 2:56:14 PM (18 months ago)

Author:

vboxsync

Message:

VMM/IEM: Added iemRegGRegStoreUxx inline helpers and replaced all the ugly casting around iemGRegRef. Fixed SMSW not clearing high 32-bits and made it set unused bits for the 32-bit operand size too if in 386-mode. bugref:10369

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp (modified) (9 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

@@ -4954 +4954 @@
         {
             case IEMMODE_16BIT:
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
+                iemGRegStoreU16(pVCpu, iGReg, offSeg);
                 break;
             case IEMMODE_32BIT:
             case IEMMODE_64BIT:
-                *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
+                iemGRegStoreU64(pVCpu, iGReg, offSeg);
                 break;
             IEM_NOT_REACHED_DEFAULT_CASE_RET();
@@ -5529 +5529 @@
     switch (enmEffOpSize)
     {
-        case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
-        case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
-        case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
+        case IEMMODE_16BIT:
+            iemGRegStoreU16(pVCpu, iGReg, pVCpu->cpum.GstCtx.ldtr.Sel);
+            break;
+        case IEMMODE_32BIT:
+        case IEMMODE_64BIT:
+            iemGRegStoreU64(pVCpu, iGReg, pVCpu->cpum.GstCtx.ldtr.Sel);
+            break;
         IEM_NOT_REACHED_DEFAULT_CASE_RET();
     }
@@ -5711 +5715 @@
     switch (enmEffOpSize)
     {
-        case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
-        case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
-        case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
+        case IEMMODE_16BIT:
+            iemGRegStoreU16(pVCpu, iGReg, pVCpu->cpum.GstCtx.tr.Sel);
+            break;
+        case IEMMODE_32BIT:
+        case IEMMODE_64BIT:
+            iemGRegStoreU64(pVCpu, iGReg, pVCpu->cpum.GstCtx.tr.Sel);
+            break;
         IEM_NOT_REACHED_DEFAULT_CASE_RET();
     }
@@ -5860 +5868 @@
     /* Store it. */
     if (IEM_IS_64BIT_CODE(pVCpu))
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
+        iemGRegStoreU64(pVCpu, iGReg, crX);
     else
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
+        iemGRegStoreU64(pVCpu, iGReg, (uint32_t)crX);
 
     return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
@@ -5893 +5901 @@
         case IEMMODE_16BIT:
             if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0;
+                iemGRegStoreU16(pVCpu, iGReg, (uint16_t)u64GuestCr0);
+            /* Unused bits are set on 386 and older CPU: */
             else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xffe0;
+                iemGRegStoreU16(pVCpu, iGReg, (uint16_t)u64GuestCr0 | 0xffe0);
             else
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xfff0;
+                iemGRegStoreU16(pVCpu, iGReg, (uint16_t)u64GuestCr0 | 0xfff0);
             break;
 
+/** @todo testcase for bits 31:16. We're not doing that correctly. */
+
         case IEMMODE_32BIT:
-            *(uint32_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)u64GuestCr0;
+            if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
+                iemGRegStoreU32(pVCpu, iGReg, (uint32_t)u64GuestCr0);
+            else /** @todo test this! */
+                iemGRegStoreU32(pVCpu, iGReg, (uint32_t)u64GuestCr0 | UINT32_C(0x7fffffe0)); /* Unused bits are set on 386. */
             break;
 
         case IEMMODE_64BIT:
-            *(uint64_t *)iemGRegRef(pVCpu, iGReg) = u64GuestCr0;
+            iemGRegStoreU64(pVCpu, iGReg, u64GuestCr0);
             break;
 
@@ -6654 +6668 @@
 
     if (IEM_IS_64BIT_CODE(pVCpu))
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
+        iemGRegStoreU64(pVCpu, iGReg, drX);
     else
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
+        iemGRegStoreU32(pVCpu, iGReg, (uint32_t)drX);
 
     return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
@@ -6827 +6841 @@
      * (different on 386/486) is exceedingly rare.
      */
-    uint64_t trX;
+    uint32_t trX;
     switch (iTrReg)
     {
@@ -6839 +6853 @@
     }
 
-    *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)trX;
+    iemGRegStoreU32(pVCpu, iGReg, trX);
 
     return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
@@ -6873 +6887 @@
      * Read the new value from the source register.
      */
-    uint64_t uNewTrX;
-    if (IEM_IS_64BIT_CODE(pVCpu)) /** @todo err... 64-bit 386? */
-        uNewTrX = iemGRegFetchU64(pVCpu, iGReg);
-    else
-        uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
+    uint32_t uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
 
     /*