Index: /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp	(revision 100083)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp	(revision 100084)
@@ -4954,9 +4954,9 @@
         {
             case IEMMODE_16BIT:
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
+                iemGRegStoreU16(pVCpu, iGReg, offSeg);
                 break;
             case IEMMODE_32BIT:
             case IEMMODE_64BIT:
-                *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
+                iemGRegStoreU64(pVCpu, iGReg, offSeg);
                 break;
             IEM_NOT_REACHED_DEFAULT_CASE_RET();
@@ -5529,7 +5529,11 @@
     switch (enmEffOpSize)
     {
-        case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
-        case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
-        case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
+        case IEMMODE_16BIT:
+            iemGRegStoreU16(pVCpu, iGReg, pVCpu->cpum.GstCtx.ldtr.Sel);
+            break;
+        case IEMMODE_32BIT:
+        case IEMMODE_64BIT:
+            iemGRegStoreU64(pVCpu, iGReg, pVCpu->cpum.GstCtx.ldtr.Sel);
+            break;
         IEM_NOT_REACHED_DEFAULT_CASE_RET();
     }
@@ -5711,7 +5715,11 @@
     switch (enmEffOpSize)
     {
-        case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
-        case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
-        case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
+        case IEMMODE_16BIT:
+            iemGRegStoreU16(pVCpu, iGReg, pVCpu->cpum.GstCtx.tr.Sel);
+            break;
+        case IEMMODE_32BIT:
+        case IEMMODE_64BIT:
+            iemGRegStoreU64(pVCpu, iGReg, pVCpu->cpum.GstCtx.tr.Sel);
+            break;
         IEM_NOT_REACHED_DEFAULT_CASE_RET();
     }
@@ -5860,7 +5868,7 @@
     /* Store it. */
     if (IEM_IS_64BIT_CODE(pVCpu))
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
+        iemGRegStoreU64(pVCpu, iGReg, crX);
     else
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
+        iemGRegStoreU64(pVCpu, iGReg, (uint32_t)crX);
 
     return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
@@ -5893,17 +5901,23 @@
         case IEMMODE_16BIT:
             if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0;
+                iemGRegStoreU16(pVCpu, iGReg, (uint16_t)u64GuestCr0);
+            /* Unused bits are set on 386 and older CPU: */
             else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xffe0;
+                iemGRegStoreU16(pVCpu, iGReg, (uint16_t)u64GuestCr0 | 0xffe0);
             else
-                *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xfff0;
+                iemGRegStoreU16(pVCpu, iGReg, (uint16_t)u64GuestCr0 | 0xfff0);
             break;
 
+/** @todo testcase for bits 31:16. We're not doing that correctly. */
+
         case IEMMODE_32BIT:
-            *(uint32_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)u64GuestCr0;
+            if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
+                iemGRegStoreU32(pVCpu, iGReg, (uint32_t)u64GuestCr0);
+            else /** @todo test this! */
+                iemGRegStoreU32(pVCpu, iGReg, (uint32_t)u64GuestCr0 | UINT32_C(0x7fffffe0)); /* Unused bits are set on 386. */
             break;
 
         case IEMMODE_64BIT:
-            *(uint64_t *)iemGRegRef(pVCpu, iGReg) = u64GuestCr0;
+            iemGRegStoreU64(pVCpu, iGReg, u64GuestCr0);
             break;
 
@@ -6654,7 +6668,7 @@
 
     if (IEM_IS_64BIT_CODE(pVCpu))
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
+        iemGRegStoreU64(pVCpu, iGReg, drX);
     else
-        *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
+        iemGRegStoreU32(pVCpu, iGReg, (uint32_t)drX);
 
     return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
@@ -6827,5 +6841,5 @@
      * (different on 386/486) is exceedingly rare.
      */
-    uint64_t trX;
+    uint32_t trX;
     switch (iTrReg)
     {
@@ -6839,5 +6853,5 @@
     }
 
-    *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)trX;
+    iemGRegStoreU32(pVCpu, iGReg, trX);
 
     return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
@@ -6873,9 +6887,5 @@
      * Read the new value from the source register.
      */
-    uint64_t uNewTrX;
-    if (IEM_IS_64BIT_CODE(pVCpu)) /** @todo err... 64-bit 386? */
-        uNewTrX = iemGRegFetchU64(pVCpu, iGReg);
-    else
-        uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
+    uint32_t uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
 
     /*
Index: /trunk/src/VBox/VMM/include/IEMInline.h
===================================================================
--- /trunk/src/VBox/VMM/include/IEMInline.h	(revision 100083)
+++ /trunk/src/VBox/VMM/include/IEMInline.h	(revision 100084)
@@ -1604,5 +1604,5 @@
  * @param   iSegReg             The segment register.
  */
-DECLINLINE(PCPUMSELREG) iemSRegGetHid(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(PCPUMSELREG) iemSRegGetHid(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
 {
     Assert(iSegReg < X86_SREG_COUNT);
@@ -1622,5 +1622,5 @@
  * @param   pSReg               The segment register.
  */
-DECLINLINE(PCPUMSELREG) iemSRegUpdateHid(PVMCPUCC pVCpu, PCPUMSELREG pSReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(PCPUMSELREG) iemSRegUpdateHid(PVMCPUCC pVCpu, PCPUMSELREG pSReg) RT_NOEXCEPT
 {
     Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
@@ -1638,5 +1638,5 @@
  * @param   iSegReg             The segment register.
  */
-DECLINLINE(uint16_t *) iemSRegRef(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint16_t *) iemSRegRef(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
 {
     Assert(iSegReg < X86_SREG_COUNT);
@@ -1653,5 +1653,5 @@
  * @param   iSegReg             The segment register.
  */
-DECLINLINE(uint16_t) iemSRegFetchU16(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint16_t) iemSRegFetchU16(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
 {
     Assert(iSegReg < X86_SREG_COUNT);
@@ -1668,5 +1668,5 @@
  * @param   iSegReg             The segment register.
  */
-DECLINLINE(uint64_t) iemSRegBaseFetchU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint64_t) iemSRegBaseFetchU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
 {
     Assert(iSegReg < X86_SREG_COUNT);
@@ -1683,5 +1683,5 @@
  * @param   iReg                The general purpose register.
  */
-DECLINLINE(void *) iemGRegRef(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(void *) iemGRegRef(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1700,5 +1700,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint8_t *) iemGRegRefU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint8_t *) iemGRegRefU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     if (iReg < 4 || (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX))
@@ -1723,6 +1723,8 @@
  *                              whereas 16 thru 19 maps to AH, CH, DH and BH.
  */
-DECLINLINE(uint8_t *) iemGRegRefU8Ex(PVMCPUCC pVCpu, uint8_t iRegEx) RT_NOEXCEPT
-{
+DECL_FORCE_INLINE(uint8_t *) iemGRegRefU8Ex(PVMCPUCC pVCpu, uint8_t iRegEx) RT_NOEXCEPT
+{
+    /** @todo This could be done by double indexing on little endian hosts:
+     *  return &pVCpu->cpum.GstCtx.aGRegs[iRegEx & 15].ab[iRegEx >> 4]; */
     if (iRegEx < 16)
         return &pVCpu->cpum.GstCtx.aGRegs[iRegEx].u8;
@@ -1741,5 +1743,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint16_t *) iemGRegRefU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint16_t *) iemGRegRefU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1755,5 +1757,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint32_t *) iemGRegRefU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint32_t *) iemGRegRefU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1769,5 +1771,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(int32_t *) iemGRegRefI32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(int32_t *) iemGRegRefI32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1783,5 +1785,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint64_t *) iemGRegRefU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint64_t *) iemGRegRefU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 64);
@@ -1797,5 +1799,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(int64_t *) iemGRegRefI64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(int64_t *) iemGRegRefI64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1811,5 +1813,5 @@
  * @param   iSegReg             The segment selector.
  */
-DECLINLINE(uint64_t *) iemSRegBaseRefU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint64_t *) iemSRegBaseRefU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
 {
     Assert(iSegReg < X86_SREG_COUNT);
@@ -1827,5 +1829,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint8_t) iemGRegFetchU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint8_t) iemGRegFetchU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     return *iemGRegRefU8(pVCpu, iReg);
@@ -1843,5 +1845,5 @@
  *                              whereas 16 thru 19 maps to AH, CH, DH and BH.
  */
-DECLINLINE(uint8_t) iemGRegFetchU8Ex(PVMCPUCC pVCpu, uint8_t iRegEx) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint8_t) iemGRegFetchU8Ex(PVMCPUCC pVCpu, uint8_t iRegEx) RT_NOEXCEPT
 {
     return *iemGRegRefU8Ex(pVCpu, iRegEx);
@@ -1856,5 +1858,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint16_t) iemGRegFetchU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint16_t) iemGRegFetchU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1870,5 +1872,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint32_t) iemGRegFetchU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint32_t) iemGRegFetchU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1884,5 +1886,5 @@
  * @param   iReg                The register.
  */
-DECLINLINE(uint64_t) iemGRegFetchU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
+DECL_FORCE_INLINE(uint64_t) iemGRegFetchU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
 {
     Assert(iReg < 16);
@@ -1892,9 +1894,52 @@
 
 /**
+ * Stores a 16-bit value to a general purpose register.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   iReg                The register.
+ * @param   uValue              The value to store.
+ */
+DECL_FORCE_INLINE(void) iemGRegStoreU16(PVMCPUCC pVCpu, uint8_t iReg, uint16_t uValue) RT_NOEXCEPT
+{
+    Assert(iReg < 16);
+    pVCpu->cpum.GstCtx.aGRegs[iReg].u16 = uValue;
+}
+
+
+/**
+ * Stores a 32-bit value to a general purpose register, implicitly clearing high
+ * values.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   iReg                The register.
+ * @param   uValue              The value to store.
+ */
+DECL_FORCE_INLINE(void) iemGRegStoreU32(PVMCPUCC pVCpu, uint8_t iReg, uint32_t uValue) RT_NOEXCEPT
+{
+    Assert(iReg < 16);
+    pVCpu->cpum.GstCtx.aGRegs[iReg].u64 = uValue;
+}
+
+
+/**
+ * Stores a 64-bit value to a general purpose register.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   iReg                The register.
+ * @param   uValue              The value to store.
+ */
+DECL_FORCE_INLINE(void) iemGRegStoreU64(PVMCPUCC pVCpu, uint8_t iReg, uint64_t uValue) RT_NOEXCEPT
+{
+    Assert(iReg < 16);
+    pVCpu->cpum.GstCtx.aGRegs[iReg].u64 = uValue;
+}
+
+
+/**
  * Get the address of the top of the stack.
  *
  * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
  */
-DECLINLINE(RTGCPTR) iemRegGetEffRsp(PCVMCPU pVCpu) RT_NOEXCEPT
+DECL_FORCE_INLINE(RTGCPTR) iemRegGetEffRsp(PCVMCPU pVCpu) RT_NOEXCEPT
 {
     if (IEM_IS_64BIT_CODE(pVCpu))
