Changeset 100096 in vbox for trunk/src/VBox/VMM/include

Timestamp:

Jun 7, 2023 3:14:56 PM (20 months ago)

Author:

vboxsync

Message:

VMM/IEM: Adjusted/reworked the relative jump MCs in the threaded function file. bugref:10369

File:

• trunk/src/VBox/VMM/include/IEMInline.h (modified) (1 diff)

trunk/src/VBox/VMM/include/IEMInline.h

@@ -2138 +2138 @@
 
 /**
+ * Adds a 8-bit signed jump offset to RIP from 64-bit code.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ * @param   enmEffOpSize        Effective operand size.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
+                                                                             IEMMODE enmEffOpSize) RT_NOEXCEPT
+{
+    Assert(IEM_IS_64BIT_CODE(pVCpu));
+    Assert(enmEffOpSize == IEMMODE_64BIT || enmEffOpSize == IEMMODE_16BIT);
+
+    uint64_t uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
+    if (enmEffOpSize == IEMMODE_16BIT)
+        uNewRip &= UINT16_MAX;
+
+    if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
+        pVCpu->cpum.GstCtx.rip = uNewRip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 8-bit signed jump offset to EIP, on 386 or later from 16-bit or 32-bit
+ * code (never 64-bit).
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ * @param   enmEffOpSize        Effective operand size.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
+                                                                             IEMMODE enmEffOpSize) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+    Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
+
+    uint32_t uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + (int32_t)offNextInstr;
+    if (enmEffOpSize == IEMMODE_16BIT)
+        uNewEip &= UINT16_MAX;
+    if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewEip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 8-bit signed jump offset to IP, on a pre-386 CPU.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegIp16RelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                            int8_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+
+    uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + (int16_t)offNextInstr;
+    if (RT_LIKELY(uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewIp;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 16-bit signed jump offset to RIP from 64-bit code.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                              int16_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(IEM_IS_64BIT_CODE(pVCpu));
+
+    pVCpu->cpum.GstCtx.rip = (uint16_t)(pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 16-bit signed jump offset to EIP from 16-bit or 32-bit code.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ *
+ * @note    This is also used by 16-bit code in pre-386 mode, as the code is
+ *          identical.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                              int16_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+
+    uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr;
+    if (RT_LIKELY(uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewIp;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 32-bit signed jump offset to RIP from 64-bit code.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * We ASSUME that the effective operand size is 64-bit here, as 16-bit is the
+ * only alternative for relative jumps in 64-bit code and that is already
+ * handled in the decoder stage.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                              int32_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(IEM_IS_64BIT_CODE(pVCpu));
+
+    uint64_t const uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
+    if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
+        pVCpu->cpum.GstCtx.rip = uNewRip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 32-bit signed jump offset to RIP from 64-bit code.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * We ASSUME that the effective operand size is 32-bit here, as 16-bit is the
+ * only alternative for relative jumps in 32-bit code and that is already
+ * handled in the decoder stage.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                              int32_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+    Assert(pVCpu->cpum.GstCtx.rip <= UINT32_MAX);
+
+    uint32_t const uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + offNextInstr;
+    if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewEip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+
+    /*
+     * Clear RF and finish the instruction (maybe raise #DB).
+     */
+    return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
  * Extended version of iemFinishInstructionWithFlagsSet that goes with
  * iemRegAddToRipAndFinishingClearingRfEx.