Changeset 100101 in vbox

Timestamp:

Jun 7, 2023 5:52:38 PM (18 months ago)

Author:

vboxsync

Message:

VMM: Add VMMR3CpuOn() for ARMv8 instead of using the VMMR3SendStartupIpi() API as the code needs to convey the start address where to execute code and a guest defined context ID, bugref:10454

Location:

trunk

Files:

• include/VBox/vmm/vmm.h (modified) (1 diff)
• src/VBox/VMM/VMMR3/VMM.cpp (modified) (5 diffs)

trunk/include/VBox/vmm/vmm.h

@@ -559 +559 @@
 VMMR3_INT_DECL(void)    VMMR3YieldStop(PVM pVM);
 VMMR3_INT_DECL(void)    VMMR3YieldResume(PVM pVM);
+#if defined(VBOX_VMM_TARGET_ARMV8)
+VMMR3_INT_DECL(void)    VMMR3CpuOn(PVM pVM, VMCPUID idCpu, RTGCPHYS GCPhysExecAddr, uint64_t u64CtxId);
+#else
 VMMR3_INT_DECL(void)    VMMR3SendStartupIpi(PVM pVM, VMCPUID idCpu, uint32_t uVector);
 VMMR3_INT_DECL(void)    VMMR3SendInitIpi(PVM pVM, VMCPUID idCpu);
+#endif
 VMMR3DECL(int)          VMMR3RegisterPatchMemory(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
 VMMR3DECL(int)          VMMR3DeregisterPatchMemory(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);

trunk/src/VBox/VMM/VMMR3/VMM.cpp

@@ -146 +146 @@
 #include <iprt/assert.h>
 #include <iprt/alloc.h>
+#if defined(VBOX_VMM_TARGET_ARMV8)
+# include <iprt/armv8.h>
+#endif
 #include <iprt/asm.h>
 #include <iprt/time.h>
@@ -1292 +1295 @@
 
 
-/**
- * VCPU worker for VMMR3SendStartupIpi.
- *
- * @param   pVM         The cross context VM structure.
- * @param   idCpu       Virtual CPU to perform SIPI on.
- * @param   uVector     The SIPI vector.
- */
-static DECLCALLBACK(int) vmmR3SendStarupIpi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
+#if defined(VBOX_VMM_TARGET_ARMV8)
+/**
+ * VCPU worker for VMMR3CpuOn.
+ *
+ * @param   pVM             The cross context VM structure.
+ * @param   idCpu           Virtual CPU to perform SIPI on.
+ * @param   GCPhysExecAddr  The guest physical address to start executing at.
+ * @param   u64CtxId        The context ID passed in x0/w0.
+ */
+static DECLCALLBACK(int) vmmR3CpuOn(PVM pVM, VMCPUID idCpu, RTGCPHYS GCPhysExecAddr, uint64_t u64CtxId)
 {
     PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
     VMCPU_ASSERT_EMT(pVCpu);
 
-    /*
-     * In the INIT state, the target CPU is only responsive to an SIPI.
-     * This is also true for when when the CPU is in VMX non-root mode.
-     *
-     * See AMD spec. 16.5 "Interprocessor Interrupts (IPI)".
-     * See Intel spec. 26.6.2 "Activity State".
-     */
     if (EMGetState(pVCpu) != EMSTATE_WAIT_SIPI)
         return VINF_SUCCESS;
 
-#if defined(VBOX_VMM_TARGET_ARMV8)
-    AssertReleaseFailed(); /** @todo */
-#else
     PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
-# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
-    if (CPUMIsGuestInVmxRootMode(pCtx))
-    {
-        /* If the CPU is in VMX non-root mode we must cause a VM-exit. */
-        if (CPUMIsGuestInVmxNonRootMode(pCtx))
-            return VBOXSTRICTRC_TODO(IEMExecVmxVmexitStartupIpi(pVCpu, uVector));
-
-        /* If the CPU is in VMX root mode (and not in VMX non-root mode) SIPIs are blocked. */
-        return VINF_SUCCESS;
-    }
-# endif
-
-    pCtx->cs.Sel        = uVector << 8;
-    pCtx->cs.ValidSel   = uVector << 8;
-    pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
-    pCtx->cs.u64Base    = uVector << 12;
-    pCtx->cs.u32Limit   = UINT32_C(0x0000ffff);
-    pCtx->rip           = 0;
-#endif
-
-    Log(("vmmR3SendSipi for VCPU %d with vector %x\n", idCpu, uVector));
+
+    pCtx->aGRegs[ARMV8_AARCH64_REG_X0].x = u64CtxId;
+    pCtx->Pc.u64                         = GCPhysExecAddr;
+
+    Log(("vmmR3CpuOn for VCPU %d with GCPhysExecAddr=%RGp u64CtxId=%#RX64\n", idCpu, GCPhysExecAddr, u64CtxId));
 
 # if 1 /* If we keep the EMSTATE_WAIT_SIPI method, then move this to EM.cpp. */
@@ -1352 +1331 @@
 
 /**
+ * Sends a Startup IPI to the virtual CPU by setting CS:EIP into
+ * vector-dependent state and unhalting processor.
+ *
+ * @param   pVM             The cross context VM structure.
+ * @param   idCpu           Virtual CPU to perform SIPI on.
+ * @param   GCPhysExecAddr  The guest physical address to start executing at.
+ * @param   u64CtxId        The context ID passed in x0/w0.
+ */
+VMMR3_INT_DECL(void)    VMMR3CpuOn(PVM pVM, VMCPUID idCpu, RTGCPHYS GCPhysExecAddr, uint64_t u64CtxId)
+{
+    AssertReturnVoid(idCpu < pVM->cCpus);
+
+    int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3CpuOn, 4, pVM, idCpu, GCPhysExecAddr, u64CtxId);
+    AssertRC(rc);
+}
+#else
+/**
+ * VCPU worker for VMMR3SendStartupIpi.
+ *
+ * @param   pVM         The cross context VM structure.
+ * @param   idCpu       Virtual CPU to perform SIPI on.
+ * @param   uVector     The SIPI vector.
+ */
+static DECLCALLBACK(int) vmmR3SendStartupIpi(PVM pVM, VMCPUID idCpu, uint32_t uVector)
+{
+    PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
+    VMCPU_ASSERT_EMT(pVCpu);
+
+    /*
+     * In the INIT state, the target CPU is only responsive to an SIPI.
+     * This is also true for when when the CPU is in VMX non-root mode.
+     *
+     * See AMD spec. 16.5 "Interprocessor Interrupts (IPI)".
+     * See Intel spec. 26.6.2 "Activity State".
+     */
+    if (EMGetState(pVCpu) != EMSTATE_WAIT_SIPI)
+        return VINF_SUCCESS;
+
+    PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
+# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+    if (CPUMIsGuestInVmxRootMode(pCtx))
+    {
+        /* If the CPU is in VMX non-root mode we must cause a VM-exit. */
+        if (CPUMIsGuestInVmxNonRootMode(pCtx))
+            return VBOXSTRICTRC_TODO(IEMExecVmxVmexitStartupIpi(pVCpu, uVector));
+
+        /* If the CPU is in VMX root mode (and not in VMX non-root mode) SIPIs are blocked. */
+        return VINF_SUCCESS;
+    }
+# endif
+
+    pCtx->cs.Sel        = uVector << 8;
+    pCtx->cs.ValidSel   = uVector << 8;
+    pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.u64Base    = uVector << 12;
+    pCtx->cs.u32Limit   = UINT32_C(0x0000ffff);
+    pCtx->rip           = 0;
+
+    Log(("vmmR3SendSipi for VCPU %d with vector %x\n", idCpu, uVector));
+
+# if 1 /* If we keep the EMSTATE_WAIT_SIPI method, then move this to EM.cpp. */
+    EMSetState(pVCpu, EMSTATE_HALTED);
+    return VINF_EM_RESCHEDULE;
+# else /* And if we go the VMCPU::enmState way it can stay here. */
+    VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STOPPED);
+    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
+    return VINF_SUCCESS;
+# endif
+}
+
+
+/**
  * VCPU worker for VMMR3SendInitIpi.
  *
@@ -1406 +1457 @@
     AssertReturnVoid(idCpu < pVM->cCpus);
 
-    int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendStarupIpi, 3, pVM, idCpu, uVector);
+    int rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)vmmR3SendStartupIpi, 3, pVM, idCpu, uVector);
     AssertRC(rc);
 }
@@ -1424 +1475 @@
     AssertRC(rc);
 }
+#endif