Changeset 100108 in vbox for trunk/src/VBox/VMM/VMMR3

Timestamp:

Jun 7, 2023 8:05:13 PM (20 months ago)

Author:

vboxsync

Message:

*: Fix build issues when setting VBOX_WITH_WARNINGS_AS_ERRORS=1 on darwin.arm64 and make it a default, bugref:10469

Location:

trunk/src/VBox/VMM/VMMR3

Files:

• DBGFDisas.cpp (modified) (1 diff)
• GICR3.cpp (modified) (3 diffs)
• GIM.cpp (modified) (2 diffs)
• HM-armv8.cpp (modified) (1 diff)
• NEMR3Native-darwin-armv8.cpp (modified) (1 diff)
• PDMAsyncCompletionFile.cpp (modified) (1 diff)
• PDMDevHlp.cpp (modified) (3 diffs)
• PDMDevMiscHlp.cpp (modified) (5 diffs)
• PGM-armv8.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp

@@ -383 +383 @@
 
 #if defined(VBOX_VMM_TARGET_ARMV8)
-    RT_NOREF(pVM, Sel, GCPtr, rc, fFlags, pszOutput, cbOutput, pcbInstr, pDisState);
+    RT_NOREF(pVM, pVCpu, Sel, GCPtr, rc, fFlags, pszOutput, cbOutput, pcbInstr, pDisState);
     AssertReleaseFailed(); /** @todo */
     return VERR_NOT_IMPLEMENTED;

trunk/src/VBox/VMM/VMMR3/GICR3.cpp

@@ -210 +210 @@
                                STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
 
+#ifdef VBOX_WITH_STATISTICS
     for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
     {
@@ -215 +216 @@
         PGICCPU pGicCpu  = VMCPU_TO_GICCPU(pVCpu);
 
-#ifdef VBOX_WITH_STATISTICS
 # if 0 /* No R0 for now. */
         GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ,    "%u/RZ/MmioRead",    "Number of APIC MMIO reads in RZ.");
@@ -227 +227 @@
         GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3,  "%u/R3/SysRegRead",  "Number of GIC system register reads in R3.");
         GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
+    }
 #endif
-    }
 
 # undef GIC_PROF_COUNTER

trunk/src/VBox/VMM/VMMR3/GIM.cpp

@@ -350 +350 @@
 static DECLCALLBACK(int) gimR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
 {
+#if defined(VBOX_VMM_TARGET_ARMV8)
+    RT_NOREF(pSSM);
+#endif
+
     switch (pVM->gim.s.enmProviderId)
     {
@@ -399 +403 @@
 VMMR3_INT_DECL(void) GIMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
 {
+#if defined(VBOX_VMM_TARGET_ARMV8)
+    RT_NOREF(offDelta);
+#endif
+
     switch (pVM->gim.s.enmProviderId)
     {

trunk/src/VBox/VMM/VMMR3/HM-armv8.cpp

@@ -539 +539 @@
 {
     Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
-    return false;
-}
+    RT_NOREF(pVM);
+    return false;
+}

trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

@@ -889 +889 @@
                  fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
 
+    RT_NOREF(fL2Fault, GCPtrDataAbrt);
     AssertReturn(fIsv, VERR_NOT_SUPPORTED); /** @todo Implement using IEM when this should occur. */
 

trunk/src/VBox/VMM/VMMR3/PDMAsyncCompletionFile.cpp

@@ -420 +420 @@
         pdmacFileEpAddTask(pEpFile, pIoTask);
         off        += paSegments[i].cbSeg;
+#ifdef RT_STRICT
         cbTransfer -= paSegments[i].cbSeg;
+#else
+        RT_NOREF(cbTransfer);
+#endif
     }
 

trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

@@ -1237 +1237 @@
     uint64_t u64Fsb = 0;
     AssertReleaseFailed();
+    RT_NOREF(pDevIns);
 #else
     uint64_t u64Fsb = CPUMGetGuestScalableBusFrequency(pDevIns->Internal.s.pVMR3);
@@ -4637 +4638 @@
 #ifdef VBOX_VMM_TARGET_ARMV8
     AssertReleaseFailed();
+    RT_NOREF(pDevIns, fEnable);
 #else
     PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
@@ -4655 +4657 @@
 
 #ifdef VBOX_VMM_TARGET_ARMV8
-    RT_NOREF(iLeaf, pEax, pEbx, pEcx, pEdx);
+    RT_NOREF(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
     AssertReleaseFailed();
 #else

trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

@@ -63 +63 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     PVM    pVM = pDevIns->Internal.s.pVMR3;
-    PVMCPU pVCpu = pVM->apCpusR3[0];  /* for PIC we always deliver to CPU 0, SMP uses APIC */
 
     /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
@@ -70 +69 @@
 #if defined(VBOX_VMM_TARGET_ARMV8)
     AssertReleaseFailed();
+    RT_NOREF(pVM);
 #else
+    PVMCPU pVCpu = pVM->apCpusR3[0];  /* for PIC we always deliver to CPU 0, SMP uses APIC */
     APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
 #endif
@@ -81 +82 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     PVM pVM = pDevIns->Internal.s.pVMR3;
-    PVMCPU pVCpu = pVM->apCpusR3[0];  /* for PIC we always deliver to CPU 0, SMP uses APIC */
 
     /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
@@ -88 +88 @@
 #if defined(VBOX_VMM_TARGET_ARMV8)
     AssertReleaseFailed();
+    RT_NOREF(pVM);
 #else
+    PVMCPU pVCpu = pVM->apCpusR3[0];  /* for PIC we always deliver to CPU 0, SMP uses APIC */
     APICLocalInterrupt(pVCpu, 0 /* u8Pin */,  0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
 #endif
@@ -136 +138 @@
 {
     PDMDEV_ASSERT_DEVINS(pDevIns);
-    PVM pVM = pDevIns->Internal.s.pVMR3;
     LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
              pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
 #if defined(VBOX_VMM_TARGET_ARMV8)
     AssertReleaseFailed();
+    RT_NOREF(pDevIns, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
     return VERR_NOT_IMPLEMENTED;
 #else
+    PVM pVM = pDevIns->Internal.s.pVMR3;
     return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
 #endif

trunk/src/VBox/VMM/VMMR3/PGM-armv8.cpp

@@ -714 +714 @@
 
     LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
+    RT_NOREF(pVCpu, GCPtr, cb, fFlags, fMask);
 
     AssertReleaseFailed();