Changeset 100118 in vbox
- Timestamp:
- Jun 8, 2023 12:41:57 PM (21 months ago)
- svn:sync-xref-src-repo-rev:
- 157811
- Location:
- trunk
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpumctx-armv8.h
r99976 r100118 147 147 /** The TTBR1_EL1 register. */ 148 148 CPUMCTXSYSREG Ttbr1; 149 /** The VBAR_EL1 register. */ 150 CPUMCTXSYSREG VBar; 149 151 150 152 /** Floating point control register. */ … … 170 172 uint64_t CntvCValEl0; 171 173 172 uint64_t au64Padding2[ 7];174 uint64_t au64Padding2[6]; 173 175 } CPUMCTX; 174 176 … … 231 233 #define CPUMCTX_EXTRN_FPSR UINT64_C(0x0000000000008000) 232 234 235 /** Various system registers (rarely accessed) are kept externally. */ 236 #define CPUMCTX_EXTRN_SYSREG UINT64_C(0x0000000000010000) 237 233 238 /** Mask of bits the keepers can use for state tracking. */ 234 239 #define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000) -
trunk/include/VBox/vmm/dbgf.h
r99379 r100118 2161 2161 DBGFREG_ARMV8_TTBR1_EL1, 2162 2162 DBGFREG_ARMV8_ELR_EL1, 2163 2164 DBGFREG_ARMV8_LAST = DBGFREG_ARMV8_ELR_EL1, 2163 DBGFREG_ARMV8_VBAR_EL1, 2164 2165 DBGFREG_ARMV8_LAST = DBGFREG_ARMV8_VBAR_EL1, 2165 2166 /** @} */ 2166 2167 -
trunk/src/VBox/VMM/VMMR3/CPUMDbg-armv8.cpp
r99379 r100118 280 280 CPU_REG_RW_AS("ttbr1_el1", TTBR1_EL1, U64, Ttbr1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 281 281 CPU_REG_RW_AS("elr_el1", ELR_EL1, U64, Elr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 282 CPU_REG_RW_AS("vbar_el1", VBAR_EL1, U64, VBar, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 282 283 CPU_REG_RW_AS("fpcr", FPCR, U64, fpcr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 283 284 CPU_REG_RW_AS("fpsr", FPSR, U64, fpsr, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), -
trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp
r100117 r100118 190 190 { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) }, 191 191 { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) }, 192 { HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG, RT_UOFFSETOF(CPUMCTX, VBar.u64) }, 192 193 }; 193 194 … … 432 433 "sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n" 433 434 "ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n" 435 "vbar_el1=%016VR{vbar_el1}\n" 434 436 ); 435 437 char szInstr[256]; RT_ZERO(szInstr); … … 478 480 479 481 if ( hrc == HV_SUCCESS 480 && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR )))482 && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG))) 481 483 { 482 484 /* System registers. */ … … 547 549 548 550 if ( hrc == HV_SUCCESS 549 && (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR ))550 != (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR ))551 && (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG)) 552 != (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG)) 551 553 { 552 554 /* System registers. */
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