Changeset 100119 in vbox

Timestamp:

Jun 8, 2023 12:42:48 PM (18 months ago)

Author:

vboxsync

Message:

VMM/CPUM: Implement CPUMGetGuestCodeBits() and CPUMGetGuestDisMode(), bugref:10387

Location:

trunk

Files:

• include/iprt/armv8.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/CPUMAllRegs-armv8.cpp (modified) (3 diffs)

trunk/include/iprt/armv8.h

@@ -444 +444 @@
 #define ARMV8_SPSR_EL2_AARCH64_M4                   RT_BIT_64(4)
 #define ARMV8_SPSR_EL2_AARCH64_M4_BIT               4
-/** Bit 5 - Reserved (read as zero). */
-#define ARMV8_SPSR_EL2_AARCH64_RSVD_5               RT_BIT_64(5)
+/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
+#define ARMV8_SPSR_EL2_AARCH64_T                    RT_BIT_64(5)
+#define ARMV8_SPSR_EL2_AARCH64_T_BIT                5
 /** Bit 6 - I - FIQ interrupt mask. */
 #define ARMV8_SPSR_EL2_AARCH64_F                    RT_BIT_64(6)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs-armv8.cpp

@@ -226 +226 @@
 VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
 {
-    RT_NOREF(pVCpu);
-    AssertReleaseFailed();
-    return false;
+    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
+    return !RT_BOOL(pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_M4);
 }
 
@@ -327 +326 @@
 
 /**
- * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
- *
- * @returns 16, 32 or 64.
+ * Figure whether the CPU is currently executing 32 or 64 bit code.
+ *
+ * @returns 32 or 64.
  * @param   pVCpu               The cross context virtual CPU structure of the calling EMT.
  */
 VMMDECL(uint32_t)       CPUMGetGuestCodeBits(PVMCPU pVCpu)
 {
-    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_PSTATE);
-    AssertReleaseFailed();
-    RT_NOREF(pVCpu);
-    return 16;
+    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
+    if (pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_M4)
+        return 32;
+
+    return 64;
 }
 
@@ -343 +343 @@
 VMMDECL(DISCPUMODE)     CPUMGetGuestDisMode(PVMCPU pVCpu)
 {
-    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_PSTATE);
-    AssertReleaseFailed();
-    RT_NOREF(pVCpu);
-    return DISCPUMODE_16BIT;
+    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
+    if (pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_M4)
+    {
+        if (pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_T)
+            return DISCPUMODE_ARMV8_T32;
+
+        return DISCPUMODE_ARMV8_A32;
+    }
+
+    return DISCPUMODE_ARMV8_A64;
 }