Changeset 10013 in vbox for trunk/src/VBox/VMM

Timestamp:

Jun 30, 2008 11:39:41 AM (16 years ago)

Author:

vboxsync

Message:

AMD64 shadow & real or protected mode without paging combo.
Flush TLB when the EFER msr changes certain bits.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• EMAll.cpp (modified) (2 diffs)
• PGMAllBth.h (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -2356 +2356 @@
     {
         uint64_t uMask = 0;
+        uint64_t oldval = pCtx->msrEFER;
 
         /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
@@ -2377 +2378 @@
         AssertMsg(!(val & ~(MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA /* ignored anyway */ |MSR_K6_EFER_SCE)), ("Unexpected value %RX64\n", val));
         pCtx->msrEFER = (pCtx->msrEFER & ~uMask) | (val & uMask);
+
+        /* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
+        if ((oldval & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)))
+            HWACCMFlushTLB(pVM);
+
         break;
     }

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -1770 +1770 @@
      * Get the shadow PDE, find the shadow page table in the pool.
      */
-    const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
 # if PGM_SHW_TYPE == PGM_TYPE_32BIT
+    const unsigned  iPDDst = GCPtrPage >> SHW_PD_SHIFT;
     X86PDE          PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
-# else /* PAE */
+# elif PGM_SHW_TYPE == PGM_TYPE_PAE
+    const unsigned  iPDDst = GCPtrPage >> SHW_PD_SHIFT;                     /* no mask; flat index into the 2048 entry array. */
     X86PDEPAE       PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
+# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
+    const unsigned  iPDDst   = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
+    const unsigned  iPdpte   = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
+    PX86PDPAE       pPDDst;
+    X86PDEPAE       PdeDst;
+    PX86PDPT        pPdptDst;
+
+    int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
+    AssertRCReturn(rc, rc);
+    Assert(pPDDst && pPdptDst);
+    PdeDst = pPDDst->a[iPDDst];
 # endif
     Assert(PdeDst.n.u1Present);
@@ -2216 +2228 @@
     PX86PD          pPDDst   = pVM->pgm.s.CTXMID(p,32BitPD);
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-    const unsigned  iPDDst   = GCPtrPage >> SHW_PD_SHIFT;               /* 0 - 2047 */
+    const unsigned  iPDDst   = GCPtrPage >> SHW_PD_SHIFT;               /* no mask; flat index into the 2048 entry array. */
     const unsigned  iPdpte   = (GCPtrPage >> X86_PDPT_SHIFT);
     PX86PDPT        pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
     PX86PDPAE       pPDDst   = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
-    const unsigned  iPml4e   = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
     const unsigned  iPdpte   = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
@@ -2603 +2614 @@
      */
 # if PGM_SHW_TYPE == PGM_TYPE_32BIT
+    const unsigned  iPDDst = GCPtrPage >> SHW_PD_SHIFT;
     PX86PD          pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
-# else
+# elif PGM_SHW_TYPE == PGM_TYPE_PAE
+    const unsigned  iPDDst = GCPtrPage >> SHW_PD_SHIFT;             /* no mask; flat index into the 2048 entry array. */
     PX86PDPAE       pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
-# endif
-    const unsigned  iPDDst = GCPtrPage >> SHW_PD_SHIFT;
+# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
+    const unsigned  iPdpte   = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
+    const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
+    PX86PDPAE       pPDDst;
+    PX86PDPT        pPdptDst;
+    rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
+    if (rc != VINF_SUCCESS)
+    {
+        AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
+        return rc;
+    }
+    Assert(pPDDst);
+
+    /* Fetch the pgm pool shadow descriptor. */
+    PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
+    Assert(pShwPde);
+# endif
     PSHWPDE         pPdeDst = &pPDDst->a[iPDDst];
     SHWPDE          PdeDst = *pPdeDst;
@@ -2630 +2658 @@
     /* Virtual address = physical address */
     GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
+# if PGM_SHW_TYPE == PGM_TYPE_AMD64
+    rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx,    iPDDst, &pShwPage);
+# else
     rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
+# endif
 
     if (    rc == VINF_SUCCESS