Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 100230)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 100231)
@@ -6735,5 +6735,5 @@
  * Common 'mov r8, imm8' helper.
  */
-FNIEMOP_DEF_1(iemOpCommonMov_r8_Ib, uint8_t, iReg)
+FNIEMOP_DEF_1(iemOpCommonMov_r8_Ib, uint8_t, iFixedReg)
 {
     uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
@@ -6742,5 +6742,5 @@
     IEM_MC_BEGIN(0, 1);
     IEM_MC_LOCAL_CONST(uint8_t, u8Value,/*=*/ u8Imm);
-    IEM_MC_STORE_GREG_U8(iReg, u8Value);
+    IEM_MC_STORE_GREG_U8(iFixedReg, u8Value);
     IEM_MC_ADVANCE_RIP_AND_FINISH();
     IEM_MC_END();
@@ -6831,5 +6831,5 @@
  * Common 'mov regX,immX' helper.
  */
-FNIEMOP_DEF_1(iemOpCommonMov_Rv_Iv, uint8_t, iReg)
+FNIEMOP_DEF_1(iemOpCommonMov_Rv_Iv, uint8_t, iFixedReg)
 {
     switch (pVCpu->iem.s.enmEffOpSize)
@@ -6842,5 +6842,5 @@
             IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL_CONST(uint16_t, u16Value,/*=*/ u16Imm);
-            IEM_MC_STORE_GREG_U16(iReg, u16Value);
+            IEM_MC_STORE_GREG_U16(iFixedReg, u16Value);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
             IEM_MC_END();
@@ -6855,5 +6855,5 @@
             IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL_CONST(uint32_t, u32Value,/*=*/ u32Imm);
-            IEM_MC_STORE_GREG_U32(iReg, u32Value);
+            IEM_MC_STORE_GREG_U32(iFixedReg, u32Value);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
             IEM_MC_END();
@@ -6867,5 +6867,5 @@
             IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL_CONST(uint64_t, u64Value,/*=*/ u64Imm);
-            IEM_MC_STORE_GREG_U64(iReg, u64Value);
+            IEM_MC_STORE_GREG_U64(iFixedReg, u64Value);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
             IEM_MC_END();
@@ -11139,4 +11139,5 @@
 {
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xdf & 0x7);
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp	(revision 100230)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp	(revision 100231)
@@ -335,5 +335,5 @@
 static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
 {
-    Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x\n", bRm));
+    Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x u16Disp=%#x\n", bRm, u16Disp));
     Assert(!IEM_IS_64BIT_CODE(pVCpu));
 
@@ -390,5 +390,5 @@
 static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint8_t bSib, uint32_t u32Disp) RT_NOEXCEPT
 {
-    Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x\n", bRm));
+    Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x bSib=%#x u32Disp=%#x\n", bRm, bSib, u32Disp));
 
     /* Handle the disp32 form with no registers first. */
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThreadedPython.py
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThreadedPython.py	(revision 100230)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThreadedPython.py	(revision 100231)
@@ -254,4 +254,8 @@
         self.oParent.raiseProblem(sMessage);
 
+    def warning(self, sMessage):
+        """ Emits a warning. """
+        self.oParent.warning(sMessage);
+
     def analyzeReferenceToType(self, sRef):
         """
@@ -283,5 +287,5 @@
             if sRef.startswith('i64'):
                 return 'int64_t';
-            if sRef in ('iReg', 'iGReg', 'iSegReg', 'iSrcReg', 'iDstReg', 'iCrReg'):
+            if sRef in ('iReg', 'iFixedReg', 'iGReg', 'iSegReg', 'iSrcReg', 'iDstReg', 'iCrReg'):
                 return 'uint8_t';
         elif ch0 == 'p':
@@ -372,10 +376,24 @@
 
         sRegRef = oStmt.asParams[idxReg];
-        sOrgExpr = '((%s) < 4 || (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) ? (%s) : (%s) | 16)' % (sRegRef, sRegRef, sRegRef);
-
-        if sRegRef.find('IEM_GET_MODRM_RM') > 0:    sStdRef = 'bRmRm8Ex';
-        elif sRegRef.find('IEM_GET_MODRM_REG') > 0: sStdRef = 'bRmReg8Ex';
-        else:                                       sStdRef = 'bOther8Ex';
-
+        if sRegRef.startswith('IEM_GET_MODRM_RM') >= 0:
+            sOrgExpr = 'IEM_GET_MODRM_RM_EX8(pVCpu, %s)' % (sRegRef,);
+        elif sRegRef.startswith('IEM_GET_MODRM_REG') >= 0:
+            sOrgExpr = 'IEM_GET_MODRM_REG_EX8(pVCpu, %s)' % (sRegRef,);
+        else:
+            sOrgExpr = '((%s) < 4 || (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) ? (%s) : (%s) + 12)' % (sRegRef, sRegRef, sRegRef);
+
+        if sRegRef.find('IEM_GET_MODRM_RM') >= 0:    sStdRef = 'bRmRm8Ex';
+        elif sRegRef.find('IEM_GET_MODRM_REG') >= 0: sStdRef = 'bRmReg8Ex';
+        elif sRegRef == 'X86_GREG_xAX':              sStdRef = 'bGregXAx8Ex';
+        elif sRegRef == 'X86_GREG_xCX':              sStdRef = 'bGregXCx8Ex';
+        elif sRegRef == 'X86_GREG_xSP':              sStdRef = 'bGregXSp8Ex';
+        elif sRegRef == 'iFixedReg':                 sStdRef = 'bFixedReg8Ex';
+        else:
+            self.warning('analyze8BitGRegStmt: sRegRef=%s -> bOther8Ex; %s %s; sOrgExpr=%s'
+                         % (sRegRef, oStmt.sName, oStmt.asParams, sOrgExpr,));
+            sStdRef = 'bOther8Ex';
+
+        #print('analyze8BitGRegStmt: %s %s; sRegRef=%s\n -> idxReg=%s sOrgExpr=%s sStdRef=%s'
+        #      % (oStmt.sName, oStmt.asParams, sRegRef, idxReg, sOrgExpr, sStdRef));
         return (idxReg, sOrgExpr, sStdRef);
 
@@ -463,5 +481,5 @@
                 # ... and IEM_MC_*_GREG_U8 into *_THREADED w/ reworked index taking REX into account
                 elif oNewStmt.sName.startswith('IEM_MC_') and oNewStmt.sName.find('_GREG_U8') > 0:
-                    (idxReg, _, sStdRef) = self.analyze8BitGRegStmt(oNewStmt);
+                    (idxReg, _, sStdRef) = self.analyze8BitGRegStmt(oStmt); # Don't use oNewStmt as it has been modified!
                     oNewStmt.asParams[idxReg] = self.dParamRefs[sStdRef][0].sNewName;
                     oNewStmt.sName += '_THREADED';
@@ -480,4 +498,5 @@
         return (aoThreadedStmts, iParamRef);
 
+
     def analyzeCodeOperation(self, aoStmts):
         """
@@ -488,4 +507,5 @@
         """
         for oStmt in aoStmts:
+            # Pick up hints from CIMPL calls and deferals.
             if oStmt.sName.startswith('IEM_MC_CALL_CIMPL_') or oStmt.sName.startswith('IEM_MC_DEFER_TO_CIMPL_'):
                 sFlagsSansComments = iai.McBlock.stripComments(oStmt.asParams[0]);
@@ -497,4 +517,9 @@
                         else:
                             self.raiseProblem('Unknown CIMPL flag value: %s' % (sFlag,));
+
+            # Set IEM_IMPL_C_F_BRANCH if we see any branching MCs.
+            if (   oStmt.sName.startswith('IEM_MC_SET_RIP')
+                or oStmt.sName.startswith('IEM_MC_REL_JMP')):
+                self.dsCImplFlags['IEM_CIMPL_F_BRANCH'] = True;
 
             # Process branches of conditionals recursively.
@@ -646,5 +671,5 @@
             if oStmt.sName.startswith('IEM_MC_') and oStmt.sName.find('_GREG_U8') > 0:
                 (idxReg, sOrgRef, sStdRef) = self.analyze8BitGRegStmt(oStmt);
-                self.aoParamRefs.append(ThreadedParamRef(sOrgRef, 'uint4_t', oStmt, idxReg, sStdRef = sStdRef));
+                self.aoParamRefs.append(ThreadedParamRef(sOrgRef, 'uint16_t', oStmt, idxReg, sStdRef = sStdRef));
                 aiSkipParams[idxReg] = True; # Skip the parameter below.
 
@@ -887,4 +912,8 @@
         raise Exception('%s:%s: error: %s' % (self.oMcBlock.sSrcFile, self.oMcBlock.iBeginLine, sMessage, ));
 
+    def warning(self, sMessage):
+        """ Emits a warning. """
+        print('%s:%s: warning: %s' % (self.oMcBlock.sSrcFile, self.oMcBlock.iBeginLine, sMessage, ));
+
     def analyzeFindVariablesAndCallArgs(self, aoStmts):
         """ Scans the statements for MC variables and call arguments. """
@@ -1032,4 +1061,15 @@
         #print('McBlock at %s:%s' % (os.path.split(self.oMcBlock.sSrcFile)[1], self.oMcBlock.iBeginLine,));
         aoDecoderStmts = [];
+
+        # Take a very simple approach to problematic instructions for now.
+        if cDepth == 0:
+            dsCImplFlags = {};
+            for oVar in self.aoVariations:
+                dsCImplFlags.update(oVar.dsCImplFlags);
+            if (   'IEM_CIMPL_F_BRANCH' in dsCImplFlags
+                or 'IEM_CIMPL_F_MODE'   in dsCImplFlags
+                or 'IEM_CIMPL_F_REP'    in dsCImplFlags):
+                aoDecoderStmts.append(iai.McCppGeneric('pVCpu->iem.s.fEndTb = true;'));
+
         for oStmt in aoStmts:
             # Copy the statement. Make a deep copy to make sure we've got our own
@@ -1235,4 +1275,7 @@
             '',
             'extern const PFNIEMTHREADEDFUNC g_apfnIemThreadedFunctions[kIemThreadedFunc_End];',
+            '#if defined(IN_RING3) || defined(LOG_ENABLED)',
+            'extern const char * const       g_apszIemThreadedFunctions[kIemThreadedFunc_End];',
+            '#endif',
         ];
 
@@ -1285,6 +1328,6 @@
                                + '\n'
                                + '/**\n'
-                               + ' * %s at line %s offset %s in %s%s\n'
-                                  % (oMcBlock.sFunction, oMcBlock.iBeginLine, oMcBlock.offBeginLine,
+                               + ' * #%u: %s at line %s offset %s in %s%s\n'
+                                  % (oVariation.iEnumValue, oMcBlock.sFunction, oMcBlock.iBeginLine, oMcBlock.offBeginLine,
                                      os.path.split(oMcBlock.sSrcFile)[1],
                                      ' (macro expansion)' if oMcBlock.iBeginLine == oMcBlock.iEndLine else '')
@@ -1373,4 +1416,40 @@
         oOut.write('};\n');
 
+        #
+        # Emit the function name table.
+        #
+        oOut.write(  '\n'
+                   + '\n'
+                   + '#if defined(IN_RING3) || defined(LOG_ENABLED)\n'
+                   + '/**\n'
+                   + ' * Function table.\n'
+                   + ' */\n'
+                   + 'const char * const g_apszIemThreadedFunctions[kIemThreadedFunc_End] =\n'
+                   + '{\n'
+                   + '    "Invalid",\n'
+                   + '\n'
+                   + '    /*\n'
+                   + '     * Predefined.\n'
+                   + '     */'
+                   + '    "BltIn_CheckMode",\n'
+                   );
+        iThreadedFunction = 1;
+        for sVariation in ThreadedFunctionVariation.kasVariationsEmitOrder:
+            oOut.write(  '\n'
+                       + '    /*\n'
+                       + '     * Variation: ' + ThreadedFunctionVariation.kdVariationNames[sVariation] + '\n'
+                       + '     */\n');
+            for oThreadedFunction in self.aoThreadedFuncs:
+                oVariation = oThreadedFunction.dVariations.get(sVariation, None);
+                if oVariation:
+                    iThreadedFunction += 1;
+                    assert oVariation.iEnumValue == iThreadedFunction;
+                    sName = oVariation.getFunctionName();
+                    if sName.startswith('iemThreadedFunc_'):
+                        sName = sName[len('iemThreadedFunc_'):];
+                    oOut.write('    /*%4u*/ "%s",\n' % (iThreadedFunction, sName,));
+        oOut.write(  '};\n'
+                   + '#endif /* IN_RING3 || LOG_ENABLED */\n');
+
         return True;
 
@@ -1441,4 +1520,5 @@
                         assert (   sModified.startswith('IEM_MC_BEGIN')
                                 or (sModified.find('IEM_MC_DEFER_TO_CIMPL_') > 0 and sModified.strip().startswith('{\n'))
+                                or sModified.startswith('pVCpu->iem.s.fEndTb = true')
                                 ), 'sModified="%s"' % (sModified,);
                         oOut.write(sModified);
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThreadedRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThreadedRecompiler.cpp	(revision 100230)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThreadedRecompiler.cpp	(revision 100231)
@@ -2,4 +2,19 @@
 /** @file
  * IEM - Instruction Decoding and Threaded Recompilation.
+ *
+ * Logging group IEM_RE_THREADED assignments:
+ *      - Level 1  (Log)  : Errors, exceptions, interrupts and such major events. [same as IEM]
+ *      - Flow  (LogFlow) :
+ *      - Level 2  (Log2) :
+ *      - Level 3  (Log3) : More detailed enter/exit IEM state info. [same as IEM]
+ *      - Level 4  (Log4) : Decoding mnemonics w/ EIP. [same as IEM]
+ *      - Level 5  (Log5) : Decoding details. [same as IEM]
+ *      - Level 6  (Log6) :
+ *      - Level 7  (Log7) :
+ *      - Level 8  (Log8) : TB compilation.
+ *      - Level 9  (Log9) : TB exec.
+ *      - Level 10 (Log10): TB block lookup.
+ *      - Level 11 (Log11): TB block lookup.
+ *      - Level 12 (Log12): TB insertion.
  */
 
@@ -295,6 +310,4 @@
 }
 
-/** @todo deal with IEM_MC_DEFER_TO_CIMPL_1, IEM_MC_DEFER_TO_CIMPL_2 and
- *        IEM_MC_DEFER_TO_CIMPL_3 as well. */
 
 /*
@@ -435,4 +448,47 @@
  */
 
+#ifdef LOG_ENABLED
+/**
+ * Logs the current instruction.
+ * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
+ * @param   pszFunction The IEM function doing the execution.
+ */
+static void iemThreadedLogCurInstr(PVMCPUCC pVCpu, const char *pszFunction) RT_NOEXCEPT
+{
+# ifdef IN_RING3
+    if (LogIs2Enabled())
+    {
+        char     szInstr[256];
+        uint32_t cbInstr = 0;
+        DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM, pVCpu->idCpu, 0, 0,
+                           DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
+                           szInstr, sizeof(szInstr), &cbInstr);
+
+        PCX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
+        Log2(("**** %s fExec=%x pTb=%p\n"
+              " eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
+              " eip=%08x esp=%08x ebp=%08x iopl=%d tr=%04x\n"
+              " cs=%04x ss=%04x ds=%04x es=%04x fs=%04x gs=%04x efl=%08x\n"
+              " fsw=%04x fcw=%04x ftw=%02x mxcsr=%04x/%04x\n"
+              " %s\n"
+              , pszFunction, pVCpu->iem.s.fExec, pVCpu->iem.s.pCurTbR3,
+              pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ebx, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.esi, pVCpu->cpum.GstCtx.edi,
+              pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.ebp, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, pVCpu->cpum.GstCtx.tr.Sel,
+              pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.ds.Sel, pVCpu->cpum.GstCtx.es.Sel,
+              pVCpu->cpum.GstCtx.fs.Sel, pVCpu->cpum.GstCtx.gs.Sel, pVCpu->cpum.GstCtx.eflags.u,
+              pFpuCtx->FSW, pFpuCtx->FCW, pFpuCtx->FTW, pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK,
+              szInstr));
+
+        if (LogIs3Enabled())
+            DBGFR3InfoEx(pVCpu->pVMR3->pUVM, pVCpu->idCpu, "cpumguest", "verbose", NULL);
+    }
+    else
+# endif
+        LogFlow(("%s: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x\n", pszFunction, pVCpu->cpum.GstCtx.cs.Sel,
+                 pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.rsp, pVCpu->cpum.GstCtx.eflags.u));
+}
+#endif /* LOG_ENABLED */
+
+
 static VBOXSTRICTRC iemThreadedCompileLongJumped(PVMCC pVM, PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict)
 {
@@ -635,4 +691,9 @@
     {
         /* Process the next instruction. */
+#ifdef LOG_ENABLED
+        iemThreadedLogCurInstr(pVCpu, "CC");
+        uint16_t const uCsLog  = pVCpu->cpum.GstCtx.cs.Sel;
+        uint64_t const uRipLog = pVCpu->cpum.GstCtx.rip;
+#endif
         uint8_t b; IEM_OPCODE_GET_FIRST_U8(&b);
         uint16_t const cCallsPrev = pTb->Thrd.cCalls;
@@ -645,7 +706,11 @@
         }
         else if (pTb->Thrd.cCalls > 0)
+        {
+            Log8(("%04x:%08RX64: End TB - %u calls, rc=%d\n", uCsLog, uRipLog, pTb->Thrd.cCalls, VBOXSTRICTRC_VAL(rcStrict)));
             break;
+        }
         else
         {
+            Log8(("%04x:%08RX64: End TB - 0 calls, rc=%d\n", uCsLog, uRipLog, VBOXSTRICTRC_VAL(rcStrict)));
             pVCpu->iem.s.pCurTbR3 = NULL;
             iemThreadedTbFree(pVM, pVCpu, pTb);
@@ -657,5 +722,8 @@
             iemThreadedCompileInitDecoder(pVCpu, true /*fReInit*/);
         else
+        {
+            Log8(("%04x:%08RX64: End TB - %u calls - full\n", uCsLog, uRipLog, pTb->Thrd.cCalls));
             break;
+        }
         iemThreadedCompileReInitOpcodeFetching(pVCpu);
     }
@@ -695,4 +763,9 @@
     while (cCallsLeft-- > 0)
     {
+#ifdef LOG_ENABLED
+        iemThreadedLogCurInstr(pVCpu, "EX");
+        Log9(("%04x:%08RX64: #%d - %d %s\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
+              pTb->Thrd.cCalls - cCallsLeft - 1, pCallEntry->enmFunction, g_apszIemThreadedFunctions[pCallEntry->enmFunction]));
+#endif
         VBOXSTRICTRC const rcStrict = g_apfnIemThreadedFunctions[pCallEntry->enmFunction](pVCpu,
                                                                                           pCallEntry->auParams[0],
Index: trunk/src/VBox/VMM/include/IEMInternal.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInternal.h	(revision 100230)
+++ trunk/src/VBox/VMM/include/IEMInternal.h	(revision 100231)
@@ -3835,4 +3835,29 @@
  */
 #define IEM_GET_MODRM_RM_8(a_bRm)           ( ((a_bRm) & X86_MODRM_RM_MASK) )
+
+/**
+ * Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
+ * register index, with REX.R added in.
+ *
+ * For use during decoding.
+ *
+ * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
+ */
+#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
+    (   (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
+     || !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
+     ? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) | 16)
+/**
+ * Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
+ * with REX.B added in.
+ *
+ * For use during decoding.
+ *
+ * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
+ */
+#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
+    (   (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
+     || !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
+     ? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) | 16)
 
 /**
