VirtualBox

Changeset 100580 in vbox for trunk/src/VBox/ValidationKit


Ignore:
Timestamp:
Jul 14, 2023 2:04:35 PM (19 months ago)
Author:
vboxsync
Message:

ValidationKit: Implement testcases for vinserti128/vinsertf128 instructions, bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r100574 r100580  
    31513151 %endif
    31523152
     3153;
     3154; VINSERTI128
     3155;
     3156EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM1, YMM2, XMM3,  0FFh
     3157EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM1, YMM2, FSxBX, 0FFh
     3158EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM1, YMM2, XMM3,  000h
     3159EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM1, YMM2, FSxBX, 000h
     3160
     3161 %if TMPL_BITS == 64
     3162EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM8, YMM9, XMM10, 0FFh
     3163EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM8, YMM9, FSxBX, 0FFh
     3164EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM8, YMM9, XMM10, 000h
     3165EMIT_INSTR_PLUS_ICEBP   vinserti128, YMM8, YMM9, FSxBX, 000h
     3166 %endif
     3167
     3168;
     3169; VINSERTF128
     3170;
     3171EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM1, YMM2, XMM3,  0FFh
     3172EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM1, YMM2, FSxBX, 0FFh
     3173EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM1, YMM2, XMM3,  000h
     3174EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM1, YMM2, FSxBX, 000h
     3175
     3176 %if TMPL_BITS == 64
     3177EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM8, YMM9, XMM10, 0FFh
     3178EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM8, YMM9, FSxBX, 0FFh
     3179EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM8, YMM9, XMM10, 000h
     3180EMIT_INSTR_PLUS_ICEBP   vinsertf128, YMM8, YMM9, FSxBX, 000h
     3181 %endif
    31533182
    31543183%endif ; BS3_INSTANTIATING_CMN

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r100574 r100580  
    78317831        {  bs3CpuInstr3_mpsadbw_XMM8_XMM9_000h_icebp_c64,          255,         RM_REG, T_SSE4_1,     8, 8,   9, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78327832        {  bs3CpuInstr3_mpsadbw_XMM8_FSxBX_000h_icebp_c64,         255,         RM_MEM, T_SSE4_1,     8, 8, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7833    };
     7834    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     7835    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     7836    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     7837                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     7838}
     7839
     7840
     7841/*
     7842 * VINSERTI128/VINSERTF128 - Insert Packed Integer Values.
     7843 */
     7844BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp);
     7845BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp);
     7846BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp);
     7847BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp);
     7848extern FNBS3FAR             bs3CpuInstr3_vinserti128_YMM8_YMM9_XMM10_0FFh_icebp_c64;
     7849extern FNBS3FAR             bs3CpuInstr3_vinserti128_YMM8_YMM9_FSxBX_0FFh_icebp_c64;
     7850extern FNBS3FAR             bs3CpuInstr3_vinserti128_YMM8_YMM9_XMM10_000h_icebp_c64;
     7851extern FNBS3FAR             bs3CpuInstr3_vinserti128_YMM8_YMM9_FSxBX_000h_icebp_c64;
     7852
     7853BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp);
     7854BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp);
     7855BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp);
     7856BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp);
     7857extern FNBS3FAR             bs3CpuInstr3_vinsertf128_YMM8_YMM9_XMM10_0FFh_icebp_c64;
     7858extern FNBS3FAR             bs3CpuInstr3_vinsertf128_YMM8_YMM9_FSxBX_0FFh_icebp_c64;
     7859extern FNBS3FAR             bs3CpuInstr3_vinsertf128_YMM8_YMM9_XMM10_000h_icebp_c64;
     7860extern FNBS3FAR             bs3CpuInstr3_vinsertf128_YMM8_YMM9_FSxBX_000h_icebp_c64;
     7861
     7862BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vinserti128_vinsertf128(uint8_t bMode)
     7863{
     7864    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] =
     7865    {
     7866        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     7867            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     7868            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     7869        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
     7870            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
     7871            /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0x9192939495969798, 0x8182838485868788) },
     7872    };
     7873    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] =
     7874    {
     7875        {   /*src2*/ RTUINT256_INIT_C(0,   0, 0, 0),
     7876            /*src1*/ RTUINT256_INIT_C(0,   0, 0, 0),
     7877            /* => */ RTUINT256_INIT_C(0,   0, 0, 0) },
     7878        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
     7879            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
     7880            /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) },
     7881    };
     7882
     7883    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     7884    {
     7885        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp_c16,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7886        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7887        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp_c16,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7888        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7889
     7890        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp_c16,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7891        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7892        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp_c16,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7893        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7894    };
     7895    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     7896    {
     7897        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp_c32,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7898        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7899        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp_c32,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7900        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7901
     7902        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp_c32,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7903        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7904        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp_c32,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7905        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7906    };
     7907    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     7908    {
     7909        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp_c64,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7910        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7911        {  bs3CpuInstr3_vinserti128_YMM8_YMM9_XMM10_0FFh_icebp_c64, 255,         RM_REG, T_AVX2_256,   8, 9,  10, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7912        {  bs3CpuInstr3_vinserti128_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   8, 9, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7913        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp_c64,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7914        {  bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7915        {  bs3CpuInstr3_vinserti128_YMM8_YMM9_XMM10_000h_icebp_c64, 255,         RM_REG, T_AVX2_256,   8, 9,  10, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7916        {  bs3CpuInstr3_vinserti128_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   8, 9, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7917
     7918        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp_c64,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7919        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7920        {  bs3CpuInstr3_vinsertf128_YMM8_YMM9_XMM10_0FFh_icebp_c64, 255,         RM_REG, T_AVX2_256,   8, 9,  10, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7921        {  bs3CpuInstr3_vinsertf128_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   8, 9, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7922        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp_c64,  255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7923        {  bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7924        {  bs3CpuInstr3_vinsertf128_YMM8_YMM9_XMM10_000h_icebp_c64, 255,         RM_REG, T_AVX2_256,   8, 9,  10, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7925        {  bs3CpuInstr3_vinsertf128_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,   8, 9, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78337926    };
    78347927    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    1283612929                                                            bs3CpuInstr3_vpbroadcastb_vpbroadcastw_vpbroadcastd_vpbroadcastq_vbroadcasti128,   0 }
    1283712930#endif
     12931#if defined (ALL_TESTS)
     12932        { "vinserti128/vinsertf128",                        bs3CpuInstr3_vinserti128_vinsertf128, 0 },
     12933#endif
    1283812934    };
    1283912935    Bs3TestInit("bs3-cpu-instr-3");
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