Changeset 100714 in vbox

Timestamp:

Jul 27, 2023 10:12:09 AM (16 months ago)

Author:

vboxsync

Message:

VMM/IEM: Require a IEMOP_HLP_DONE_DECODING in all MC blocks so we know exacly when the recompiler starts emitting code (calls) and we can make sure it's still safe to restart insturction decoding. Also made the python script check this and that nothing that smells like decoding happens after IEMOP_HLP_DONE_DECODING and its friends. bugref:10369

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstructionsCommonBodyMacros.h (modified) (3 diffs)
• VMMAll/IEMAllInstructionsOneByte.cpp.h (modified) (266 diffs)
• VMMAll/IEMAllInstructionsPython.py (modified) (4 diffs)
• VMMAll/IEMAllInstructionsThree0f38.cpp.h (modified) (29 diffs)
• VMMAll/IEMAllInstructionsThree0f3a.cpp.h (modified) (24 diffs)
• VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (219 diffs)
• VMMAll/IEMAllInstructionsVexMap1.cpp.h (modified) (53 diffs)
• VMMAll/IEMAllInstructionsVexMap2.cpp.h (modified) (21 diffs)
• VMMAll/IEMAllInstructionsVexMap3.cpp.h (modified) (15 diffs)
• include/IEMOpHlp.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsCommonBodyMacros.h

@@ -47 +47 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         switch (pVCpu->iem.s.enmEffOpSize) \
         { \
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
                 IEM_MC_ARG(uint16_t,   u16Src,  1); \
@@ -67 +67 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
                 IEM_MC_ARG(uint32_t,   u32Src,  1); \
@@ -84 +85 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
                 IEM_MC_ARG(uint64_t,   u64Src,  1); \

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h

@@ -71 +71 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        \
         IEM_MC_BEGIN(3, 0); \
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0); \
@@ -78 +76 @@
         IEM_MC_ARG(uint32_t *, pEFlags, 2); \
          \
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \
         IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
@@ -158 +157 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
+        IEM_MC_BEGIN(3, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_BEGIN(3, 0); \
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0); \
         IEM_MC_ARG(uint8_t,    u8Src,   1); \
@@ -208 +207 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         switch (pVCpu->iem.s.enmEffOpSize) \
         { \
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
                 IEM_MC_ARG(uint16_t,   u16Src,  1); \
@@ -228 +227 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
                 IEM_MC_ARG(uint32_t,   u32Src,  1); \
@@ -245 +245 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
                 IEM_MC_ARG(uint64_t,   u64Src,  1); \
@@ -422 +423 @@
 #define IEMOP_BODY_BINARY_AL_Ib(a_fnNormalU8) \
     uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
     \
     IEM_MC_BEGIN(3, 0); \
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
     IEM_MC_ARG(uint8_t *,       pu8Dst,             0); \
     IEM_MC_ARG_CONST(uint8_t,   u8Src,/*=*/ u8Imm,  1); \
@@ -446 +447 @@
         { \
             uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); \
-            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
             IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ u16Imm,    1); \
@@ -464 +465 @@
         { \
             uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); \
-            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
             IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ u32Imm,    1); \
@@ -484 +485 @@
         { \
             uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); \
-            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
             IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ u64Imm,    1); \
@@ -1554 +1555 @@
  */
 #define IEMOP_BODY_UNARY_GReg(a_fnNormalU16, a_fnNormalU32, a_iReg) \
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
     switch (pVCpu->iem.s.enmEffOpSize) \
     { \
         case IEMMODE_16BIT: \
             IEM_MC_BEGIN(2, 0); \
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint16_t *,  pu16Dst, 0); \
             IEM_MC_ARG(uint32_t *,  pEFlags, 1); \
@@ -1570 +1571 @@
         case IEMMODE_32BIT: \
             IEM_MC_BEGIN(2, 0); \
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint32_t *,  pu32Dst, 0); \
             IEM_MC_ARG(uint32_t *,  pEFlags, 1); \
@@ -1973 +1975 @@
 FNIEMOP_DEF_1(iemOpCommonPushGReg, uint8_t, iReg)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     if (IEM_IS_64BIT_CODE(pVCpu))
     {
@@ -1985 +1986 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Value);
             IEM_MC_FETCH_GREG_U16(u16Value, iReg);
@@ -1994 +1996 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
             IEM_MC_FETCH_GREG_U32(u32Value, iReg);
@@ -2003 +2006 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_FETCH_GREG_U64(u64Value, iReg);
@@ -2064 +2068 @@
     {
         IEM_MC_BEGIN(0, 1);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(uint16_t, u16Value);
         IEM_MC_FETCH_GREG_U16(u16Value, X86_GREG_xSP);
@@ -2110 +2115 @@
 FNIEMOP_DEF_1(iemOpCommonPopGReg, uint8_t, iReg)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     if (IEM_IS_64BIT_CODE(pVCpu))
     {
@@ -2122 +2126 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t *, pu16Dst);
             IEM_MC_REF_GREG_U16(pu16Dst, iReg);
@@ -2131 +2136 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t *, pu32Dst);
             IEM_MC_REF_GREG_U32(pu32Dst, iReg);
@@ -2141 +2147 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t *, pu64Dst);
             IEM_MC_REF_GREG_U64(pu64Dst, iReg);
@@ -2207 +2214 @@
     }
 
-    IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
-                           DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
     /** @todo add testcase for this instruction. */
     switch (pVCpu->iem.s.enmEffOpSize)
@@ -2214 +2219 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
+                                   DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
             IEM_MC_LOCAL(uint16_t, u16Dst);
             IEM_MC_POP_U16(&u16Dst); /** @todo not correct MC, fix later. */
@@ -2223 +2230 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
+                                   DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
             IEM_MC_LOCAL(uint32_t, u32Dst);
             IEM_MC_POP_U32(&u32Dst);
@@ -2232 +2241 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
+                                   DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
             IEM_MC_LOCAL(uint64_t, u64Dst);
             IEM_MC_POP_U64(&u64Dst);
@@ -2462 +2473 @@
     {
         /* Register */
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DECODED_NL_2(OP_ARPL, IEMOPFORM_MR_REG, OP_PARM_Ew, OP_PARM_Gw, DISOPTYPE_HARMLESS);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint16_t *,      pu16Dst,    0);
         IEM_MC_ARG(uint16_t,        u16Src,     1);
@@ -2520 +2531 @@
              * Register to register.
              */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_FETCH_GREG_U32_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -2653 +2664 @@
         {
             uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
+            IEM_MC_BEGIN(0,0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-            IEM_MC_BEGIN(0,0);
             IEM_MC_PUSH_U16(u16Imm);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2664 +2675 @@
         {
             uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
+            IEM_MC_BEGIN(0,0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-            IEM_MC_BEGIN(0,0);
             IEM_MC_PUSH_U32(u32Imm);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2675 +2686 @@
         {
             uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
+            IEM_MC_BEGIN(0,0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-            IEM_MC_BEGIN(0,0);
             IEM_MC_PUSH_U64(u64Imm);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2707 +2718 @@
                 /* register operand */
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
+                IEM_MC_BEGIN(3, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-                IEM_MC_BEGIN(3, 1);
                 IEM_MC_ARG(uint16_t *,      pu16Dst,            0);
                 IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ u16Imm,1);
@@ -2757 +2767 @@
                 /* register operand */
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
+                IEM_MC_BEGIN(3, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-                IEM_MC_BEGIN(3, 1);
                 IEM_MC_ARG(uint32_t *,      pu32Dst,            0);
                 IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ u32Imm,1);
@@ -2807 +2816 @@
                 /* register operand */
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
+                IEM_MC_BEGIN(3, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-                IEM_MC_BEGIN(3, 1);
                 IEM_MC_ARG(uint64_t *,      pu64Dst,            0);
                 IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ u64Imm,1);
@@ -2863 +2871 @@
     IEMOP_HLP_MIN_186();
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
 
@@ -2870 +2877 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_PUSH_U16(i8Imm);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2876 +2884 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_PUSH_U32(i8Imm);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2882 +2891 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_PUSH_U64(i8Imm);
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2910 +2920 @@
                 /* register operand */
                 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
+                IEM_MC_BEGIN(3, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-                IEM_MC_BEGIN(3, 1);
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0);
                 IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ (int8_t)u8Imm, 1);
@@ -2960 +2969 @@
                 /* register operand */
                 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
+                IEM_MC_BEGIN(3, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-                IEM_MC_BEGIN(3, 1);
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0);
                 IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ (int8_t)u8Imm, 1);
@@ -3010 +3018 @@
                 /* register operand */
                 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
+                IEM_MC_BEGIN(3, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-                IEM_MC_BEGIN(3, 1);
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0);
                 IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ (int8_t)u8Imm, 1);
@@ -3257 +3264 @@
     IEMOP_MNEMONIC(jo_Jb, "jo  Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3277 +3284 @@
     IEMOP_MNEMONIC(jno_Jb, "jno Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3296 +3303 @@
     IEMOP_MNEMONIC(jc_Jb, "jc/jnae Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3316 +3323 @@
     IEMOP_MNEMONIC(jnc_Jb, "jnc/jnb Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3336 +3343 @@
     IEMOP_MNEMONIC(je_Jb, "je/jz   Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3356 +3363 @@
     IEMOP_MNEMONIC(jne_Jb, "jne/jnz Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3376 +3383 @@
     IEMOP_MNEMONIC(jbe_Jb, "jbe/jna Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3396 +3403 @@
     IEMOP_MNEMONIC(ja_Jb, "ja/jnbe Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3416 +3423 @@
     IEMOP_MNEMONIC(js_Jb, "js  Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3436 +3443 @@
     IEMOP_MNEMONIC(jns_Jb, "jns Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3456 +3463 @@
     IEMOP_MNEMONIC(jp_Jb, "jp  Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3476 +3483 @@
     IEMOP_MNEMONIC(jnp_Jb, "jnp Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3496 +3503 @@
     IEMOP_MNEMONIC(jl_Jb, "jl/jnge Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3516 +3523 @@
     IEMOP_MNEMONIC(jge_Jb, "jnl/jge Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3536 +3543 @@
     IEMOP_MNEMONIC(jle_Jb, "jle/jng Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
         IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -3556 +3563 @@
     IEMOP_MNEMONIC(jg_Jb, "jnle/jg Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3578 +3585 @@
         /* register target */ \
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
+        IEM_MC_BEGIN(3, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_BEGIN(3, 0); \
         IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
         IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     1); \
@@ -3779 +3786 @@
             { \
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); \
+                IEM_MC_BEGIN(3, 0); \
                 IEMOP_HLP_DONE_DECODING(); \
-                IEM_MC_BEGIN(3, 0); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
                 IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ u16Imm,   1); \
@@ -3797 +3804 @@
             { \
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); \
+                IEM_MC_BEGIN(3, 0); \
                 IEMOP_HLP_DONE_DECODING(); \
-                IEM_MC_BEGIN(3, 0); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
                 IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ u32Imm,   1); \
@@ -3817 +3824 @@
             { \
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); \
+                IEM_MC_BEGIN(3, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_BEGIN(3, 0); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
                 IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ u64Imm,   1); \
@@ -4143 +4150 @@
          * Register target \
          */ \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
         switch (pVCpu->iem.s.enmEffOpSize) \
@@ -4150 +4156 @@
             { \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
                 IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ (int8_t)u8Imm,1); \
@@ -4166 +4173 @@
             { \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
                 IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ (int8_t)u8Imm,1); \
@@ -4184 +4192 @@
             { \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
                 IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ (int8_t)u8Imm,1); \
@@ -4527 +4536 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(0, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 2);
         IEM_MC_LOCAL(uint8_t, uTmp1);
         IEM_MC_LOCAL(uint8_t, uTmp2);
@@ -4553 +4561 @@
 
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_MEM_MAP(pu8Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
         IEM_MC_REF_GREG_U8(pu8Reg, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4580 +4589 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 2);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, uTmp1);
                 IEM_MC_LOCAL(uint16_t, uTmp2);
@@ -4600 +4608 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 2);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, uTmp1);
                 IEM_MC_LOCAL(uint32_t, uTmp2);
@@ -4614 +4623 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 2);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, uTmp1);
                 IEM_MC_LOCAL(uint64_t, uTmp2);
@@ -4644 +4654 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_MEM_MAP(pu16Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
                 IEM_MC_REF_GREG_U16(pu16Reg, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4663 +4674 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_MEM_MAP(pu32Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
                 IEM_MC_REF_GREG_U32(pu32Reg, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4683 +4695 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_MEM_MAP(pu64Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
                 IEM_MC_REF_GREG_U64(pu64Reg, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4716 +4729 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint8_t, u8Value);
         IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4756 +4769 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4770 +4783 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4779 +4793 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -4852 +4867 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint8_t, u8Value);
         IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -4892 +4907 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -4906 +4921 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -4915 +4931 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -5011 +5028 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_FETCH_SREG_U16(u16Value, iSegReg);
@@ -5025 +5042 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_FETCH_SREG_ZX_U32(u32Value, iSegReg);
@@ -5034 +5052 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_FETCH_SREG_ZX_U64(u64Value, iSegReg);
@@ -5149 +5168 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG_CONST(uint8_t, iSRegArg, iSegReg, 0);
         IEM_MC_ARG(uint16_t,      u16Value,          1);
@@ -5390 +5409 @@
 FNIEMOP_DEF_1(iemOpCommonXchgGRegRax, uint8_t, iReg)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     iReg |= pVCpu->iem.s.uRexB;
     switch (pVCpu->iem.s.enmEffOpSize)
@@ -5397 +5414 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0, 2);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Tmp1);
             IEM_MC_LOCAL(uint16_t, u16Tmp2);
@@ -5409 +5427 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0, 2);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Tmp1);
             IEM_MC_LOCAL(uint32_t, u32Tmp2);
@@ -5421 +5440 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0, 2);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Tmp1);
             IEM_MC_LOCAL(uint64_t, u64Tmp2);
@@ -5466 +5486 @@
     else
         IEMOP_MNEMONIC(nop, "nop");
+    /** @todo testcase: lock nop; lock pause */
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING();
     IEM_MC_ADVANCE_RIP_AND_FINISH();
     IEM_MC_END();
@@ -5547 +5569 @@
 FNIEMOP_DEF(iemOp_cbw)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -5553 +5574 @@
             IEMOP_MNEMONIC(cbw, "cbw");
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 7) {
                 IEM_MC_OR_GREG_U16(X86_GREG_xAX, UINT16_C(0xff00));
@@ -5565 +5587 @@
             IEMOP_MNEMONIC(cwde, "cwde");
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 15) {
                 IEM_MC_OR_GREG_U32(X86_GREG_xAX, UINT32_C(0xffff0000));
@@ -5577 +5600 @@
             IEMOP_MNEMONIC(cdqe, "cdqe");
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 31) {
                 IEM_MC_OR_GREG_U64(X86_GREG_xAX, UINT64_C(0xffffffff00000000));
@@ -5596 +5620 @@
 FNIEMOP_DEF(iemOp_cwd)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -5602 +5625 @@
             IEMOP_MNEMONIC(cwd, "cwd");
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 15) {
                 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xDX, UINT16_C(0xffff));
@@ -5614 +5638 @@
             IEMOP_MNEMONIC(cdq, "cdq");
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 31) {
                 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xDX, UINT32_C(0xffffffff));
@@ -5626 +5651 @@
             IEMOP_MNEMONIC(cqo, "cqo");
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 63) {
                 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xDX, UINT64_C(0xffffffffffffffff));
@@ -5665 +5691 @@
 {
     IEMOP_MNEMONIC(wait, "wait");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE();
     IEM_MC_MAYBE_RAISE_FPU_XCPT();
@@ -5705 +5730 @@
 {
     IEMOP_MNEMONIC(sahf, "sahf");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     if (   IEM_IS_64BIT_CODE(pVCpu)
         && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf)
         IEMOP_RAISE_INVALID_OPCODE_RET();
     IEM_MC_BEGIN(0, 2);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint32_t, u32Flags);
     IEM_MC_LOCAL(uint32_t, EFlags);
@@ -5730 +5755 @@
 {
     IEMOP_MNEMONIC(lahf, "lahf");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     if (   IEM_IS_64BIT_CODE(pVCpu)
         && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf)
         IEMOP_RAISE_INVALID_OPCODE_RET();
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint8_t, u8Flags);
     IEM_MC_FETCH_EFLAGS_U8(u8Flags);
@@ -5745 +5770 @@
 /**
  * Macro used by iemOp_mov_AL_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL and
- * iemOp_mov_Ov_rAX to fetch the moffsXX bit of the opcode and fend off lock
- * prefixes.  Will return on failures.
+ * iemOp_mov_Ov_rAX to fetch the moffsXX bit of the opcode.
+ * Will return/throw on failures.
  * @param   a_GCPtrMemOff   The variable to store the offset in.
  */
@@ -5765 +5790 @@
             IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
         } \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
     } while (0)
 
@@ -5774 +5798 @@
 {
     /*
-     * Get the offset and fend off lock prefixes.
+     * Get the offset.
      */
     IEMOP_MNEMONIC(mov_AL_Ob, "mov AL,Ob");
@@ -5784 +5808 @@
      */
     IEM_MC_BEGIN(0,1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint8_t, u8Tmp);
     IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
@@ -5798 +5823 @@
 {
     /*
-     * Get the offset and fend off lock prefixes.
+     * Get the offset.
      */
     IEMOP_MNEMONIC(mov_rAX_Ov, "mov rAX,Ov");
@@ -5811 +5836 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Tmp);
             IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
@@ -5820 +5846 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Tmp);
             IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
@@ -5829 +5856 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Tmp);
             IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
@@ -5847 +5875 @@
 {
     /*
-     * Get the offset and fend off lock prefixes.
+     * Get the offset.
      */
     IEMOP_MNEMONIC(mov_Ob_AL, "mov Ob,AL");
@@ -5857 +5885 @@
      */
     IEM_MC_BEGIN(0,1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint8_t, u8Tmp);
     IEM_MC_FETCH_GREG_U8(u8Tmp, X86_GREG_xAX);
@@ -5871 +5900 @@
 {
     /*
-     * Get the offset and fend off lock prefixes.
+     * Get the offset.
      */
     IEMOP_MNEMONIC(mov_Ov_rAX, "mov Ov,rAX");
@@ -5884 +5913 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Tmp);
             IEM_MC_FETCH_GREG_U16(u16Tmp, X86_GREG_xAX);
@@ -5893 +5923 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Tmp);
             IEM_MC_FETCH_GREG_U32(u32Tmp, X86_GREG_xAX);
@@ -5902 +5933 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Tmp);
             IEM_MC_FETCH_GREG_U64(u64Tmp, X86_GREG_xAX);
@@ -5916 +5948 @@
 #define IEM_MOVS_CASE(ValBits, AddrBits) \
         IEM_MC_BEGIN(0, 2); \
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
         IEM_MC_LOCAL(RTGCPTR,           uAddr); \
@@ -5937 +5970 @@
 FNIEMOP_DEF(iemOp_movsb_Xb_Yb)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -5945 +5976 @@
     {
         IEMOP_MNEMONIC(rep_movsb_Xb_Yb, "rep movsb Xb,Yb");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -5953 +5985 @@
         }
     }
-    IEMOP_MNEMONIC(movsb_Xb_Yb, "movsb Xb,Yb");
 
     /*
      * Sharing case implementation with movs[wdq] below.
      */
+    IEMOP_MNEMONIC(movsb_Xb_Yb, "movsb Xb,Yb");
     switch (pVCpu->iem.s.enmEffAddrMode)
     {
@@ -5973 +6005 @@
 FNIEMOP_DEF(iemOp_movswd_Xv_Yv)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     /*
@@ -5981 +6012 @@
     {
         IEMOP_MNEMONIC(rep_movs_Xv_Yv, "rep movs Xv,Yv");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6011 +6043 @@
         }
     }
-    IEMOP_MNEMONIC(movs_Xv_Yv, "movs Xv,Yv");
 
     /*
@@ -6017 +6048 @@
      * Using ugly macro for implementing the cases, sharing it with movsb.
      */
+    IEMOP_MNEMONIC(movs_Xv_Yv, "movs Xv,Yv");
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -6057 +6089 @@
 #define IEM_CMPS_CASE(ValBits, AddrBits) \
         IEM_MC_BEGIN(3, 3); \
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint##ValBits##_t *, puValue1, 0); \
         IEM_MC_ARG(uint##ValBits##_t,   uValue2,  1); \
@@ -6086 +6119 @@
 FNIEMOP_DEF(iemOp_cmpsb_Xb_Yb)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     /*
@@ -6094 +6126 @@
     {
         IEMOP_MNEMONIC(repz_cmps_Xb_Yb, "repz cmps Xb,Yb");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -6105 +6138 @@
     {
         IEMOP_MNEMONIC(repnz_cmps_Xb_Yb, "repnz cmps Xb,Yb");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -6113 +6147 @@
         }
     }
-    IEMOP_MNEMONIC(cmps_Xb_Yb, "cmps Xb,Yb");
 
     /*
      * Sharing case implementation with cmps[wdq] below.
      */
+    IEMOP_MNEMONIC(cmps_Xb_Yb, "cmps Xb,Yb");
     switch (pVCpu->iem.s.enmEffAddrMode)
     {
@@ -6133 +6167 @@
 FNIEMOP_DEF(iemOp_cmpswd_Xv_Yv)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6141 +6173 @@
     {
         IEMOP_MNEMONIC(repe_cmps_Xv_Yv, "repe cmps Xv,Yv");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6175 +6208 @@
     {
         IEMOP_MNEMONIC(repne_cmps_Xv_Yv, "repne cmps Xv,Yv");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6206 +6240 @@
     }
 
-    IEMOP_MNEMONIC(cmps_Xv_Yv, "cmps Xv,Yv");
-
     /*
      * Annoying double switch here.
      * Using ugly macro for implementing the cases, sharing it with cmpsb.
      */
+    IEMOP_MNEMONIC(cmps_Xv_Yv, "cmps Xv,Yv");
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -6274 +6307 @@
 #define IEM_STOS_CASE(ValBits, AddrBits) \
         IEM_MC_BEGIN(0, 2); \
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
         IEM_MC_LOCAL(RTGCPTR, uAddr); \
@@ -6292 +6326 @@
 FNIEMOP_DEF(iemOp_stosb_Yb_AL)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6300 +6332 @@
     {
         IEMOP_MNEMONIC(rep_stos_Yb_al, "rep stos Yb,al");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -6308 +6341 @@
         }
     }
-    IEMOP_MNEMONIC(stos_Yb_al, "stos Yb,al");
 
     /*
      * Sharing case implementation with stos[wdq] below.
      */
+    IEMOP_MNEMONIC(stos_Yb_al, "stos Yb,al");
     switch (pVCpu->iem.s.enmEffAddrMode)
     {
@@ -6328 +6361 @@
 FNIEMOP_DEF(iemOp_stoswd_Yv_eAX)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6336 +6367 @@
     {
         IEMOP_MNEMONIC(rep_stos_Yv_rAX, "rep stos Yv,rAX");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6366 +6398 @@
         }
     }
-    IEMOP_MNEMONIC(stos_Yv_rAX, "stos Yv,rAX");
 
     /*
@@ -6372 +6403 @@
      * Using ugly macro for implementing the cases, sharing it with stosb.
      */
+    IEMOP_MNEMONIC(stos_Yv_rAX, "stos Yv,rAX");
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -6412 +6444 @@
 #define IEM_LODS_CASE(ValBits, AddrBits) \
         IEM_MC_BEGIN(0, 2); \
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
         IEM_MC_LOCAL(RTGCPTR, uAddr); \
@@ -6430 +6463 @@
 FNIEMOP_DEF(iemOp_lodsb_AL_Xb)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6438 +6469 @@
     {
         IEMOP_MNEMONIC(rep_lodsb_AL_Xb, "rep lodsb AL,Xb");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -6446 +6478 @@
         }
     }
-    IEMOP_MNEMONIC(lodsb_AL_Xb, "lodsb AL,Xb");
 
     /*
      * Sharing case implementation with stos[wdq] below.
      */
+    IEMOP_MNEMONIC(lodsb_AL_Xb, "lodsb AL,Xb");
     switch (pVCpu->iem.s.enmEffAddrMode)
     {
@@ -6466 +6498 @@
 FNIEMOP_DEF(iemOp_lodswd_eAX_Xv)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6474 +6504 @@
     {
         IEMOP_MNEMONIC(rep_lods_rAX_Xv, "rep lods rAX,Xv");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6504 +6535 @@
         }
     }
-    IEMOP_MNEMONIC(lods_rAX_Xv, "lods rAX,Xv");
 
     /*
@@ -6510 +6540 @@
      * Using ugly macro for implementing the cases, sharing it with lodsb.
      */
+    IEMOP_MNEMONIC(lods_rAX_Xv, "lods rAX,Xv");
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -6550 +6581 @@
 #define IEM_SCAS_CASE(ValBits, AddrBits) \
         IEM_MC_BEGIN(3, 2); \
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint##ValBits##_t *, puRax,   0); \
         IEM_MC_ARG(uint##ValBits##_t,   uValue,  1); \
@@ -6574 +6606 @@
 FNIEMOP_DEF(iemOp_scasb_AL_Xb)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6582 +6612 @@
     {
         IEMOP_MNEMONIC(repe_scasb_AL_Xb, "repe scasb AL,Xb");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -6593 +6624 @@
     {
         IEMOP_MNEMONIC(repone_scasb_AL_Xb, "repne scasb AL,Xb");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffAddrMode)
         {
@@ -6601 +6633 @@
         }
     }
-    IEMOP_MNEMONIC(scasb_AL_Xb, "scasb AL,Xb");
 
     /*
      * Sharing case implementation with stos[wdq] below.
      */
+    IEMOP_MNEMONIC(scasb_AL_Xb, "scasb AL,Xb");
     switch (pVCpu->iem.s.enmEffAddrMode)
     {
@@ -6621 +6653 @@
 FNIEMOP_DEF(iemOp_scaswd_eAX_Xv)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /*
      * Use the C implementation if a repeat prefix is encountered.
@@ -6629 +6659 @@
     {
         IEMOP_MNEMONIC(repe_scas_rAX_Xv, "repe scas rAX,Xv");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6662 +6693 @@
     {
         IEMOP_MNEMONIC(repne_scas_rAX_Xv, "repne scas rAX,Xv");
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -6692 +6724 @@
         }
     }
-    IEMOP_MNEMONIC(scas_rAX_Xv, "scas rAX,Xv");
 
     /*
@@ -6698 +6729 @@
      * Using ugly macro for implementing the cases, sharing it with scasb.
      */
+    IEMOP_MNEMONIC(scas_rAX_Xv, "scas rAX,Xv");
     switch (pVCpu->iem.s.enmEffOpSize)
     {
@@ -6741 +6773 @@
 {
     uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL_CONST(uint8_t, u8Value,/*=*/ u8Imm);
     IEM_MC_STORE_GREG_U8(iFixedReg, u8Value);
@@ -6841 +6872 @@
         {
             uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL_CONST(uint16_t, u16Value,/*=*/ u16Imm);
             IEM_MC_STORE_GREG_U16(iFixedReg, u16Value);
@@ -6854 +6884 @@
         {
             uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL_CONST(uint32_t, u32Value,/*=*/ u32Imm);
             IEM_MC_STORE_GREG_U32(iFixedReg, u32Value);
@@ -6866 +6895 @@
         {
             uint64_t u64Imm; IEM_OPCODE_GET_NEXT_U64(&u64Imm); /* 64-bit immediate! */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL_CONST(uint64_t, u64Value,/*=*/ u64Imm);
             IEM_MC_STORE_GREG_U64(iFixedReg, u64Value);
@@ -6986 +7014 @@
         /* register */
         uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint8_t *,       pu8Dst,            0);
         IEM_MC_ARG_CONST(uint8_t,   cShiftArg, cShift, 1);
@@ -7048 +7076 @@
         /* register */
         uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,           0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg, cShift, 1);
@@ -7065 +7093 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,           0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg, cShift, 1);
@@ -7078 +7107 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,           0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg, cShift, 1);
@@ -7338 +7368 @@
         /* register access */
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_RM(pVCpu, bRm), u8Imm);
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7574 +7604 @@
     {
         /* register */
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint8_t *,       pu8Dst,             0);
         IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=*/1,   1);
@@ -7633 +7663 @@
     {
         /* register */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,           0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=1*/1, 1);
@@ -7650 +7680 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,           0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=1*/1, 1);
@@ -7663 +7694 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,           0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=1*/1, 1);
@@ -7768 +7800 @@
     {
         /* register */
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint8_t *,   pu8Dst,     0);
         IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -7828 +7860 @@
     {
         /* register */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,    0);
                 IEM_MC_ARG(uint8_t,         cShiftArg,  1);
@@ -7846 +7878 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,    0);
                 IEM_MC_ARG(uint8_t,         cShiftArg,  1);
@@ -7860 +7893 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,    0);
                 IEM_MC_ARG(uint8_t,         cShiftArg,  1);
@@ -7978 +8012 @@
 {
     IEMOP_MNEMONIC(salc, "salc");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_NO_64BIT();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
         IEM_MC_STORE_GREG_U8_CONST(X86_GREG_xAX, 0xff);
@@ -7998 +8032 @@
 {
     IEMOP_MNEMONIC(xlat, "xlat");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     switch (pVCpu->iem.s.enmEffAddrMode)
     {
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint8_t,  u8Tmp);
             IEM_MC_LOCAL(uint16_t, u16Addr);
@@ -8015 +8049 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint8_t,  u8Tmp);
             IEM_MC_LOCAL(uint32_t, u32Addr);
@@ -8027 +8062 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint8_t,  u8Tmp);
             IEM_MC_LOCAL(uint64_t, u64Addr);
@@ -8051 +8087 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_st0_stN, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(3, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
     IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,        FpuRes,     0);
@@ -8083 +8118 @@
 FNIEMOP_DEF_2(iemOpHlpFpuNoStore_st0_stN, uint8_t, bRm, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(3, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
     IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Fsw,        u16Fsw,     0);
@@ -8115 +8149 @@
 FNIEMOP_DEF_2(iemOpHlpFpuNoStore_st0_stN_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(3, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
     IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Fsw,        u16Fsw,     0);
@@ -8571 +8604 @@
 {
     IEMOP_MNEMONIC(fnop, "fnop");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_MAYBE_RAISE_FPU_XCPT();
@@ -8589 +8621 @@
 {
     IEMOP_MNEMONIC(fld_stN, "fld stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /** @todo Testcase: Check if this raises \#MF?  Intel mentioned it not. AMD
      *        indicates that it does. */
     IEM_MC_BEGIN(0, 2);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -8616 +8647 @@
 {
     IEMOP_MNEMONIC(fxch_stN, "fxch stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     /** @todo Testcase: Check if this raises \#MF?  Intel mentioned it not. AMD
      *        indicates that it does. */
     IEM_MC_BEGIN(2, 3);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value1);
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value2);
@@ -8647 +8677 @@
 {
     IEMOP_MNEMONIC(fstp_st0_stN, "fstp st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     /* fstp st0, st0 is frequently used as an official 'ffreep st0' sequence. */
@@ -8654 +8683 @@
     {
         IEM_MC_BEGIN(0, 1);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL_CONST(uint16_t,        u16Fsw, /*=*/ 0);
         IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -8671 +8701 @@
     {
         IEM_MC_BEGIN(0, 2);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value);
         IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -8698 +8729 @@
 FNIEMOP_DEF_1(iemOpHlpFpu_st0, PFNIEMAIMPLFPUR80UNARY, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(2, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
     IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,    FpuRes, 0);
@@ -8740 +8770 @@
 {
     IEMOP_MNEMONIC(ftst_st0, "ftst st0");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(2, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
     IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Fsw,    u16Fsw, 0);
@@ -8766 +8795 @@
 {
     IEMOP_MNEMONIC(fxam_st0, "fxam st0");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(2, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
     IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Fsw,    u16Fsw, 0);
@@ -8792 +8820 @@
 FNIEMOP_DEF_1(iemOpHlpFpuPushConstant, PFNIEMAIMPLFPUR80LDCONST, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(1, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
     IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,    FpuRes, 0);
@@ -8891 +8918 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(3, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
     IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,        FpuRes,     0);
@@ -8931 +8957 @@
 FNIEMOP_DEF_1(iemOpHlpFpuReplace_st0_push, PFNIEMAIMPLFPUR80UNARYTWO, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(2, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULTTWO,           FpuResTwo);
     IEM_MC_ARG_LOCAL_REF(PIEMFPURESULTTWO,  pFpuResTwo, FpuResTwo,  0);
@@ -8989 +9014 @@
 {
     IEMOP_MNEMONIC(fdecstp, "fdecstp");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     /* Note! C0, C2 and C3 are documented as undefined, we clear them. */
     /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
      *        FINCSTP and FDECSTP. */
-
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -9012 +9036 @@
 {
     IEMOP_MNEMONIC(fincstp, "fincstp");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     /* Note! C0, C2 and C3 are documented as undefined, we clear them. */
     /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
      *        FINCSTP and FDECSTP. */
-
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -9183 +9206 @@
 {
     IEMOP_MNEMONIC(fcmovb_st0_stN, "fcmovb st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9210 +9232 @@
 {
     IEMOP_MNEMONIC(fcmove_st0_stN, "fcmove st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9237 +9258 @@
 {
     IEMOP_MNEMONIC(fcmovbe_st0_stN, "fcmovbe st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9264 +9284 @@
 {
     IEMOP_MNEMONIC(fcmovu_st0_stN, "fcmovu st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9295 +9314 @@
 FNIEMOP_DEF_1(iemOpHlpFpuNoStore_st0_st1_pop_pop, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(3, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
     IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Fsw,        u16Fsw,     0);
@@ -9729 +9747 @@
 {
     IEMOP_MNEMONIC(fcmovnb_st0_stN, "fcmovnb st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9756 +9773 @@
 {
     IEMOP_MNEMONIC(fcmovne_st0_stN, "fcmovne st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9783 +9799 @@
 {
     IEMOP_MNEMONIC(fcmovnbe_st0_stN, "fcmovnbe st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9810 +9825 @@
 {
     IEMOP_MNEMONIC(fcmovnnu_st0_stN, "fcmovnnu st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
 
@@ -9837 +9851 @@
 {
     IEMOP_MNEMONIC(fneni, "fneni (8087/ign)");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -9849 +9863 @@
 {
     IEMOP_MNEMONIC(fndisi, "fndisi (8087/ign)");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -9861 +9875 @@
 {
     IEMOP_MNEMONIC(fnclex, "fnclex");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
@@ -9885 +9898 @@
 {
     IEMOP_MNEMONIC(fnsetpm, "fnsetpm (80287/ign)");   /* set protected mode on fpu. */
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -9898 +9911 @@
     IEMOP_MNEMONIC(frstpm, "frstpm (80287XL/ign)"); /* reset pm, back to real mode. */
 #if 0 /* #UDs on newer CPUs */
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0,0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -9992 +10005 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(3, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
     IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes,        FpuRes,     0);
@@ -10457 +10469 @@
 {
     IEMOP_MNEMONIC(ffree_stN, "ffree stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     /* Note! C0, C1, C2 and C3 are documented as undefined, we leave the
              unmodified. */
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10479 +10490 @@
 {
     IEMOP_MNEMONIC(fst_st0_stN, "fst st0,stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 2);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -10810 +10820 @@
 {
     IEMOP_MNEMONIC(ffreep_stN, "ffreep stN");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10831 +10840 @@
 {
     IEMOP_MNEMONIC(fnstsw_ax, "fnstsw ax");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
     IEM_MC_BEGIN(0, 1);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t, u16Tmp);
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -11184 +11192 @@
     IEMOP_MNEMONIC(loopne_Jb, "loopne Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
 
@@ -11191 +11198 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
             IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
@@ -11202 +11210 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
             IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
@@ -11213 +11222 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
             IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
@@ -11234 +11244 @@
     IEMOP_MNEMONIC(loope_Jb, "loope Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
 
@@ -11241 +11250 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
             IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
@@ -11252 +11262 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
             IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
@@ -11263 +11274 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
             IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
@@ -11284 +11296 @@
     IEMOP_MNEMONIC(loop_Jb, "loop Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
 
@@ -11301 +11312 @@
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0,0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0);
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11308 +11320 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0,0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0);
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11315 +11328 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0,0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0);
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11328 +11342 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,0);
-
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
             IEM_MC_IF_CX_IS_NZ() {
@@ -11340 +11354 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
             IEM_MC_IF_ECX_IS_NZ() {
@@ -11351 +11366 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
             IEM_MC_IF_RCX_IS_NZ() {
@@ -11372 +11388 @@
     IEMOP_MNEMONIC(jecxz_Jb, "jecxz Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
 
@@ -11379 +11394 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_CX_IS_NZ() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11389 +11405 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_ECX_IS_NZ() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11399 +11416 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0,0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_RCX_IS_NZ() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11499 +11517 @@
             int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
             IEM_MC_BEGIN(0, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
             IEM_MC_END();
@@ -11509 +11528 @@
             int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
             IEM_MC_BEGIN(0, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
             IEM_MC_END();
@@ -11547 +11567 @@
     IEMOP_MNEMONIC(jmp_Jb, "jmp Jb");
     int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     IEM_MC_END();
@@ -11681 +11701 @@
 {
     IEMOP_MNEMONIC(cmc, "cmc");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_FLIP_EFL_BIT(X86_EFL_CF);
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11696 +11716 @@
     { \
         /* register access */ \
+        IEM_MC_BEGIN(2, 0); \
         IEMOP_HLP_DONE_DECODING(); \
-        IEM_MC_BEGIN(2, 0); \
         IEM_MC_ARG(uint8_t *,   pu8Dst, 0); \
         IEM_MC_ARG(uint32_t *,  pEFlags, 1); \
@@ -11758 +11778 @@
          * Register target \
          */ \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         switch (pVCpu->iem.s.enmEffOpSize) \
         { \
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(2, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,  pu16Dst, 0); \
                 IEM_MC_ARG(uint32_t *,  pEFlags, 1); \
@@ -11774 +11794 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(2, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,  pu32Dst, 0); \
                 IEM_MC_ARG(uint32_t *,  pEFlags, 1); \
@@ -11786 +11807 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(2, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,  pu64Dst, 0); \
                 IEM_MC_ARG(uint32_t *,  pEFlags, 1); \
@@ -11814 +11836 @@
                     \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
+                    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                     IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \
                     IEM_MC_FETCH_EFLAGS(EFlags); \
@@ -11831 +11854 @@
                     \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
+                    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                     IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \
                     IEM_MC_FETCH_EFLAGS(EFlags); \
@@ -11848 +11872 @@
                     \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
+                    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                     IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \
                     IEM_MC_FETCH_EFLAGS(EFlags); \
@@ -11875 +11900 @@
                     \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
+                    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                     IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \
                     IEM_MC_FETCH_EFLAGS(EFlags); \
@@ -11892 +11918 @@
                     \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
+                    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                     IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \
                     IEM_MC_FETCH_EFLAGS(EFlags); \
@@ -11909 +11936 @@
                     \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
+                    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                     IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \
                     IEM_MC_FETCH_EFLAGS(EFlags); \
@@ -11940 +11968 @@
         /* register access */
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint8_t *,       pu8Dst,             0);
         IEM_MC_ARG_CONST(uint8_t,   u8Src,/*=*/u8Imm,   1);
@@ -11983 +12010 @@
     {
         /* register access */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint16_t *,      pu16AX,     0);
         IEM_MC_ARG(uint8_t,         u8Value,    1);
@@ -12037 +12064 @@
     {
         /* register access */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
             {
+                IEM_MC_BEGIN(4, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_BEGIN(4, 1);
                 IEM_MC_ARG(uint16_t *,      pu16AX,     0);
                 IEM_MC_ARG(uint16_t *,      pu16DX,     1);
@@ -12067 +12093 @@
             case IEMMODE_32BIT:
             {
+                IEM_MC_BEGIN(4, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_BEGIN(4, 1);
                 IEM_MC_ARG(uint32_t *,      pu32AX,     0);
                 IEM_MC_ARG(uint32_t *,      pu32DX,     1);
@@ -12094 +12120 @@
             case IEMMODE_64BIT:
             {
+                IEM_MC_BEGIN(4, 1);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_BEGIN(4, 1);
                 IEM_MC_ARG(uint64_t *,      pu64AX,     0);
                 IEM_MC_ARG(uint64_t *,      pu64DX,     1);
@@ -12278 +12304 @@
     {
         /* register access */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -12285 +12310 @@
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/u16Imm,     1);
@@ -12300 +12326 @@
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/u32Imm,     1);
@@ -12316 +12343 @@
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/u64Imm,     1);
@@ -12467 +12495 @@
 {
     IEMOP_MNEMONIC(clc, "clc");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_CLEAR_EFL_BIT(X86_EFL_CF);
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -12481 +12509 @@
 {
     IEMOP_MNEMONIC(stc, "stc");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_SET_EFL_BIT(X86_EFL_CF);
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -12514 +12542 @@
 {
     IEMOP_MNEMONIC(cld, "cld");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_CLEAR_EFL_BIT(X86_EFL_DF);
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -12528 +12556 @@
 {
     IEMOP_MNEMONIC(std, "std");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_SET_EFL_BIT(X86_EFL_DF);
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -12605 +12633 @@
     {
         /* The new RIP is taken from a register. */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(1, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t, u16Target, 0);
                 IEM_MC_FETCH_GREG_U16(u16Target, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -12618 +12646 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(1, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t, u32Target, 0);
                 IEM_MC_FETCH_GREG_U32(u32Target, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -12626 +12655 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(1, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t, u64Target, 0);
                 IEM_MC_FETCH_GREG_U64(u64Target, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -12768 +12798 @@
     {
         /* The new RIP is taken from a register. */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Target);
                 IEM_MC_FETCH_GREG_U16(u16Target, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -12781 +12811 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Target);
                 IEM_MC_FETCH_GREG_U32(u32Target, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -12789 +12820 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Target);
                 IEM_MC_FETCH_GREG_U64(u64Target, IEM_GET_MODRM_RM(pVCpu, bRm));

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

@@ -2276 +2276 @@
 
                 # Hand it to the handler.
-                fnParser = g_dMcStmtParsers.get(sName);
+                fnParser = g_dMcStmtParsers.get(sName)[0];
                 if not fnParser:
                     self.raiseDecodeError(sRawCode, off, 'Unknown MC statement: %s' % (sName,));
@@ -2387 +2387 @@
                               or sRawCode.find('IEMOP_HLP_DECODED_', off, offEnd) >= 0
                               or sRawCode.find('IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE', off, offEnd) >= 0
+                              or sRawCode.find('IEMOP_HLP_VMX_INSTR', off, offEnd) >= 0
+                              or sRawCode.find('IEMOP_HLP_IN_VMX_OPERATION', off, offEnd) >= 0 ## @todo wrong
                            );
 
@@ -2474 +2476 @@
         return None;
 
+    koReCppFirstWord = re.compile(r'^\s*(\w+)[ (;]');
+    kdDecodeCppStmtOkayAfterDone = {
+        'IEMOP_HLP_IN_VMX_OPERATION': True,
+        'IEMOP_HLP_VMX_INSTR':        True,
+    };
+
+    def checkForDoneDecoding(self, aoStmts):
+        """
+        Checks that the block contains a IEMOP_HLP_DONE_*DECODING* macro
+        invocation.
+        Returns None on success, error string on failure.
+
+        This ensures safe instruction restarting in case the recompiler runs
+        out of TB resources during recompilation (e.g. aRanges or aGCPhysPages
+        entries).
+        """
+
+        # The IEMOP_HLP_DONE_ stuff is not allowed inside conditionals, so we
+        # don't need to look.
+        cIemOpHlpDone = 0;
+        for iStmt, oStmt in enumerate(aoStmts):
+            if oStmt.isCppStmt():
+                #print('dbg: #%u[%u]: %s %s (%s)'
+                #      % (iStmt + 1, cIemOpHlpDone, oStmt.sName, 'd' if oStmt.fDecode else 'r', oStmt.asParams[0],));
+
+                oMatch = self.koReCppFirstWord.match(oStmt.asParams[0]);
+                if oMatch:
+                    sFirstWord = oMatch.group(1);
+                    if (   sFirstWord.startswith('IEMOP_HLP_DONE_')
+                        or sFirstWord.startswith('IEMOP_HLP_DECODED_')):
+                        cIemOpHlpDone += 1;
+                    elif cIemOpHlpDone > 0 and oStmt.fDecode and sFirstWord not in self.kdDecodeCppStmtOkayAfterDone:
+                        return "statement #%u: Decoding statement following IEMOP_HLP_DONE_*DECODING*!" % (iStmt + 1,);
+                #else: print('dbg: #%u[%u]: %s' % (iStmt + 1, cIemOpHlpDone, oStmt.asParams[0]));
+            else:
+                #print('dbg: #%u[%u]: %s' % (iStmt + 1, cIemOpHlpDone, oStmt.sName));
+                if oStmt.sName.startswith('IEM_MC_DEFER_TO_CIMPL_') and iStmt == 0: # implicit
+                    cIemOpHlpDone += 1;
+                elif cIemOpHlpDone == 0 and g_dMcStmtParsers.get(oStmt.sName, (None, False))[1]:
+                    return "statement #%u: State modifying MC statement before IEMOP_HLP_DONE_*DECODING*!" % (iStmt + 1,);
+                elif cIemOpHlpDone > 0  and oStmt.sName in ('IEM_MC_CALC_RM_EFF_ADDR',):
+                    return "statement #%u: Decoding statement following IEMOP_HLP_DONE_*DECODING*!" % (iStmt + 1,);
+        if cIemOpHlpDone == 1:
+            return None;
+        if cIemOpHlpDone > 1:
+            return "Block has more than one IEMOP_HLP_DONE_*DECODING* invocation!";
+        return "Block is missing IEMOP_HLP_DONE_*DECODING* invocation!";
+
     def check(self):
         """
@@ -2486 +2536 @@
             asRet.append(sRet);
 
+        sRet = self.checkForDoneDecoding(aoStmts);
+        if sRet:
+            asRet.append(sRet);
+
         return asRet;
 
 
 
-## IEM_MC_XXX -> parser dictionary.
+## IEM_MC_XXX -> parser + info dictionary.
+#
+# The info is currently a single boolean entry indicating whether the
+# statement modifies state and must not be used before IEMOP_HL_DONE_*.
+#
 # The raw table was generated via the following command
 #       sed -n -e "s/^# *define *\(IEM_MC_[A-Z_0-9]*\)[ (].*$/        '\1': McBlock.parseMcGeneric,/p" include/IEMMc.h \
-#       | sort | uniq | gawk "{printf """    %%-60s %%s\n""", $1, $2}"
+#       | sort | uniq | gawk "{printf """    %%-60s (%%s,        True)\n""", $1, $2}"
 g_dMcStmtParsers = {
-    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE':                     McBlock.parseMcGeneric,
-    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ':                       McBlock.parseMcGeneric,
-    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE':                     McBlock.parseMcGeneric,
-    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ':                       McBlock.parseMcGeneric,
-    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE':                     McBlock.parseMcGeneric,
-    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ':                       McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U16':                                       McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U16_TO_LOCAL':                              McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U32_TO_LOCAL':                              McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U64':                                       McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U64_TO_LOCAL':                              McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U8':                                        McBlock.parseMcGeneric,
-    'IEM_MC_ADD_GREG_U8_TO_LOCAL':                               McBlock.parseMcGeneric,
-    'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR':                          McBlock.parseMcGeneric,
-    'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR':                          McBlock.parseMcGeneric,
-    'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR':                          McBlock.parseMcGeneric,
-    'IEM_MC_ADVANCE_RIP_AND_FINISH':                             McBlock.parseMcGeneric,
-    'IEM_MC_AND_2LOCS_U32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_AND_ARG_U16':                                        McBlock.parseMcGeneric,
-    'IEM_MC_AND_ARG_U32':                                        McBlock.parseMcGeneric,
-    'IEM_MC_AND_ARG_U64':                                        McBlock.parseMcGeneric,
-    'IEM_MC_AND_GREG_U16':                                       McBlock.parseMcGeneric,
-    'IEM_MC_AND_GREG_U32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_AND_GREG_U64':                                       McBlock.parseMcGeneric,
-    'IEM_MC_AND_GREG_U8':                                        McBlock.parseMcGeneric,
-    'IEM_MC_AND_LOCAL_U16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_AND_LOCAL_U32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_AND_LOCAL_U64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_AND_LOCAL_U8':                                       McBlock.parseMcGeneric,
-    'IEM_MC_ARG':                                                McBlock.parseMcArg,
-    'IEM_MC_ARG_CONST':                                          McBlock.parseMcArgConst,
-    'IEM_MC_ARG_LOCAL_EFLAGS':                                   McBlock.parseMcArgLocalEFlags,
-    'IEM_MC_ARG_LOCAL_REF':                                      McBlock.parseMcArgLocalRef,
-    'IEM_MC_ASSIGN':                                             McBlock.parseMcGeneric,
-    'IEM_MC_ASSIGN_TO_SMALLER':                                  McBlock.parseMcGeneric,
-    'IEM_MC_ASSIGN_U8_SX_U64':                                   McBlock.parseMcGeneric,
-    'IEM_MC_ASSIGN_U32_SX_U64':                                  McBlock.parseMcGeneric,
-    'IEM_MC_BEGIN':                                              McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX':                         McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX':                       McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX':                         McBlock.parseMcGeneric,
-    'IEM_MC_BSWAP_LOCAL_U16':                                    McBlock.parseMcGeneric,
-    'IEM_MC_BSWAP_LOCAL_U32':                                    McBlock.parseMcGeneric,
-    'IEM_MC_BSWAP_LOCAL_U64':                                    McBlock.parseMcGeneric,
-    'IEM_MC_CALC_RM_EFF_ADDR':                                   McBlock.parseMcGeneric,
-    'IEM_MC_CALL_AIMPL_3':                                       McBlock.parseMcCallAImpl,
-    'IEM_MC_CALL_AIMPL_4':                                       McBlock.parseMcCallAImpl,
-    'IEM_MC_CALL_AVX_AIMPL_2':                                   McBlock.parseMcCallAvxAImpl,
-    'IEM_MC_CALL_AVX_AIMPL_3':                                   McBlock.parseMcCallAvxAImpl,
-    'IEM_MC_CALL_CIMPL_0':                                       McBlock.parseMcCallCImpl,
-    'IEM_MC_CALL_CIMPL_1':                                       McBlock.parseMcCallCImpl,
-    'IEM_MC_CALL_CIMPL_2':                                       McBlock.parseMcCallCImpl,
-    'IEM_MC_CALL_CIMPL_3':                                       McBlock.parseMcCallCImpl,
-    'IEM_MC_CALL_CIMPL_4':                                       McBlock.parseMcCallCImpl,
-    'IEM_MC_CALL_CIMPL_5':                                       McBlock.parseMcCallCImpl,
-    'IEM_MC_CALL_FPU_AIMPL_1':                                   McBlock.parseMcCallFpuAImpl,
-    'IEM_MC_CALL_FPU_AIMPL_2':                                   McBlock.parseMcCallFpuAImpl,
-    'IEM_MC_CALL_FPU_AIMPL_3':                                   McBlock.parseMcCallFpuAImpl,
-    'IEM_MC_CALL_MMX_AIMPL_2':                                   McBlock.parseMcCallMmxAImpl,
-    'IEM_MC_CALL_MMX_AIMPL_3':                                   McBlock.parseMcCallMmxAImpl,
-    'IEM_MC_CALL_SSE_AIMPL_2':                                   McBlock.parseMcCallSseAImpl,
-    'IEM_MC_CALL_SSE_AIMPL_3':                                   McBlock.parseMcCallSseAImpl,
-    'IEM_MC_CALL_VOID_AIMPL_0':                                  McBlock.parseMcCallVoidAImpl,
-    'IEM_MC_CALL_VOID_AIMPL_1':                                  McBlock.parseMcCallVoidAImpl,
-    'IEM_MC_CALL_VOID_AIMPL_2':                                  McBlock.parseMcCallVoidAImpl,
-    'IEM_MC_CALL_VOID_AIMPL_3':                                  McBlock.parseMcCallVoidAImpl,
-    'IEM_MC_CALL_VOID_AIMPL_4':                                  McBlock.parseMcCallVoidAImpl,
-    'IEM_MC_CLEAR_EFL_BIT':                                      McBlock.parseMcGeneric,
-    'IEM_MC_CLEAR_FSW_EX':                                       McBlock.parseMcGeneric,
-    'IEM_MC_CLEAR_HIGH_GREG_U64':                                McBlock.parseMcGeneric,
-    'IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF':                         McBlock.parseMcGeneric,
-    'IEM_MC_CLEAR_XREG_U32_MASK':                                McBlock.parseMcGeneric,
-    'IEM_MC_CLEAR_YREG_128_UP':                                  McBlock.parseMcGeneric,
-    'IEM_MC_COMMIT_EFLAGS':                                      McBlock.parseMcGeneric,
-    'IEM_MC_COPY_XREG_U128':                                     McBlock.parseMcGeneric,
-    'IEM_MC_COPY_YREG_U128_ZX_VLMAX':                            McBlock.parseMcGeneric,
-    'IEM_MC_COPY_YREG_U256_ZX_VLMAX':                            McBlock.parseMcGeneric,
-    'IEM_MC_COPY_YREG_U64_ZX_VLMAX':                             McBlock.parseMcGeneric,
-    'IEM_MC_DEFER_TO_CIMPL_0_RET':                               McBlock.parseMcGeneric,
-    'IEM_MC_DEFER_TO_CIMPL_1_RET':                               McBlock.parseMcGeneric,
-    'IEM_MC_DEFER_TO_CIMPL_2_RET':                               McBlock.parseMcGeneric,
-    'IEM_MC_DEFER_TO_CIMPL_3_RET':                               McBlock.parseMcGeneric,
-    'IEM_MC_END':                                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_EFLAGS':                                       McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_EFLAGS_U8':                                    McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_FCW':                                          McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_FSW':                                          McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U16':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U16_SX_U32':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U16_SX_U64':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U16_ZX_U32':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U16_ZX_U64':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U32_SX_U64':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U32_ZX_U64':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U64_ZX_U64':                              McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8_SX_U16':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8_SX_U32':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8_SX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8_ZX_U16':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8_ZX_U32':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_GREG_U8_ZX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_D80':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_I16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_I32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_I64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_R32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_R64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_R80':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_S32_SX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U128':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U128_ALIGN_SSE':                           McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U128_NO_AC':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U16_DISP':                                 McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U16_SX_U32':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U16_SX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U16_ZX_U32':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U16_ZX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U256':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U256_ALIGN_AVX':                           McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U256_NO_AC':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U32_DISP':                                 McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U32_SX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U32_ZX_U64':                               McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U64_ALIGN_U128':                           McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U64_DISP':                                 McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8':                                       McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8_SX_U16':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8_SX_U32':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8_SX_U64':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8_ZX_U16':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8_ZX_U32':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_U8_ZX_U64':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_XMM':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_XMM_ALIGN_SSE':                            McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_XMM_NO_AC':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_XMM_U32':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_XMM_U64':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_YMM':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_YMM_ALIGN_AVX':                            McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM_YMM_NO_AC':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM16_U8':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MEM32_U8':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MREG_U32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_MREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_SREG_BASE_U32':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_SREG_BASE_U64':                                McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_SREG_U16':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_SREG_ZX_U32':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_SREG_ZX_U64':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_XREG_U128':                                    McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_XREG_U16':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_XREG_U32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_XREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_XREG_U8':                                      McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_XREG_XMM':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_YREG_2ND_U64':                                 McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_YREG_U128':                                    McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_YREG_U256':                                    McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_YREG_U32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FETCH_YREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FLIP_EFL_BIT':                                       McBlock.parseMcGeneric,
-    'IEM_MC_FPU_FROM_MMX_MODE':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_DEC_TOP':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_FREE':                                     McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_INC_TOP':                                  McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_PUSH_OVERFLOW':                            McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP':                     McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW':                           McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO':                       McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_UNDERFLOW':                                McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP':                         McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP':                McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP':                       McBlock.parseMcGeneric,
-    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP':                   McBlock.parseMcGeneric,
-    'IEM_MC_FPU_TO_MMX_MODE':                                    McBlock.parseMcGeneric,
-    'IEM_MC_IF_CX_IS_NZ':                                        McBlock.parseMcGenericCond,
-    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET':                    McBlock.parseMcGenericCond,
-    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET':                        McBlock.parseMcGenericCond,
-    'IEM_MC_IF_ECX_IS_NZ':                                       McBlock.parseMcGenericCond,
-    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET':                   McBlock.parseMcGenericCond,
-    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET':                       McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_ANY_BITS_SET':                                McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_BIT_NOT_SET':                                 McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ':                     McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_BIT_SET':                                     McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE':                          McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_BITS_EQ':                                     McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_BITS_NE':                                     McBlock.parseMcGenericCond,
-    'IEM_MC_IF_EFL_NO_BITS_SET':                                 McBlock.parseMcGenericCond,
-    'IEM_MC_IF_FCW_IM':                                          McBlock.parseMcGenericCond,
-    'IEM_MC_IF_FPUREG_IS_EMPTY':                                 McBlock.parseMcGenericCond,
-    'IEM_MC_IF_FPUREG_NOT_EMPTY':                                McBlock.parseMcGenericCond,
-    'IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80':                        McBlock.parseMcGenericCond,
-    'IEM_MC_IF_GREG_BIT_SET':                                    McBlock.parseMcGenericCond,
-    'IEM_MC_IF_LOCAL_IS_Z':                                      McBlock.parseMcGenericCond,
-    'IEM_MC_IF_MXCSR_XCPT_PENDING':                              McBlock.parseMcGenericCond,
-    'IEM_MC_IF_RCX_IS_NZ':                                       McBlock.parseMcGenericCond,
-    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET':                   McBlock.parseMcGenericCond,
-    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET':                       McBlock.parseMcGenericCond,
-    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80':                   McBlock.parseMcGenericCond,
-    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST':             McBlock.parseMcGenericCond,
-    'IEM_MC_IMPLICIT_AVX_AIMPL_ARGS':                            McBlock.parseMcGeneric,
-    'IEM_MC_INT_CLEAR_ZMM_256_UP':                               McBlock.parseMcGeneric,
-    'IEM_MC_LOCAL':                                              McBlock.parseMcLocal,
-    'IEM_MC_LOCAL_CONST':                                        McBlock.parseMcLocalConst,
-    'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT':                       McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE':                   McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_FPU_XCPT':                               McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT':                          McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT':                       McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0':                 McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':             McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT':                       McBlock.parseMcGeneric,
-    'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE':              McBlock.parseMcGeneric,
-    'IEM_MC_MEM_COMMIT_AND_UNMAP':                               McBlock.parseMcGeneric,
-    'IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE':                 McBlock.parseMcGeneric,
-    'IEM_MC_MEM_MAP':                                            McBlock.parseMcGeneric,
-    'IEM_MC_MEM_MAP_EX':                                         McBlock.parseMcGeneric,
-    'IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX':                        McBlock.parseMcGeneric,
-    'IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX':                    McBlock.parseMcGeneric,
-    'IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX':                    McBlock.parseMcGeneric,
-    'IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX':                 McBlock.parseMcGeneric,
-    'IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX':                 McBlock.parseMcGeneric,
-    'IEM_MC_MODIFIED_MREG':                                      McBlock.parseMcGeneric,
-    'IEM_MC_MODIFIED_MREG_BY_REF':                               McBlock.parseMcGeneric,
-    'IEM_MC_OR_2LOCS_U32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_OR_GREG_U16':                                        McBlock.parseMcGeneric,
-    'IEM_MC_OR_GREG_U32':                                        McBlock.parseMcGeneric,
-    'IEM_MC_OR_GREG_U64':                                        McBlock.parseMcGeneric,
-    'IEM_MC_OR_GREG_U8':                                         McBlock.parseMcGeneric,
-    'IEM_MC_OR_LOCAL_U16':                                       McBlock.parseMcGeneric,
-    'IEM_MC_OR_LOCAL_U32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_OR_LOCAL_U8':                                        McBlock.parseMcGeneric,
-    'IEM_MC_POP_U16':                                            McBlock.parseMcGeneric,
-    'IEM_MC_POP_U32':                                            McBlock.parseMcGeneric,
-    'IEM_MC_POP_U64':                                            McBlock.parseMcGeneric,
-    'IEM_MC_PREPARE_AVX_USAGE':                                  McBlock.parseMcGeneric,
-    'IEM_MC_PREPARE_FPU_USAGE':                                  McBlock.parseMcGeneric,
-    'IEM_MC_PREPARE_SSE_USAGE':                                  McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_FPU_RESULT':                                    McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_FPU_RESULT_MEM_OP':                             McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_FPU_RESULT_TWO':                                McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_U16':                                           McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_U32':                                           McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_U32_SREG':                                      McBlock.parseMcGeneric,
-    'IEM_MC_PUSH_U64':                                           McBlock.parseMcGeneric,
-    'IEM_MC_RAISE_DIVIDE_ERROR':                                 McBlock.parseMcGeneric,
-    'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO':                          McBlock.parseMcGeneric,
-    'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED':                    McBlock.parseMcGeneric,
-    'IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':                   McBlock.parseMcGeneric,
-    'IEM_MC_REF_EFLAGS':                                         McBlock.parseMcGeneric,
-    'IEM_MC_REF_FPUREG':                                         McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_I32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_I32_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_I64':                                       McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_I64_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_U16':                                       McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_U32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_U64':                                       McBlock.parseMcGeneric,
-    'IEM_MC_REF_GREG_U8':                                        McBlock.parseMcGeneric,
-    'IEM_MC_REF_LOCAL':                                          McBlock.parseMcGeneric,
-    'IEM_MC_REF_MREG_U32_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_MREG_U64':                                       McBlock.parseMcGeneric,
-    'IEM_MC_REF_MREG_U64_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_MXCSR':                                          McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_R32_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_R64_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_U128':                                      McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_U128_CONST':                                McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_U32_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_U64_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_XREG_XMM_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REF_YREG_U128':                                      McBlock.parseMcGeneric,
-    'IEM_MC_REF_YREG_U128_CONST':                                McBlock.parseMcGeneric,
-    'IEM_MC_REF_YREG_U64_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_REL_JMP_S16_AND_FINISH':                             McBlock.parseMcGeneric,
-    'IEM_MC_REL_JMP_S32_AND_FINISH':                             McBlock.parseMcGeneric,
-    'IEM_MC_REL_JMP_S8_AND_FINISH':                              McBlock.parseMcGeneric,
-    'IEM_MC_RETURN_ON_FAILURE':                                  McBlock.parseMcGeneric,
-    'IEM_MC_SAR_LOCAL_S16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_SAR_LOCAL_S32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_SAR_LOCAL_S64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_SET_EFL_BIT':                                        McBlock.parseMcGeneric,
-    'IEM_MC_SET_FPU_RESULT':                                     McBlock.parseMcGeneric,
-    'IEM_MC_SET_RIP_U16_AND_FINISH':                             McBlock.parseMcGeneric,
-    'IEM_MC_SET_RIP_U32_AND_FINISH':                             McBlock.parseMcGeneric,
-    'IEM_MC_SET_RIP_U64_AND_FINISH':                             McBlock.parseMcGeneric,
-    'IEM_MC_SHL_LOCAL_S16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_SHL_LOCAL_S32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_SHL_LOCAL_S64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_SHR_LOCAL_U8':                                       McBlock.parseMcGeneric,
-    'IEM_MC_SSE_UPDATE_MXCSR':                                   McBlock.parseMcGeneric,
-    'IEM_MC_STORE_FPU_RESULT':                                   McBlock.parseMcGeneric,
-    'IEM_MC_STORE_FPU_RESULT_MEM_OP':                            McBlock.parseMcGeneric,
-    'IEM_MC_STORE_FPU_RESULT_THEN_POP':                          McBlock.parseMcGeneric,
-    'IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP':              McBlock.parseMcGeneric,
-    'IEM_MC_STORE_FPUREG_R80_SRC_REF':                           McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_I64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U16':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U16_CONST':                               McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U32_CONST':                               McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U64_CONST':                               McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U8':                                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_GREG_U8_CONST':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_I16_CONST_BY_REF':                         McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_I32_CONST_BY_REF':                         McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_I64_CONST_BY_REF':                         McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_I8_CONST_BY_REF':                          McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_INDEF_D80_BY_REF':                         McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF':                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF':                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF':                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U128':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U128_ALIGN_SSE':                           McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U16_CONST':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U256':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U256_ALIGN_AVX':                           McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U32':                                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U32_CONST':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U64':                                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U64_CONST':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U8':                                       McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MEM_U8_CONST':                                 McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MREG_U32_ZX_U64':                              McBlock.parseMcGeneric,
-    'IEM_MC_STORE_MREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_SREG_BASE_U32':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_SREG_BASE_U64':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_SSE_RESULT':                                   McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_HI_U64':                                  McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_R32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_R64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U128':                                    McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U16':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U32':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U32_U128':                                McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U32_ZX_U128':                             McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U64':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U64_ZX_U128':                             McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_U8':                                      McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_XMM':                                     McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_XMM_U32':                                 McBlock.parseMcGeneric,
-    'IEM_MC_STORE_XREG_XMM_U64':                                 McBlock.parseMcGeneric,
-    'IEM_MC_STORE_YREG_U128':                                    McBlock.parseMcGeneric,
-    'IEM_MC_STORE_YREG_U128_ZX_VLMAX':                           McBlock.parseMcGeneric,
-    'IEM_MC_STORE_YREG_U256_ZX_VLMAX':                           McBlock.parseMcGeneric,
-    'IEM_MC_STORE_YREG_U32_ZX_VLMAX':                            McBlock.parseMcGeneric,
-    'IEM_MC_STORE_YREG_U64_ZX_VLMAX':                            McBlock.parseMcGeneric,
-    'IEM_MC_SUB_GREG_U16':                                       McBlock.parseMcGeneric,
-    'IEM_MC_SUB_GREG_U32':                                       McBlock.parseMcGeneric,
-    'IEM_MC_SUB_GREG_U64':                                       McBlock.parseMcGeneric,
-    'IEM_MC_SUB_GREG_U8':                                        McBlock.parseMcGeneric,
-    'IEM_MC_SUB_LOCAL_U16':                                      McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FPU_OPCODE_IP':                               McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FSW':                                         McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FSW_CONST':                                   McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FSW_THEN_POP':                                McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FSW_THEN_POP_POP':                            McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FSW_WITH_MEM_OP':                             McBlock.parseMcGeneric,
-    'IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP':                    McBlock.parseMcGeneric,
+    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ADD_GREG_U16':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADD_GREG_U16_TO_LOCAL':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ADD_GREG_U32':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADD_GREG_U32_TO_LOCAL':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ADD_GREG_U64':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADD_GREG_U64_TO_LOCAL':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ADD_GREG_U8':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADD_GREG_U8_TO_LOCAL':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ADVANCE_RIP_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_AND_2LOCS_U32':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_ARG_U16':                                        (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_ARG_U32':                                        (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_ARG_U64':                                        (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_GREG_U16':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_AND_GREG_U32':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_AND_GREG_U64':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_AND_GREG_U8':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_AND_LOCAL_U16':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_LOCAL_U32':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_LOCAL_U64':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_AND_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ARG':                                                (McBlock.parseMcArg,               False),
+    'IEM_MC_ARG_CONST':                                          (McBlock.parseMcArgConst,          False),
+    'IEM_MC_ARG_LOCAL_EFLAGS':                                   (McBlock.parseMcArgLocalEFlags,    False),
+    'IEM_MC_ARG_LOCAL_REF':                                      (McBlock.parseMcArgLocalRef,       False),
+    'IEM_MC_ASSIGN':                                             (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ASSIGN_TO_SMALLER':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ASSIGN_U8_SX_U64':                                   (McBlock.parseMcGeneric,           False),
+    'IEM_MC_ASSIGN_U32_SX_U64':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_BEGIN':                                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX':                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_BSWAP_LOCAL_U16':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_BSWAP_LOCAL_U32':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_BSWAP_LOCAL_U64':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_CALC_RM_EFF_ADDR':                                   (McBlock.parseMcGeneric,           False),
+    'IEM_MC_CALL_AIMPL_3':                                       (McBlock.parseMcCallAImpl,         True),
+    'IEM_MC_CALL_AIMPL_4':                                       (McBlock.parseMcCallAImpl,         True),
+    'IEM_MC_CALL_AVX_AIMPL_2':                                   (McBlock.parseMcCallAvxAImpl,      True),
+    'IEM_MC_CALL_AVX_AIMPL_3':                                   (McBlock.parseMcCallAvxAImpl,      True),
+    'IEM_MC_CALL_CIMPL_0':                                       (McBlock.parseMcCallCImpl,         True),
+    'IEM_MC_CALL_CIMPL_1':                                       (McBlock.parseMcCallCImpl,         True),
+    'IEM_MC_CALL_CIMPL_2':                                       (McBlock.parseMcCallCImpl,         True),
+    'IEM_MC_CALL_CIMPL_3':                                       (McBlock.parseMcCallCImpl,         True),
+    'IEM_MC_CALL_CIMPL_4':                                       (McBlock.parseMcCallCImpl,         True),
+    'IEM_MC_CALL_CIMPL_5':                                       (McBlock.parseMcCallCImpl,         True),
+    'IEM_MC_CALL_FPU_AIMPL_1':                                   (McBlock.parseMcCallFpuAImpl,      True),
+    'IEM_MC_CALL_FPU_AIMPL_2':                                   (McBlock.parseMcCallFpuAImpl,      True),
+    'IEM_MC_CALL_FPU_AIMPL_3':                                   (McBlock.parseMcCallFpuAImpl,      True),
+    'IEM_MC_CALL_MMX_AIMPL_2':                                   (McBlock.parseMcCallMmxAImpl,      True),
+    'IEM_MC_CALL_MMX_AIMPL_3':                                   (McBlock.parseMcCallMmxAImpl,      True),
+    'IEM_MC_CALL_SSE_AIMPL_2':                                   (McBlock.parseMcCallSseAImpl,      True),
+    'IEM_MC_CALL_SSE_AIMPL_3':                                   (McBlock.parseMcCallSseAImpl,      True),
+    'IEM_MC_CALL_VOID_AIMPL_0':                                  (McBlock.parseMcCallVoidAImpl,     True),
+    'IEM_MC_CALL_VOID_AIMPL_1':                                  (McBlock.parseMcCallVoidAImpl,     True),
+    'IEM_MC_CALL_VOID_AIMPL_2':                                  (McBlock.parseMcCallVoidAImpl,     True),
+    'IEM_MC_CALL_VOID_AIMPL_3':                                  (McBlock.parseMcCallVoidAImpl,     True),
+    'IEM_MC_CALL_VOID_AIMPL_4':                                  (McBlock.parseMcCallVoidAImpl,     True),
+    'IEM_MC_CLEAR_EFL_BIT':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_CLEAR_FSW_EX':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_CLEAR_HIGH_GREG_U64':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_CLEAR_XREG_U32_MASK':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_CLEAR_YREG_128_UP':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_COMMIT_EFLAGS':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_COPY_XREG_U128':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_COPY_YREG_U128_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_COPY_YREG_U256_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_COPY_YREG_U64_ZX_VLMAX':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_DEFER_TO_CIMPL_0_RET':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_DEFER_TO_CIMPL_1_RET':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_DEFER_TO_CIMPL_2_RET':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_DEFER_TO_CIMPL_3_RET':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_END':                                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_EFLAGS':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_EFLAGS_U8':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_FCW':                                          (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_FSW':                                          (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U16':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U16_SX_U32':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U16_SX_U64':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U16_ZX_U32':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U16_ZX_U64':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U32':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U32_SX_U64':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U32_ZX_U64':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U64':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U64_ZX_U64':                              (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8_SX_U16':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8_SX_U32':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8_SX_U64':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8_ZX_U16':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8_ZX_U32':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_GREG_U8_ZX_U64':                               (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_MEM_D80':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_I16':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_I32':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_I64':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_R32':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_R64':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_R80':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_S32_SX_U64':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U128':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U128_NO_AC':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U16':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U16_DISP':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U16_SX_U32':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U16_SX_U64':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U16_ZX_U32':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U16_ZX_U64':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U256':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U256_ALIGN_AVX':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U256_NO_AC':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U32':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U32_DISP':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U32_SX_U64':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U32_ZX_U64':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U64':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U64_ALIGN_U128':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U64_DISP':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8_SX_U16':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8_SX_U32':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8_SX_U64':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8_ZX_U16':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8_ZX_U32':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_U8_ZX_U64':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_XMM':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_XMM_ALIGN_SSE':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_XMM_NO_AC':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_XMM_U32':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_XMM_U64':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_YMM':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_YMM_ALIGN_AVX':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM_YMM_NO_AC':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM16_U8':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MEM32_U8':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FETCH_MREG_U32':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_MREG_U64':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_SREG_BASE_U32':                                (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_SREG_BASE_U64':                                (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_SREG_U16':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_SREG_ZX_U32':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_SREG_ZX_U64':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_XREG_U128':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_XREG_U16':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_XREG_U32':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_XREG_U64':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_XREG_U8':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_XREG_XMM':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_YREG_2ND_U64':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_YREG_U128':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_YREG_U256':                                    (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_YREG_U32':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FETCH_YREG_U64':                                     (McBlock.parseMcGeneric,           False),
+    'IEM_MC_FLIP_EFL_BIT':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_FROM_MMX_MODE':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_DEC_TOP':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_FREE':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_INC_TOP':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_PUSH_OVERFLOW':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP':                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO':                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_UNDERFLOW':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP':                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP':                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP':                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_FPU_TO_MMX_MODE':                                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_IF_CX_IS_NZ':                                        (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET':                    (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET':                        (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_ECX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET':                   (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET':                       (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_ANY_BITS_SET':                                (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_BIT_NOT_SET':                                 (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ':                     (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_BIT_SET':                                     (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE':                          (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_BITS_EQ':                                     (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_BITS_NE':                                     (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_EFL_NO_BITS_SET':                                 (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_FCW_IM':                                          (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_FPUREG_IS_EMPTY':                                 (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_FPUREG_NOT_EMPTY':                                (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80':                        (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_GREG_BIT_SET':                                    (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_LOCAL_IS_Z':                                      (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_MXCSR_XCPT_PENDING':                              (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_RCX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET':                   (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET':                       (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80':                   (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST':             (McBlock.parseMcGenericCond,       True),
+    'IEM_MC_IMPLICIT_AVX_AIMPL_ARGS':                            (McBlock.parseMcGeneric,           False),
+    'IEM_MC_INT_CLEAR_ZMM_256_UP':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_LOCAL':                                              (McBlock.parseMcLocal,             False),
+    'IEM_MC_LOCAL_CONST':                                        (McBlock.parseMcLocalConst,        False),
+    'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE':                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_FPU_XCPT':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0':                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE':              (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE':                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MEM_MAP':                                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MEM_MAP_EX':                                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX':                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX':                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX':                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX':                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MODIFIED_MREG':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_MODIFIED_MREG_BY_REF':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_OR_2LOCS_U32':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_OR_GREG_U16':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_OR_GREG_U32':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_OR_GREG_U64':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_OR_GREG_U8':                                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_OR_LOCAL_U16':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_OR_LOCAL_U32':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_OR_LOCAL_U8':                                        (McBlock.parseMcGeneric,           False),
+    'IEM_MC_POP_U16':                                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_POP_U32':                                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_POP_U64':                                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PREPARE_AVX_USAGE':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_PREPARE_FPU_USAGE':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_PREPARE_SSE_USAGE':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_PUSH_FPU_RESULT':                                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PUSH_FPU_RESULT_MEM_OP':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PUSH_FPU_RESULT_TWO':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PUSH_U16':                                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PUSH_U32':                                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PUSH_U32_SREG':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_PUSH_U64':                                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_RAISE_DIVIDE_ERROR':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED':                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_REF_EFLAGS':                                         (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_FPUREG':                                         (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_I32':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_I32_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_I64':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_I64_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_U16':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_U32':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_U64':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_GREG_U8':                                        (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_LOCAL':                                          (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_MREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_MREG_U64':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_MREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_MXCSR':                                          (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_R32_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_R64_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_U128':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_U128_CONST':                                (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_XREG_XMM_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_YREG_U128':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_YREG_U128_CONST':                                (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REF_YREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
+    'IEM_MC_REL_JMP_S16_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_REL_JMP_S32_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_REL_JMP_S8_AND_FINISH':                              (McBlock.parseMcGeneric,           True),
+    'IEM_MC_RETURN_ON_FAILURE':                                  (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SAR_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SAR_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SAR_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SET_EFL_BIT':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SET_FPU_RESULT':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SET_RIP_U16_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SET_RIP_U32_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SET_RIP_U64_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SHL_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SHL_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SHL_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SHR_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False),
+    'IEM_MC_SSE_UPDATE_MXCSR':                                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_FPU_RESULT':                                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_FPU_RESULT_MEM_OP':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_FPU_RESULT_THEN_POP':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP':              (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_FPUREG_R80_SRC_REF':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_I64':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U16':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U16_CONST':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U32':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U32_CONST':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U64':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U64_CONST':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U8':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_GREG_U8_CONST':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_I16_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_I32_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_I64_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_I8_CONST_BY_REF':                          (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_INDEF_D80_BY_REF':                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF':                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF':                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF':                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U128':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U16':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U16_CONST':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U256':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U256_ALIGN_AVX':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U32':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U32_CONST':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U64':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U64_CONST':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U8':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MEM_U8_CONST':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MREG_U32_ZX_U64':                              (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_MREG_U64':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_SREG_BASE_U32':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_SREG_BASE_U64':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_SSE_RESULT':                                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_HI_U64':                                  (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_R32':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_R64':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U128':                                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U16':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U32':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U32_U128':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U32_ZX_U128':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U64':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U64_ZX_U128':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_U8':                                      (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_XMM':                                     (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_XMM_U32':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_XREG_XMM_U64':                                 (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_YREG_U128':                                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_YREG_U128_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_YREG_U256_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_YREG_U32_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_STORE_YREG_U64_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SUB_GREG_U16':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SUB_GREG_U32':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SUB_GREG_U64':                                       (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SUB_GREG_U8':                                        (McBlock.parseMcGeneric,           True),
+    'IEM_MC_SUB_LOCAL_U16':                                      (McBlock.parseMcGeneric,           False),
+    'IEM_MC_UPDATE_FPU_OPCODE_IP':                               (McBlock.parseMcGeneric,           True),
+    'IEM_MC_UPDATE_FSW':                                         (McBlock.parseMcGeneric,           True),
+    'IEM_MC_UPDATE_FSW_CONST':                                   (McBlock.parseMcGeneric,           True),
+    'IEM_MC_UPDATE_FSW_THEN_POP':                                (McBlock.parseMcGeneric,           True),
+    'IEM_MC_UPDATE_FSW_THEN_POP_POP':                            (McBlock.parseMcGeneric,           True),
+    'IEM_MC_UPDATE_FSW_WITH_MEM_OP':                             (McBlock.parseMcGeneric,           True),
+    'IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP':                    (McBlock.parseMcGeneric,           True),
 };
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h

@@ -49 +49 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -111 +111 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -167 +167 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -226 +226 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -282 +282 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -342 +342 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -402 +402 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -690 +690 @@
          * Register, register. \
          */ \
+        IEM_MC_BEGIN(3, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
-        IEM_MC_BEGIN(3, 0); \
         IEM_MC_ARG(PRTUINT128U,  puDst,  0); \
         IEM_MC_ARG(PCRTUINT128U, puSrc,  1); \
@@ -785 +785 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc1,  0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc2,  1);
@@ -906 +906 @@
          * Register, register. \
          */ \
+        IEM_MC_BEGIN(2, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
-        IEM_MC_BEGIN(2, 0); \
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0); \
         IEM_MC_ARG(uint64_t,    uSrc, 1); \
@@ -1310 +1310 @@
 {
     IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-    IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
-    IEMOP_HLP_VMX_INSTR("invept", kVmxVDiag_Invept);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if (IEM_IS_MODRM_MEM_MODE(bRm))
@@ -1325 +1322 @@
             IEM_MC_FETCH_GREG_U64(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
+            IEMOP_HLP_VMX_INSTR(       "invept", kVmxVDiag_Invept);
             IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
             IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS,
@@ -1338 +1338 @@
             IEM_MC_FETCH_GREG_U32(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
+            IEMOP_HLP_VMX_INSTR(       "invept", kVmxVDiag_Invept);
             IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
             IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS,
@@ -1345 +1348 @@
     }
     Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_RAISE_INVALID_OPCODE_RET();
 }
@@ -1356 +1360 @@
 {
     IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-    IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
-    IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if (IEM_IS_MODRM_MEM_MODE(bRm))
@@ -1371 +1372 @@
             IEM_MC_FETCH_GREG_U64(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
+            IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
             IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
             IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS,
@@ -1384 +1388 @@
             IEM_MC_FETCH_GREG_U32(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
+            IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
             IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
             IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS,
@@ -1391 +1398 @@
     }
     Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_RAISE_INVALID_OPCODE_RET();
 }
@@ -1401 +1409 @@
 {
     IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if (IEM_IS_MODRM_MEM_MODE(bRm))
@@ -1414 +1421 @@
             IEM_MC_FETCH_GREG_U64(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
             IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
@@ -1426 +1434 @@
             IEM_MC_FETCH_GREG_U32(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
             IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
@@ -1432 +1441 @@
     }
     Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_RAISE_INVALID_OPCODE_RET();
 }
@@ -1565 +1575 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc, 1);
@@ -1804 +1814 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint32_t *,          puDst, 0);
         IEM_MC_ARG(uint8_t,             uSrc,  1);
@@ -1920 +1930 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
                 IEM_MC_ARG(uint16_t,            uSrc,  1);
@@ -1938 +1948 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
                 IEM_MC_ARG(uint32_t,            uSrc,  1);
@@ -1951 +1962 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
                 IEM_MC_ARG(uint64_t,            uSrc,  1);
@@ -2067 +2079 @@
             if (IEM_IS_MODRM_REG_MODE(bRm)) \
             { \
+                IEM_MC_BEGIN(3, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_BEGIN(3, 0); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1); \
@@ -2102 +2114 @@
             if (IEM_IS_MODRM_REG_MODE(bRm)) \
             { \
+                IEM_MC_BEGIN(3, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_BEGIN(3, 0); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1); \

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h

@@ -52 +52 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc,               1);
@@ -111 +111 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc,               1);
@@ -171 +171 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -243 +243 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc,               1);
@@ -323 +323 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -388 +388 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -481 +481 @@
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t,            uSrc, 1);
@@ -553 +553 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint8_t,   uValue);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -597 +597 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint16_t,  uValue);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -648 +648 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t,  uSrc);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -695 +695 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t,  uSrc);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -739 +739 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint32_t,  uSrc);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -792 +792 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint8_t,   uSrc);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -835 +835 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 3);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-        IEM_MC_BEGIN(0, 3);
         IEM_MC_LOCAL(uint32_t,  uSrc);
         IEM_MC_LOCAL(uint8_t,   uSrcSel);
@@ -899 +899 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t,  uSrc);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -946 +946 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t,  uSrc);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -1055 +1055 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc,               1);
@@ -1147 +1147 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(4, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-            IEM_MC_BEGIN(4, 1);
             IEM_MC_ARG(PRTUINT128U,                puDst,             0);
             IEM_MC_ARG(uint32_t *,                 pEFlags,             1);
@@ -1211 +1211 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(4, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-            IEM_MC_BEGIN(4, 1);
             IEM_MC_ARG(PRTUINT128U,                puDst,             0);
             IEM_MC_ARG(uint32_t *,                 pEFlags,             1);
@@ -1283 +1283 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(4, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-            IEM_MC_BEGIN(4, 1);
             IEM_MC_ARG(uint32_t *,                 pu32Ecx,             0);
             IEM_MC_ARG(uint32_t *,                 pEFlags,             1);
@@ -1348 +1348 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(4, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-            IEM_MC_BEGIN(4, 1);
             IEM_MC_ARG(uint32_t *,                 pu32Ecx,             0);
             IEM_MC_ARG(uint32_t *,                 pEFlags,             1);
@@ -1420 +1420 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_ARG(PRTUINT128U,                puDst,             0);
         IEM_MC_ARG(uint32_t *,                 pEFlags,             1);
@@ -1485 +1485 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_ARG(uint32_t *,                 pu32Ecx,             0);
         IEM_MC_ARG(uint32_t *,                 pEFlags,             1);
@@ -1582 +1582 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc,               1);

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -50 +50 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -112 +112 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -172 +172 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -235 +235 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -295 +295 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -357 +357 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
         IEM_MC_ARG(PCRTUINT128U,         pSrc, 1);
@@ -412 +412 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
         IEM_MC_ARG(PCRTUINT128U,         pSrc, 1);
@@ -470 +470 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
         IEM_MC_ARG(PCRTUINT128U,         pSrc, 1);
@@ -523 +523 @@
          * MMX, MMX.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
         IEM_MC_ARG(uint64_t const *,        puSrc, 1);
@@ -585 +585 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,            puSrc, 1);
@@ -645 +645 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,            puSrc, 1);
@@ -705 +705 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
         IEM_MC_ARG(uint64_t const *,        puSrc, 1);
@@ -767 +767 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,            puSrc, 1);
@@ -827 +827 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
@@ -891 +891 @@
          * XMM128, XMM32.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
@@ -955 +955 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
@@ -1019 +1019 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
@@ -1083 +1083 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,            puSrc, 1);
@@ -1143 +1143 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
@@ -1250 +1250 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
-        IEM_MC_BEGIN(1, 0);
         IEM_MC_ARG(uint16_t, u16Sel, 0);
         IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -1281 +1281 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(1, 0);
         IEM_MC_ARG(uint16_t, u16Sel, 0);
         IEM_MC_FETCH_GREG_U16(u16Sel, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -1311 +1311 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint16_t,    u16Sel,            0);
         IEM_MC_ARG_CONST(bool,  fWriteArg, fWrite, 1);
@@ -1526 +1526 @@
          *        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX and
          *        IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES here. */
+/** @todo testcase: test prefixes and exceptions. currently not checking for the
+ *        OPSIZE one ... */
         IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
         IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_xgetbv);
@@ -1542 +1544 @@
          *        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX and
          *        IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES here. */
+/** @todo testcase: test prefixes and exceptions. currently not checking for the
+ *        OPSIZE one ... */
         IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
         IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_xsetbv);
@@ -1583 +1587 @@
 {
     IEMOP_MNEMONIC(vmmcall, "vmmcall");
+    /** @todo r=bird: Table A-8 on page 524 in vol 3 has VMGEXIT for this
+     *        opcode sequence when F3 or F2 is used as prefix. So, the assumtion
+     *        here cannot be right... */
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */
 
@@ -1702 +1709 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint16_t, u16Tmp,                         0);
         IEM_MC_ARG_CONST(RTGCPTR,  GCPtrEffDst, NIL_RTGCPTR, 1);
@@ -1729 +1736 @@
     IEMOP_MNEMONIC(invlpg, "invlpg");
     IEMOP_HLP_MIN_486();
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_BEGIN(1, 1);
     IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 0);
     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_VMEXIT, iemCImpl_invlpg, GCPtrEffDst);
     IEM_MC_END();
@@ -1851 +1858 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
         switch (pVCpu->iem.s.enmEffOpSize)
         {
@@ -1857 +1863 @@
             {
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
                 IEM_MC_ARG(uint16_t *,  pu16Dst,           0);
                 IEM_MC_ARG(uint16_t,    u16Sel,            1);
@@ -1872 +1879 @@
             {
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
                 IEM_MC_ARG(uint64_t *,  pu64Dst,           0);
                 IEM_MC_ARG(uint16_t,    u16Sel,            1);
@@ -2052 +2060 @@
 {
     IEMOP_MNEMONIC(femms, "femms");
+
+    IEM_MC_BEGIN(0,0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-    IEM_MC_BEGIN(0,0);
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_MAYBE_RAISE_FPU_XCPT();
@@ -2102 +2110 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -2153 +2161 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -2203 +2211 @@
          * XMM32, XMM32.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
 
@@ -2256 +2264 @@
          * XMM64, XMM64.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -2309 +2317 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -2359 +2367 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -2409 +2417 @@
          * XMM32, XMM32.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
 
@@ -2462 +2470 @@
          * XMM64, XMM64.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -2514 +2522 @@
         IEMOP_MNEMONIC2(RM_REG, MOVHLPS, movhlps, Vq_WO, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -2626 +2634 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
 
@@ -2686 +2694 @@
          * XMM128, XMM64.
          */
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
-        IEM_MC_BEGIN(1, 0);
         IEM_MC_ARG(uint64_t,                    uSrc, 0);
 
@@ -2933 +2941 @@
         IEMOP_MNEMONIC2(RM_REG, MOVLHPS, movlhps, VqHi_WO, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -3044 +3052 @@
          * XMM128, XMM128.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
 
@@ -3255 +3263 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_ADVANCE_RIP_AND_FINISH();
         IEM_MC_END();
@@ -3415 +3423 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -3464 +3472 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -3516 +3524 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -3565 +3573 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -3610 +3618 @@
          * XMM, MMX
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(X86XMMREG,             Dst);
@@ -3681 +3688 @@
          * XMM, MMX
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(X86XMMREG,             Dst);
@@ -4082 +4088 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4150 +4155 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4470 +4474 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4539 +4542 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4860 +4862 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -4929 +4931 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -5002 +5004 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -5071 +5073 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -5233 +5235 @@
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(0, 1); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_LOCAL(uint16_t, u16Tmp); \
                 a_Cnd { \
@@ -5244 +5247 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(0, 1); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_LOCAL(uint32_t, u32Tmp); \
                 a_Cnd { \
@@ -5257 +5261 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(0, 1); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_LOCAL(uint64_t, u64Tmp); \
                 a_Cnd { \
@@ -5278 +5283 @@
                 IEM_MC_LOCAL(uint16_t, u16Tmp); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
                 a_Cnd { \
@@ -5291 +5297 @@
                 IEM_MC_LOCAL(uint32_t, u32Tmp); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
                 a_Cnd { \
@@ -5306 +5313 @@
                 IEM_MC_LOCAL(uint64_t, u64Tmp); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
                 a_Cnd { \
@@ -5459 +5467 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(2, 1);
         IEM_MC_LOCAL(uint8_t,           u8Dst);
         IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst,  u8Dst, 0);
@@ -5488 +5496 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 1);
         IEM_MC_LOCAL(uint8_t,           u8Dst);
         IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst,  u8Dst, 0);
@@ -6191 +6199 @@
         {
             /* MMX, greg64 */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -6243 +6251 @@
         {
             /* MMX, greg32 */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
 
@@ -6298 +6306 @@
         {
             /* XMM, greg64 */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -6348 +6356 @@
         {
             /* XMM, greg32 */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
 
@@ -6403 +6411 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -6458 +6466 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -6509 +6517 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -6551 +6559 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
-
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG(uint64_t const *,    pSrc, 1);
@@ -6618 +6625 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,         puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,        puSrc, 1);
@@ -6704 +6710 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
         IEM_MC_ARG_CONST(uint8_t,       bShiftArg, /*=*/ bImm, 1);
@@ -6751 +6756 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,         pDst, 0);
         IEM_MC_ARG_CONST(uint8_t,       bShiftArg, /*=*/ bImm, 1);
@@ -7066 +7070 @@
 {
     IEMOP_MNEMONIC(emms, "emms");
+    IEM_MC_BEGIN(0,0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-    IEM_MC_BEGIN(0,0);
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
     IEM_MC_MAYBE_RAISE_FPU_XCPT();
@@ -7096 +7099 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
         if (enmEffOpSize == IEMMODE_64BIT)
         {
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint64_t *, pu64Dst, 0);
             IEM_MC_ARG(uint64_t,   u64Enc,  1);
@@ -7110 +7113 @@
         {
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint64_t *, pu64Dst, 0);
             IEM_MC_ARG(uint32_t,   u32Enc,  1);
@@ -7177 +7181 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
         if (enmEffOpSize == IEMMODE_64BIT)
         {
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint64_t, u64Val, 0);
             IEM_MC_ARG(uint64_t, u64Enc, 1);
@@ -7191 +7195 @@
         {
             IEM_MC_BEGIN(2, 0);
+            IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint32_t, u32Val, 0);
             IEM_MC_ARG(uint32_t, u32Enc, 1);
@@ -7315 +7320 @@
         {
             /* greg64, MMX */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -7367 +7372 @@
         {
             /* greg32, MMX */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
 
@@ -7423 +7428 @@
         {
             /* greg64, XMM */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -7473 +7478 @@
         {
             /* greg32, XMM */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
 
@@ -7525 +7530 @@
          * XMM128, XMM64.
          */
+        IEM_MC_BEGIN(0, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -7575 +7580 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t, u64Tmp);
         IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
@@ -7621 +7626 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -7662 +7667 @@
          * XMM, XMM.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
@@ -7706 +7711 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -7719 +7723 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -7741 +7744 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7754 +7756 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7776 +7777 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -7789 +7789 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -7811 +7810 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7824 +7822 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7846 +7843 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -7859 +7855 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -7881 +7876 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7894 +7888 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7916 +7909 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -7929 +7921 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -7951 +7942 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7964 +7954 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7986 +7975 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -7999 +7987 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -8021 +8008 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8034 +8020 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8056 +8041 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -8069 +8053 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -8091 +8074 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8104 +8086 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8126 +8107 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -8139 +8119 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -8161 +8140 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8174 +8152 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8196 +8173 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
@@ -8209 +8185 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
@@ -8231 +8206 @@
     {
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8244 +8218 @@
     {
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8270 +8243 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8311 +8284 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8352 +8325 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8393 +8366 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8434 +8407 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8475 +8448 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8516 +8489 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8557 +8530 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8598 +8571 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8639 +8612 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8680 +8653 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8721 +8694 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8762 +8735 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8803 +8776 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8844 +8817 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1);
@@ -8885 +8858 @@
     {
         /* register target */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
             IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0);
@@ -8918 +8891 @@
 FNIEMOP_DEF_1(iemOpCommonPushSReg, uint8_t, iReg)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     Assert(iReg < X86_SREG_FS || !IEM_IS_64BIT_CODE(pVCpu));
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
@@ -8926 +8898 @@
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Value);
             IEM_MC_FETCH_SREG_U16(u16Value, iReg);
@@ -8935 +8908 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
             IEM_MC_FETCH_SREG_ZX_U32(u32Value, iReg);
@@ -8944 +8918 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_FETCH_SREG_ZX_U64(u64Value, iReg);
@@ -8997 +8972 @@
     { \
         /* register destination. */ \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         switch (pVCpu->iem.s.enmEffOpSize) \
         { \
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
                 IEM_MC_ARG(uint16_t,        u16Src,                 1); \
@@ -9018 +8993 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
                 IEM_MC_ARG(uint32_t,        u32Src,                 1); \
@@ -9035 +9011 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
                 IEM_MC_ARG(uint64_t,        u64Src,                 1); \
@@ -9267 +9244 @@
     {
         uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
         switch (pVCpu->iem.s.enmEffOpSize)
@@ -9273 +9249 @@
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG(uint16_t,        u16Src,                 1);
@@ -9289 +9266 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG(uint32_t,        u32Src,                 1);
@@ -9306 +9284 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG(uint64_t,        u64Src,                 1);
@@ -9412 +9391 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG(uint16_t,        u16Src,                 1);
@@ -9435 +9413 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG(uint32_t,        u32Src,                 1);
@@ -9453 +9432 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG(uint64_t,        u64Src,                 1);
@@ -9849 +9829 @@
     RT_NOREF_PV(bRm);
     IEMOP_MNEMONIC(lfence, "lfence");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-    if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
-        IEMOP_RAISE_INVALID_OPCODE_RET();
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 #ifdef RT_ARCH_ARM64
     IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_lfence);
@@ -9872 +9849 @@
     RT_NOREF_PV(bRm);
     IEMOP_MNEMONIC(mfence, "mfence");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-    if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
-        IEMOP_RAISE_INVALID_OPCODE_RET();
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 #ifdef RT_ARCH_ARM64
     IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_mfence);
@@ -9895 +9869 @@
     RT_NOREF_PV(bRm);
     IEMOP_MNEMONIC(sfence, "sfence");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-    if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
-        IEMOP_RAISE_INVALID_OPCODE_RET();
-
     IEM_MC_BEGIN(0, 0);
+    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 #ifdef RT_ARCH_ARM64
     IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_sfence);
@@ -9917 +9888 @@
 {
     IEMOP_MNEMONIC(rdfsbase, "rdfsbase Ry");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint64_t, u64Dst, 0);
@@ -9931 +9902 @@
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint32_t, u32Dst, 0);
@@ -9945 +9917 @@
 {
     IEMOP_MNEMONIC(rdgsbase, "rdgsbase Ry");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint64_t, u64Dst, 0);
@@ -9959 +9931 @@
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint32_t, u32Dst, 0);
@@ -9973 +9946 @@
 {
     IEMOP_MNEMONIC(wrfsbase, "wrfsbase Ry");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint64_t, u64Dst, 0);
@@ -9988 +9961 @@
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint32_t, u32Dst, 0);
@@ -10002 +9976 @@
 {
     IEMOP_MNEMONIC(wrgsbase, "wrgsbase Ry");
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint64_t, u64Dst, 0);
@@ -10017 +9991 @@
     {
         IEM_MC_BEGIN(1, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
         IEM_MC_ARG(uint32_t, u32Dst, 0);
@@ -10096 +10071 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(4, 0);
         IEMOP_HLP_DONE_DECODING();
-        IEM_MC_BEGIN(4, 0);
         IEM_MC_ARG(uint8_t *,       pu8Dst,                 0);
         IEM_MC_ARG(uint8_t *,       pu8Al,                  1);
@@ -10154 +10129 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG(uint16_t *,      pu16Ax,                 1);
@@ -10179 +10154 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pu32Eax,                1);
@@ -10205 +10181 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(4, 0);
+                IEMOP_HLP_DONE_DECODING();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG(uint64_t *,      pu64Rax,                1);
@@ -10473 +10450 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_FETCH_GREG_U8_ZX_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -10487 +10464 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_FETCH_GREG_U8_ZX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -10496 +10474 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_FETCH_GREG_U8_ZX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -10571 +10550 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
             IEM_MC_FETCH_GREG_U16_ZX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -10584 +10563 @@
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_FETCH_GREG_U16_ZX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -10674 +10654 @@
         /* register destination. */ \
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         \
         switch (pVCpu->iem.s.enmEffOpSize) \
@@ -10680 +10659 @@
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
                 IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ bImm & 0x0f,  1); \
@@ -10694 +10674 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
                 IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ bImm & 0x1f,  1); \
@@ -10709 +10690 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(3, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
                 IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ bImm & 0x3f,  1); \
@@ -10967 +10949 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
                 IEM_MC_ARG(uint16_t,   u16Src,  1);
@@ -10987 +10969 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
                 IEM_MC_ARG(uint32_t,   u32Src,  1);
@@ -11004 +10987 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
                 IEM_MC_ARG(uint64_t,   u64Src,  1);
@@ -11178 +11162 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_FETCH_GREG_U8_SX_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -11192 +11176 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_FETCH_GREG_U8_SX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -11201 +11186 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(0, 1);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_FETCH_GREG_U8_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -11276 +11262 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
             IEM_MC_FETCH_GREG_U16_SX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -11289 +11275 @@
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_FETCH_GREG_U16_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm));
@@ -11341 +11328 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0);
         IEM_MC_ARG(uint8_t *,  pu8Reg,  1);
@@ -11369 +11355 @@
 
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
         IEM_MC_FETCH_GREG_U8(u8RegCopy, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -11399 +11386 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *, pu16Dst,  0);
                 IEM_MC_ARG(uint16_t *, pu16Reg,  1);
@@ -11420 +11406 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *, pu32Dst,  0);
                 IEM_MC_ARG(uint32_t *, pu32Reg,  1);
@@ -11437 +11424 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(3, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *, pu64Dst,  0);
                 IEM_MC_ARG(uint64_t *, pu64Reg,  1);
@@ -11469 +11457 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
                 IEM_MC_FETCH_GREG_U16(u16RegCopy, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -11494 +11483 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
                 IEM_MC_FETCH_GREG_U32(u32RegCopy, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -11519 +11509 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
                 IEM_MC_FETCH_GREG_U64(u64RegCopy, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -11553 +11544 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11624 +11615 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11695 +11686 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11766 +11757 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(4, 2);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11843 +11834 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
-                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE(pVCpu, fSse2);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 
                 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -11858 +11848 @@
 
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
-                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE(pVCpu, fSse2);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 
                 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm));
@@ -11895 +11884 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(uint64_t *,           pu64Dst,               0);
         IEM_MC_ARG(uint16_t,             u16Src,                1);
@@ -11949 +11938 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,          puDst,                 0);
         IEM_MC_ARG(uint16_t,             u16Src,                1);
@@ -12003 +11992 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(uint16_t,              u16Dst);
         IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,  u16Dst,      0);
@@ -12035 +12024 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(uint16_t,              u16Dst);
         IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,  u16Dst,      0);
@@ -12070 +12059 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
         IEM_MC_ARG(PCRTUINT128U,         pSrc, 1);
@@ -12122 +12111 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(3, 0);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
         IEM_MC_ARG(PCRTUINT128U,         pSrc, 1);
@@ -12313 +12302 @@
     {
         /* register destination. */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1);
@@ -12332 +12321 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1);
@@ -12347 +12337 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1);
@@ -12455 +12446 @@
     {
         /* register destination. */
-        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         switch (pVCpu->iem.s.enmEffOpSize)
         {
             case IEMMODE_16BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1);
@@ -12474 +12465 @@
             case IEMMODE_32BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1);
@@ -12489 +12481 @@
             case IEMMODE_64BIT:
                 IEM_MC_BEGIN(2, 0);
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1);
@@ -12562 +12555 @@
 FNIEMOP_DEF_1(iemOpCommonBswapGReg, uint8_t, iReg)
 {
-    IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     switch (pVCpu->iem.s.enmEffOpSize)
     {
         case IEMMODE_16BIT:
             IEM_MC_BEGIN(1, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ARG(uint32_t *,  pu32Dst, 0);
             IEM_MC_REF_GREG_U32(pu32Dst, iReg);     /* Don't clear the high dword! */
@@ -12576 +12569 @@
         case IEMMODE_32BIT:
             IEM_MC_BEGIN(1, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ARG(uint32_t *,  pu32Dst, 0);
             IEM_MC_REF_GREG_U32(pu32Dst, iReg);
@@ -12586 +12580 @@
         case IEMMODE_64BIT:
             IEM_MC_BEGIN(1, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ARG(uint64_t *,  pu64Dst, 0);
             IEM_MC_REF_GREG_U64(pu64Dst, iReg);
@@ -12809 +12804 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 2);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -12863 +12858 @@
          */
         IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZx_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -12915 +12910 @@
          */
         IEMOP_MNEMONIC2(RM_REG, MOVDQ2Q, movdq2q, Pq_WO, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
 
@@ -12954 +12949 @@
         /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
         IEMOP_MNEMONIC2(RM_REG, PMOVMSKB, pmovmskb, Gd, Nq, DISOPTYPE_X86_MMX | DISOPTYPE_HARMLESS, 0);
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
         IEM_MC_ARG(uint64_t const *,        puSrc, 1);
@@ -12983 +12978 @@
         /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
         IEMOP_MNEMONIC2(RM_REG, PMOVMSKB, pmovmskb, Gd, Ux, DISOPTYPE_X86_SSE | DISOPTYPE_HARMLESS, 0);
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
         IEM_MC_ARG(PCRTUINT128U,            puSrc, 1);

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h

@@ -51 +51 @@
         if (pVCpu->iem.s.uVexLength)
         {
+            IEM_MC_BEGIN(4, 3);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(4, 3);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -71 +71 @@
         else
         {
+            IEM_MC_BEGIN(4, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(4, 0);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
             IEM_MC_ARG(PRTUINT128U,          puDst,  1);
@@ -165 +165 @@
         if (pVCpu->iem.s.uVexLength)
         {
+            IEM_MC_BEGIN(3, 3);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(3, 3);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -184 +184 @@
         else
         {
+            IEM_MC_BEGIN(3, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(3, 0);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
             IEM_MC_ARG(PCRTUINT128U,         puSrc1, 1);
@@ -307 +307 @@
         if (pVCpu->iem.s.uVexLength)
         {
+            IEM_MC_BEGIN(2, 2);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(2, 2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -323 +323 @@
         else
         {
+            IEM_MC_BEGIN(2, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(2, 0);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
             IEM_MC_ARG(PCRTUINT128U,         puSrc,  1);
@@ -432 +432 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
@@ -507 +507 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
@@ -583 +583 @@
          */
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
@@ -646 +646 @@
          */
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -709 +709 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
@@ -784 +784 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
@@ -859 +859 @@
          */
         IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -923 +923 @@
          */
         IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -986 +986 @@
          */
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
-
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -1111 +1110 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         if (pVCpu->iem.s.uVexLength == 0)
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
 
@@ -1133 +1132 @@
         {
             IEM_MC_BEGIN(3, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
             IEM_MC_ARG_CONST(uint8_t,   iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
@@ -1215 +1215 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         if (pVCpu->iem.s.uVexLength == 0)
         {
             IEM_MC_BEGIN(1, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_ARG(uint64_t,                    uSrc, 0);
 
@@ -1235 +1235 @@
         {
             IEM_MC_BEGIN(3, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
             IEM_MC_ARG_CONST(uint8_t,   iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
@@ -1451 +1452 @@
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -1563 +1564 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         if (pVCpu->iem.s.uVexLength == 0)
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(RTUINT128U,                  uSrc);
 
@@ -1585 +1586 @@
         {
             IEM_MC_BEGIN(3, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
             IEM_MC_ARG_CONST(uint8_t,   iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
@@ -1783 +1785 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(1, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -1860 +1862 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(1, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -1956 +1958 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(1, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -2032 +2034 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(1, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(1, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -2286 +2288 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2357 +2359 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2431 +2433 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2502 +2504 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(4, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(4, 1);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2612 +2614 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
+            IEM_MC_BEGIN(2, 1);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(2, 1);
             IEM_MC_LOCAL(uint8_t,           u8Dst);
             IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst,  u8Dst, 0);
@@ -2628 +2630 @@
         else
         {
+            IEM_MC_BEGIN(2, 2);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(2, 2);
             IEM_MC_LOCAL(uint8_t,               u8Dst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -2663 +2665 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
+            IEM_MC_BEGIN(2, 1);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(2, 1);
             IEM_MC_LOCAL(uint8_t,           u8Dst);
             IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst,  u8Dst, 0);
@@ -2679 +2681 @@
         else
         {
+            IEM_MC_BEGIN(2, 2);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(2, 2);
             IEM_MC_LOCAL(uint8_t,               u8Dst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -3021 +3023 @@
 //         * Register, register.
 //         */
+//        IEM_MC_BEGIN(2, 0);
 //        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-//        IEM_MC_BEGIN(2, 0);
 //        IEM_MC_ARG(PRTUINT128U,          pDst, 0);
 //        IEM_MC_ARG(PCRTUINT128U,         pSrc, 1);
@@ -3171 +3173 @@
         {
             /* XMM, greg64 */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -3221 +3223 @@
         {
             /* XMM, greg32 */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
 
@@ -3280 +3282 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -3355 +3357 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -3433 +3435 @@
         if (pVCpu->iem.s.uVexLength)
         {
+            IEM_MC_BEGIN(3, 2);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
-            IEM_MC_BEGIN(3, 2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -3450 +3452 @@
         else
         {
+            IEM_MC_BEGIN(3, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-            IEM_MC_BEGIN(3, 0);
             IEM_MC_ARG(PRTUINT128U,             puDst,                 0);
             IEM_MC_ARG(PCRTUINT128U,            puSrc,                 1);
@@ -3863 +3865 @@
         {
             /* greg64, XMM */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
 
@@ -3913 +3915 @@
         {
             /* greg32, XMM */
+            IEM_MC_BEGIN(0, 1);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-            IEM_MC_BEGIN(0, 1);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
 
@@ -3966 +3968 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -4023 +4025 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -4099 +4101 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -4400 +4402 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
-        IEM_MC_BEGIN(4, 0);
         IEM_MC_ARG(PRTUINT128U,          puDst,                 0);
         IEM_MC_ARG(PCRTUINT128U,         puSrc,                 1);
@@ -4465 +4467 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(3, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
-        IEM_MC_BEGIN(3, 1);
         IEM_MC_LOCAL(uint16_t,              u16Dst);
         IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,  u16Dst,      0);
@@ -4500 +4502 @@
         { \
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
+            IEM_MC_BEGIN(4, 3); \
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
-            IEM_MC_BEGIN(4, 3); \
             IEM_MC_LOCAL(RTUINT256U,            uDst); \
             IEM_MC_LOCAL(RTUINT256U,            uSrc1); \
@@ -4522 +4524 @@
         { \
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
+            IEM_MC_BEGIN(4, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
-            IEM_MC_BEGIN(4, 0); \
             IEM_MC_ARG(PRTUINT128U,          puDst,                 0); \
             IEM_MC_ARG(PCRTUINT128U,         puSrc1,                1); \
@@ -4705 +4707 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
-        IEM_MC_BEGIN(0, 0);
 
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -4755 +4757 @@
         if (pVCpu->iem.s.uVexLength)
         {
+            IEM_MC_BEGIN(2, 1);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
-            IEM_MC_BEGIN(2, 1);
             IEM_MC_ARG(uint64_t *,              puDst, 0);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -4771 +4773 @@
         else
         {
+            IEM_MC_BEGIN(2, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-            IEM_MC_BEGIN(2, 0);
             IEM_MC_ARG(uint64_t *,              puDst, 0);
             IEM_MC_ARG(PCRTUINT128U,            puSrc, 1);

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h

@@ -221 +221 @@
         if (pVCpu->iem.s.uVexLength)
         {
+            IEM_MC_BEGIN(3, 2);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(3, 2);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
             IEM_MC_LOCAL(RTUINT256U,            uSrc2);
@@ -240 +240 @@
         else
         {
+            IEM_MC_BEGIN(3, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(3, 0);
             IEM_MC_ARG(PCRTUINT128U,            puSrc1,  0);
             IEM_MC_ARG(PCRTUINT128U,            puSrc2,  1);
@@ -323 +323 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
         if (pVCpu->iem.s.uVexLength)
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint32_t,              uSrc);
 
@@ -341 +341 @@
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint32_t,              uSrc);
 
@@ -408 +409 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
         if (pVCpu->iem.s.uVexLength)
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint64_t,              uSrc);
 
@@ -426 +427 @@
         {
             IEM_MC_BEGIN(0, 1);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint64_t,              uSrc);
 
@@ -549 +551 @@
         if (pVCpu->iem.s.uVexLength) \
         { \
+            IEM_MC_BEGIN(2, 1); \
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
-            IEM_MC_BEGIN(2, 1); \
             IEM_MC_LOCAL(RTUINT256U,            uDst); \
             IEM_MC_ARG_LOCAL_REF(PRTUINT256U,   puDst, uDst, 0); \
@@ -566 +568 @@
         else \
         { \
+            IEM_MC_BEGIN(2, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
-            IEM_MC_BEGIN(2, 0); \
             IEM_MC_ARG(PRTUINT128U,          puDst,  0); \
             IEM_MC_ARG(uint64_t,             uSrc,   1); \
@@ -966 +968 @@
          * Register, register.
          */
+        IEM_MC_BEGIN(2, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
-        IEM_MC_BEGIN(2, 0);
         IEM_MC_ARG(PRTUINT128U,          puDst,  0);
         IEM_MC_ARG(PCRTUINT128U,         puSrc,  1);
@@ -1641 +1643 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
             IEM_MC_BEGIN(4, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
             IEM_MC_ARG(uint64_t *,          pDst,    0);
             IEM_MC_ARG(uint64_t,            uSrc1,   1);
@@ -1661 +1663 @@
         {
             IEM_MC_BEGIN(4, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
             IEM_MC_ARG(uint32_t *,          pDst,    0);
             IEM_MC_ARG(uint32_t,            uSrc1,   1);
@@ -1741 +1744 @@
          * Register, register. \
          */ \
-        IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc,    1); \
@@ -1759 +1762 @@
         { \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc,    1); \
@@ -1891 +1895 @@
          * Register, register. \
          */ \
-        IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
             IEM_MC_BEGIN(4, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc1,   1); \
@@ -1912 +1916 @@
         { \
             IEM_MC_BEGIN(4, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc1,   1); \
@@ -1986 +1991 @@
          * Register, register. \
          */ \
-        IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc1,   1); \
@@ -2004 +2009 @@
         { \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc1,   1); \
@@ -2077 +2083 @@
          * Register, register. \
          */ \
-        IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc1,   1); \
@@ -2096 +2102 @@
         { \
             IEM_MC_BEGIN(3, 0); \
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc1,   1); \
@@ -2187 +2194 @@
          * Register, register.
          */
-        IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
             IEM_MC_BEGIN(4, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
             IEM_MC_ARG(uint64_t *,          pDst1,   0);
             IEM_MC_ARG(uint64_t *,          pDst2,   1);
@@ -2207 +2214 @@
         {
             IEM_MC_BEGIN(4, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
             IEM_MC_ARG(uint32_t *,          pDst1,   0);
             IEM_MC_ARG(uint32_t *,          pDst2,   1);

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap3.cpp.h

@@ -54 +54 @@
         {
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(4, 3);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(4, 3);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -75 +75 @@
         {
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+            IEM_MC_BEGIN(4, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(4, 0);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
             IEM_MC_ARG(PCRTUINT128U,         puSrc1, 1);
@@ -170 +170 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
         if (pVCpu->iem.s.uVexLength)
         {
             IEM_MC_BEGIN(4, 3);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -193 +193 @@
         {
             IEM_MC_BEGIN(4, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
             IEM_MC_ARG(PCRTUINT128U,         puSrc1, 1);
@@ -293 +294 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 3);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
-        IEM_MC_BEGIN(4, 3);
         IEM_MC_LOCAL(RTUINT256U,            uDst);
         IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -424 +425 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
-
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
 
@@ -517 +517 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(0, 1);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
-
-        IEM_MC_BEGIN(0, 1);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
 
@@ -588 +587 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
-        IEM_MC_BEGIN(4, 0);
         IEM_MC_ARG(PRTUINT128U,          puDst,  0);
         IEM_MC_ARG(PCRTUINT128U,         puSrc1, 1);
@@ -652 +651 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
+        IEM_MC_BEGIN(4, 3);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
-        IEM_MC_BEGIN(4, 3);
         IEM_MC_LOCAL(RTUINT256U,            uDst);
         IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -727 +726 @@
          */
         uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
-        IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
         if (pVCpu->iem.s.uVexLength)
         {
             IEM_MC_BEGIN(4, 4);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -752 +751 @@
         {
             IEM_MC_BEGIN(4, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
             IEM_MC_ARG(PCRTUINT128U,         puSrc1, 1);
@@ -869 +869 @@
          * Register, register.
          */
+        uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
         if (pVCpu->iem.s.uVexLength)
         {
-            uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
-
+            IEM_MC_BEGIN(4, 4);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
-            IEM_MC_BEGIN(4, 4);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -895 +894 @@
         else
         {
-            uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
-
+            IEM_MC_BEGIN(4, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
-            IEM_MC_BEGIN(4, 0);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
             IEM_MC_ARG(PCRTUINT128U,         puSrc1, 1);
@@ -1123 +1120 @@
          */
         uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
-        IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
             IEM_MC_BEGIN(3, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
             IEM_MC_ARG(uint64_t *,          pDst,    0);
             IEM_MC_ARG(uint64_t,            uSrc1,   1);
@@ -1139 +1136 @@
         {
             IEM_MC_BEGIN(3, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
             IEM_MC_ARG(uint32_t *,          pDst,    0);
             IEM_MC_ARG(uint32_t,            uSrc1,   1);

trunk/src/VBox/VMM/include/IEMOpHlp.h

@@ -327 +327 @@
  *
  *  @note Update IEM_VMX_IN_VMX_OPERATION if changes are made here.
+ *
+ * @todo r=bird: This is absolutely *INCORRECT* since IEM_VMX_IS_ROOT_MODE
+ *       is a complicated runtime state (calls CPUMIsGuestInVmxRootMode), and
+ *       not something we can decide while decoding.  Convert to an IEM_MC!
  */
 # define IEMOP_HLP_IN_VMX_OPERATION(a_szInstr, a_InsDiagPrefix) \