Changeset 100723 in vbox

Timestamp:

Jul 28, 2023 7:23:31 AM (22 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

158582

Message:

VMM/ARM: Add debug system registers in the vCPU state, bugref:10387, bugref:10390

Location:

trunk

Files:

• include/VBox/vmm/cpumctx-armv8.h (modified) (3 diffs)
• src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp (modified) (4 diffs)

trunk/include/VBox/vmm/cpumctx-armv8.h

@@ -119 +119 @@
 #ifndef VBOX_FOR_DTRACE_LIB
 AssertCompileSize(CPUMCTXSYSREG, 8);
+
+
+/**
+ * A debug register state (control and value), these are held together
+ * because they will be accessed together very often and thus minimizes
+ * stress on the cache.
+ */
+typedef struct CPUMCTXSYSREGDBG
+{
+    /** The control register. */
+    CPUMCTXSYSREG   Ctrl;
+    /** The value register. */
+    CPUMCTXSYSREG   Value;
+} CPUMCTXSYSREGDBG;
+/** Pointer to a debug register state. */
+typedef CPUMCTXSYSREGDBG *PCPUMCTXSYSREGDBG;
+/** Pointer to a const debug register state. */
+typedef const CPUMCTXSYSREGDBG *PCCPUMCTXSYSREGDBG;
 #endif
 
@@ -128 +146 @@
 {
     /** The general purpose register array view. */
-    CPUMCTXGREG     aGRegs[31];
+    CPUMCTXGREG         aGRegs[31];
     /** The NEON SIMD & FP register array view. */
-    CPUMCTXVREG     aVRegs[32];
+    CPUMCTXVREG         aVRegs[32];
     /** The stack registers (EL0, EL1). */
-    CPUMCTXSYSREG   aSpReg[2];
+    CPUMCTXSYSREG       aSpReg[2];
     /** The program counter. */
-    CPUMCTXSYSREG   Pc;
+    CPUMCTXSYSREG       Pc;
     /** The SPSR (Saved Program Status Register) (EL1 only). */
-    CPUMCTXSYSREG   Spsr;
+    CPUMCTXSYSREG       Spsr;
     /** The ELR (Exception Link Register) (EL1 only). */
-    CPUMCTXSYSREG   Elr;
+    CPUMCTXSYSREG       Elr;
     /** The SCTLR_EL1 register. */
-    CPUMCTXSYSREG   Sctlr;
+    CPUMCTXSYSREG       Sctlr;
     /** THe TCR_EL1 register. */
-    CPUMCTXSYSREG   Tcr;
+    CPUMCTXSYSREG       Tcr;
     /** The TTBR0_EL1 register. */
-    CPUMCTXSYSREG   Ttbr0;
+    CPUMCTXSYSREG       Ttbr0;
     /** The TTBR1_EL1 register. */
-    CPUMCTXSYSREG   Ttbr1;
+    CPUMCTXSYSREG       Ttbr1;
     /** The VBAR_EL1 register. */
-    CPUMCTXSYSREG   VBar;
+    CPUMCTXSYSREG       VBar;
+    /** Breakpoint registers, DBGB{C,V}<n>_EL1. */
+    CPUMCTXSYSREGDBG    aBp[16];
+    /** Watchpoint registers, DBGW{C,V}<n>_EL1. */
+    CPUMCTXSYSREGDBG    aWp[16];
 
     /** Floating point control register. */
-    uint64_t        fpcr;
+    uint64_t            fpcr;
     /** Floating point status register. */
-    uint64_t        fpsr;
+    uint64_t            fpsr;
     /** The internal PSTATE state (as given from SPSR_EL2). */
-    uint64_t        fPState;
-
-    uint32_t        fPadding0;
+    uint64_t            fPState;
+
+    uint32_t            fPadding0;
 
     /** OS lock status accessed through OSLAR_EL1 and OSLSR_EL1. */
-    bool            fOsLck;
-
-    uint8_t         afPadding1[7];
+    bool                fOsLck;
+
+    uint8_t             afPadding1[7];
 
     /** Externalized state tracker, CPUMCTX_EXTRN_XXX. */
-    uint64_t        fExtrn;
+    uint64_t            fExtrn;
 
     /** The CNTV_CTL_EL0 register, always synced during VM-exit. */
-    uint64_t        CntvCtlEl0;
+    uint64_t            CntvCtlEl0;
     /** The CNTV_CVAL_EL0 register, always synced during VM-exit. */
-    uint64_t        CntvCValEl0;
-
-    uint64_t        au64Padding2[6];
+    uint64_t            CntvCValEl0;
+
+    uint64_t            au64Padding2[6];
 } CPUMCTX;
 
@@ -233 +255 @@
 #define CPUMCTX_EXTRN_FPSR                      UINT64_C(0x0000000000008000)
 
+/** Debug system registers are kept externally. */
+#define CPUMCTX_EXTRN_SYSREG_DEBUG              UINT64_C(0x0000000000010000)
 /** Various system registers (rarely accessed) are kept externally. */
-#define CPUMCTX_EXTRN_SYSREG                    UINT64_C(0x0000000000010000)
+#define CPUMCTX_EXTRN_SYSREG_MISC               UINT64_C(0x0000000000020000)
 
 /** Mask of bits the keepers can use for state tracking. */

trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

@@ -174 +174 @@
 #undef CPUM_VREG_EMIT
 };
+/** Debug system registers. */
+static const struct
+{
+    hv_sys_reg_t        enmHvReg;
+    uint32_t            offCpumCtx;
+} s_aCpumDbgRegs[] =
+{
+#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
+    { HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
+    { HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
+    /* Breakpoint registers. */
+    CPUM_DBGREG_EMIT(B, 0),
+    CPUM_DBGREG_EMIT(B, 1),
+    CPUM_DBGREG_EMIT(B, 2),
+    CPUM_DBGREG_EMIT(B, 3),
+    CPUM_DBGREG_EMIT(B, 4),
+    CPUM_DBGREG_EMIT(B, 5),
+    CPUM_DBGREG_EMIT(B, 6),
+    CPUM_DBGREG_EMIT(B, 7),
+    CPUM_DBGREG_EMIT(B, 8),
+    CPUM_DBGREG_EMIT(B, 9),
+    CPUM_DBGREG_EMIT(B, 10),
+    CPUM_DBGREG_EMIT(B, 11),
+    CPUM_DBGREG_EMIT(B, 12),
+    CPUM_DBGREG_EMIT(B, 13),
+    CPUM_DBGREG_EMIT(B, 14),
+    CPUM_DBGREG_EMIT(B, 15),
+    /* Watchpoint registers. */
+    CPUM_DBGREG_EMIT(W, 0),
+    CPUM_DBGREG_EMIT(W, 1),
+    CPUM_DBGREG_EMIT(W, 2),
+    CPUM_DBGREG_EMIT(W, 3),
+    CPUM_DBGREG_EMIT(W, 4),
+    CPUM_DBGREG_EMIT(W, 5),
+    CPUM_DBGREG_EMIT(W, 6),
+    CPUM_DBGREG_EMIT(W, 7),
+    CPUM_DBGREG_EMIT(W, 8),
+    CPUM_DBGREG_EMIT(W, 9),
+    CPUM_DBGREG_EMIT(W, 10),
+    CPUM_DBGREG_EMIT(W, 11),
+    CPUM_DBGREG_EMIT(W, 12),
+    CPUM_DBGREG_EMIT(W, 13),
+    CPUM_DBGREG_EMIT(W, 14),
+    CPUM_DBGREG_EMIT(W, 15)
+#undef CPUM_DBGREG_EMIT
+};
 /** System registers. */
 static const struct
@@ -190 +236 @@
     { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr0.u64)        },
     { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr1.u64)        },
-    { HV_SYS_REG_VBAR_EL1,  CPUMCTX_EXTRN_SYSREG,           RT_UOFFSETOF(CPUMCTX, VBar.u64)         },
+    { HV_SYS_REG_VBAR_EL1,  CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, VBar.u64)         },
 };
 /** ID registers. */
@@ -512 +558 @@
 
     if (   hrc == HV_SUCCESS
-        && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG)))
+        && (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
+    {
+        /* Debug registers. */
+        for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
+        {
+            uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
+            hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
+        }
+    }
+
+    if (   hrc == HV_SUCCESS
+        && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC)))
     {
         /* System registers. */
@@ -581 +638 @@
 
     if (   hrc == HV_SUCCESS
-        &&     (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG))
-            !=                              (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG))
+        && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
+    {
+        /* Debug registers. */
+        for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
+        {
+            uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
+            hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
+        }
+    }
+
+    if (   hrc == HV_SUCCESS
+        &&     (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
+            !=                              (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
     {
         /* System registers. */