Changeset 100725 in vbox

Timestamp:

Jul 28, 2023 9:48:52 AM (16 months ago)

Author:

vboxsync

Message:

VMM/ARM: Add some more system registers to the vCPU state, bugref:10387, bugref:10390

Location:

trunk

Files:

• include/VBox/vmm/cpumctx-armv8.h (modified) (2 diffs)
• src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp (modified) (2 diffs)

trunk/include/VBox/vmm/cpumctx-armv8.h

@@ -195 +195 @@
     /** Watchpoint registers, DBGW{C,V}n_EL1. */
     CPUMCTXSYSREGDBG    aWp[16];
+    /** The MDSCR_EL1 register. */
+    CPUMCTXSYSREG       Mdscr;
     /** APDA key register state. */
     CPUMCTXSYSREGPAKEY  Apda;
@@ -205 +207 @@
     /** APIB key register state. */
     CPUMCTXSYSREGPAKEY  Apib;
+    /** The AFSR0_EL1 register. */
+    CPUMCTXSYSREG       Afsr0;
+    /** The AFSR1_EL1 register. */
+    CPUMCTXSYSREG       Afsr1;
+    /** The AMAIR_EL1 register. */
+    CPUMCTXSYSREG       Amair;
+    /** The CNTKCTL_EL1 register. */
+    CPUMCTXSYSREG       CntKCtl;
+    /** The CONTEXTIDR_EL1 register. */
+    CPUMCTXSYSREG       ContextIdr;
+    /** The CPACR_EL1 register. */
+    CPUMCTXSYSREG       Cpacr;
+    /** The CSSELR_EL1 register. */
+    CPUMCTXSYSREG       Csselr;
+    /** The ESR_EL1 register. */
+    CPUMCTXSYSREG       Esr;
+    /** The FAR_EL1 register. */
+    CPUMCTXSYSREG       Far;
+    /** The MAIR_EL1 register. */
+    CPUMCTXSYSREG       Mair;
+    /** The PAR_EL1 register. */
+    CPUMCTXSYSREG       Par;
+    /** The TPIDRRO_EL0 register. */
+    CPUMCTXSYSREG       TpIdrRoEl0;
+    /** The TPIDR_ELn registers. */
+    CPUMCTXSYSREG       aTpIdr[2];
+    /** TheMDCCINT_EL1 register. */
+    CPUMCTXSYSREG       MDccInt;   
 
     /** Floating point control register. */

trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

@@ -217 +217 @@
     CPUM_DBGREG_EMIT(W, 13),
     CPUM_DBGREG_EMIT(W, 14),
-    CPUM_DBGREG_EMIT(W, 15)
+    CPUM_DBGREG_EMIT(W, 15),
+    { HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
 #undef CPUM_DBGREG_EMIT
 };
@@ -246 +247 @@
 } s_aCpumSysRegs[] =
 {
-    { HV_SYS_REG_SP_EL0,    CPUMCTX_EXTRN_SP,               RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64)    },
-    { HV_SYS_REG_SP_EL1,    CPUMCTX_EXTRN_SP,               RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64)    },
-    { HV_SYS_REG_SPSR_EL1,  CPUMCTX_EXTRN_SPSR,             RT_UOFFSETOF(CPUMCTX, Spsr.u64)         },
-    { HV_SYS_REG_ELR_EL1,   CPUMCTX_EXTRN_ELR,              RT_UOFFSETOF(CPUMCTX, Elr.u64)          },
-    { HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Sctlr.u64)        },
-    { HV_SYS_REG_TCR_EL1,   CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Tcr.u64)          },
-    { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr0.u64)        },
-    { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr1.u64)        },
-    { HV_SYS_REG_VBAR_EL1,  CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, VBar.u64)         },
+    { HV_SYS_REG_SP_EL0,            CPUMCTX_EXTRN_SP,               RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64)    },
+    { HV_SYS_REG_SP_EL1,            CPUMCTX_EXTRN_SP,               RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64)    },
+    { HV_SYS_REG_SPSR_EL1,          CPUMCTX_EXTRN_SPSR,             RT_UOFFSETOF(CPUMCTX, Spsr.u64)         },
+    { HV_SYS_REG_ELR_EL1,           CPUMCTX_EXTRN_ELR,              RT_UOFFSETOF(CPUMCTX, Elr.u64)          },
+    { HV_SYS_REG_SCTLR_EL1,         CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Sctlr.u64)        },
+    { HV_SYS_REG_TCR_EL1,           CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Tcr.u64)          },
+    { HV_SYS_REG_TTBR0_EL1,         CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr0.u64)        },
+    { HV_SYS_REG_TTBR1_EL1,         CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr1.u64)        },
+    { HV_SYS_REG_VBAR_EL1,          CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, VBar.u64)         },
+    { HV_SYS_REG_AFSR0_EL1,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Afsr0.u64)        },
+    { HV_SYS_REG_AFSR1_EL1,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Afsr1.u64)        },
+    { HV_SYS_REG_AMAIR_EL1,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Amair.u64)        },
+    { HV_SYS_REG_CNTKCTL_EL1,       CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, CntKCtl.u64)      },
+    { HV_SYS_REG_CONTEXTIDR_EL1,    CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, ContextIdr.u64)   },
+    { HV_SYS_REG_CPACR_EL1,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Cpacr.u64)        },
+    { HV_SYS_REG_CSSELR_EL1,        CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Csselr.u64)       },
+    { HV_SYS_REG_ESR_EL1,           CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Esr.u64)          },
+    { HV_SYS_REG_FAR_EL1,           CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Far.u64)          },
+    { HV_SYS_REG_MAIR_EL1,          CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Mair.u64)         },
+    { HV_SYS_REG_PAR_EL1,           CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Par.u64)          },
+    { HV_SYS_REG_TPIDRRO_EL0,       CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64)   },
+    { HV_SYS_REG_TPIDR_EL0,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64)    },
+    { HV_SYS_REG_TPIDR_EL1,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64)    },
+    { HV_SYS_REG_MDCCINT_EL1,       CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, MDccInt.u64)      }
+
 };
 /** ID registers. */