- Timestamp:
- Aug 1, 2023 10:59:03 AM (17 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/GICAll.cpp
r100186 r100767 52 52 *********************************************************************************************************************************/ 53 53 54 #ifdef LOG_ENABLED 55 /** 56 * Returns a human readable string of the given exception class. 57 * 58 * @returns Pointer to the string matching the given EC. 59 * @param u32Ec The exception class to return the string for. 60 */ 61 static const char *gicIccRegisterStringify(uint32_t u32Reg) 62 { 63 switch (u32Reg) 64 { 65 #define GIC_ICC_REG_CASE(a_Reg) case ARMV8_AARCH64_SYSREG_ ## a_Reg: return #a_Reg 66 GIC_ICC_REG_CASE(ICC_PMR_EL1); 67 GIC_ICC_REG_CASE(ICC_IAR0_EL1); 68 GIC_ICC_REG_CASE(ICC_EOIR0_EL1); 69 GIC_ICC_REG_CASE(ICC_HPPIR0_EL1); 70 GIC_ICC_REG_CASE(ICC_BPR0_EL1); 71 GIC_ICC_REG_CASE(ICC_AP0R0_EL1); 72 GIC_ICC_REG_CASE(ICC_AP0R1_EL1); 73 GIC_ICC_REG_CASE(ICC_AP0R2_EL1); 74 GIC_ICC_REG_CASE(ICC_AP0R3_EL1); 75 GIC_ICC_REG_CASE(ICC_AP1R0_EL1); 76 GIC_ICC_REG_CASE(ICC_AP1R1_EL1); 77 GIC_ICC_REG_CASE(ICC_AP1R2_EL1); 78 GIC_ICC_REG_CASE(ICC_AP1R3_EL1); 79 GIC_ICC_REG_CASE(ICC_DIR_EL1); 80 GIC_ICC_REG_CASE(ICC_RPR_EL1); 81 GIC_ICC_REG_CASE(ICC_SGI1R_EL1); 82 GIC_ICC_REG_CASE(ICC_ASGI1R_EL1); 83 GIC_ICC_REG_CASE(ICC_SGI0R_EL1); 84 GIC_ICC_REG_CASE(ICC_IAR1_EL1); 85 GIC_ICC_REG_CASE(ICC_EOIR1_EL1); 86 GIC_ICC_REG_CASE(ICC_HPPIR1_EL1); 87 GIC_ICC_REG_CASE(ICC_BPR1_EL1); 88 GIC_ICC_REG_CASE(ICC_CTLR_EL1); 89 GIC_ICC_REG_CASE(ICC_SRE_EL1); 90 GIC_ICC_REG_CASE(ICC_IGRPEN0_EL1); 91 GIC_ICC_REG_CASE(ICC_IGRPEN1_EL1); 92 #undef GIC_ICC_REG_CASE 93 default: 94 break; 95 } 96 97 return "<UNKNOWN>"; 98 } 99 #endif 100 101 54 102 /** 55 103 * Sets the interrupt pending force-flag and pokes the EMT if required. … … 235 283 } 236 284 237 LogFlowFunc(("pThis=%p fIrq=%RTbool fFiq=%RTbool\n",238 pThis, *pfIrq, *pfFiq));285 LogFlowFunc(("pThis=%p bPriority=%u bmIntEnabled=%#x bmIntPending=%#x bmIntActive=%#x fIrq=%RTbool fFiq=%RTbool\n", 286 pThis, bPriority, bmIntEnabled, bmIntPending, bmIntActive, *pfIrq, *pfFiq)); 239 287 } 240 288 … … 984 1032 PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3); 985 1033 986 LogFlowFunc(("pVCpu=%p u32Reg=%#x pu64Value=%RX64\n", pVCpu, u32Reg, *pu64Value));1034 LogFlowFunc(("pVCpu=%p u32Reg=%#x{%s} pu64Value=%RX64\n", pVCpu, u32Reg, gicIccRegisterStringify(u32Reg), *pu64Value)); 987 1035 return VINF_SUCCESS; 988 1036 } … … 1003 1051 */ 1004 1052 VMCPU_ASSERT_EMT(pVCpu); 1005 LogFlowFunc(("pVCpu=%p u32Reg=%#x u64Value=%RX64\n", pVCpu, u32Reg, u64Value));1053 LogFlowFunc(("pVCpu=%p u32Reg=%#x{%s} u64Value=%RX64\n", pVCpu, u32Reg, gicIccRegisterStringify(u32Reg), u64Value)); 1006 1054 1007 1055 PGICCPU pThis = VMCPU_TO_GICCPU(pVCpu);
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