Changeset 100782 in vbox for trunk

Timestamp:

Aug 3, 2023 1:15:55 AM (19 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

158666

Message:

bs3kit,bs3-timers-1: Extended the bs3-timers-1 testcase to check for interrupt delivery and inhibiting. bugref:10369

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• Makefile.kmk (modified) (1 diff)
• bs3-timers-1-asm.asm (added)
• bs3-timers-1-x0.c (modified) (7 diffs)
• bs3-timers-1.c (modified) (2 diffs)
• bs3kit/bs3-cmn-PitIrqHandler.c (modified) (2 diffs)
• bs3kit/bs3-cmn-pit.c (modified) (1 diff)
• bs3kit/bs3kit.h (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/Makefile.kmk

@@ -426 +426 @@
         bs3kit/bs3-first-rm.asm \
         bs3-timers-1.c \
-        bs3-timers-1-x0.c
+        bs3-timers-1-x0.c \
+        bs3-timers-1-asm.asm
 
  #

trunk/src/VBox/ValidationKit/bootsectors/bs3-timers-1-x0.c

@@ -45 +45 @@
 
 
-static uint8_t bs3Timers1_Pit(uint8_t bMode, uint16_t uHz, uint32_t cNsMaxDiviation)
+/*********************************************************************************************************************************
+*   Structures and Typedefs                                                                                                      *
+*********************************************************************************************************************************/
+typedef enum BS3TIMERSIRQLOOP
+{
+    BS3TIMERSIRQLOOP_INVALID = 0,
+    BS3TIMERSIRQLOOP_SIMPLE,
+    BS3TIMERSIRQLOOP_STI_HLT_CLI,
+    BS3TIMERSIRQLOOP_STI_STI_CLI,
+    BS3TIMERSIRQLOOP_POPF_CLI,
+    BS3TIMERSIRQLOOP_END
+} BS3TIMERSIRQLOOP;
+
+
+typedef enum BS3TIMERSNOIRQLOOP
+{
+    BS3TIMERSNOIRQLOOP_INVALID = 0,
+    BS3TIMERSNOIRQLOOP_SIMPLE,
+    BS3TIMERSNOIRQLOOP_STI_CLI,
+    BS3TIMERSNOIRQLOOP_END
+} BS3TIMERSNOIRQLOOP;
+
+
+/*********************************************************************************************************************************
+*   External Assembly Functions                                                                                                  *
+*********************************************************************************************************************************/
+extern FNBS3NEAR bs3Timers1StiHltCli;
+extern FNBS3NEAR bs3Timers1StiHltCli_IrqPc;
+extern FNBS3NEAR bs3Timers1StiStiCli;
+extern FNBS3NEAR bs3Timers1StiStiCli_IrqPc;
+extern FNBS3NEAR bs3Timers1PopfCli;
+extern FNBS3NEAR bs3Timers1PopfCli_IrqPc;
+
+extern FNBS3NEAR bs3Timers1StiCli;
+
+
+
+static uint8_t bs3Timers1_Pit(uint8_t bMode, uint16_t uHz, uint32_t cNsMaxDiviation, BS3TIMERSIRQLOOP enmIrqLoop)
 {
     uint32_t const  cTargetTicks = uHz * 3;
@@ -53 +90 @@
     uint64_t        cNsDeltaAbs;
 
+    ASMIntEnable();
+    ASMNopPause();
+    ASMIntDisable();
+
+
+    ASMIntDisable(); /* paranoia */
     Bs3PitSetupAndEnablePeriodTimer(uHz);
     cNsElapsed = Bs3TestNow();
-    ASMIntEnable();
     uActualHz  = g_cBs3PitIntervalHz;
 
-    while (g_cBs3PitTicks < cTargetTicks)
-        ASMHalt();
+    switch (enmIrqLoop)
+    {
+        default:
+        case BS3TIMERSIRQLOOP_SIMPLE:
+            ASMIntEnable();
+            while (g_cBs3PitTicks < cTargetTicks)
+                ASMHalt();
+            break;
+
+        /* This variant enabls interrupt like this: sti; hlt; cli */
+        case BS3TIMERSIRQLOOP_STI_HLT_CLI:
+            while (g_cBs3PitTicks < cTargetTicks)
+            {
+                uint32_t const uIrqPc = g_Bs3PitIrqRip.u32;
+                if (uIrqPc == (uint16_t)&bs3Timers1StiHltCli_IrqPc || uIrqPc == 0)
+                    bs3Timers1StiHltCli();
+                else
+                {
+                    Bs3TestFailedF("IrqPC = %#RX32, expected %#RX16!\n", uIrqPc, (uint16_t)&bs3Timers1StiHltCli_IrqPc);
+                    break;
+                }
+            }
+            break;
+
+        /* This variant enabls interrupt like this: sti; sti; cli */
+        case BS3TIMERSIRQLOOP_STI_STI_CLI:
+            while (g_cBs3PitTicks < cTargetTicks)
+            {
+                uint32_t const uIrqPc = g_Bs3PitIrqRip.u32;
+                if (uIrqPc == (uint16_t)&bs3Timers1StiStiCli_IrqPc || uIrqPc == 0)
+                    bs3Timers1StiStiCli();
+                else
+                {
+                    Bs3TestFailedF("IrqPC = %#RX32, expected %#RX16!\n", uIrqPc, (uint16_t)&bs3Timers1StiStiCli_IrqPc);
+                    break;
+                }
+            }
+            break;
+
+        /* This variant enabls interrupt like this: enabling-if-popf; cli */
+        case BS3TIMERSIRQLOOP_POPF_CLI:
+            while (g_cBs3PitTicks < cTargetTicks)
+            {
+                uint32_t const uIrqPc = g_Bs3PitIrqRip.u32;
+                if (uIrqPc == (uint16_t)&bs3Timers1PopfCli_IrqPc || uIrqPc == 0)
+                    bs3Timers1PopfCli();
+                else
+                {
+                    Bs3TestFailedF("IrqPC = %#RX32, expected %#RX16!\n", uIrqPc, (uint16_t)&bs3Timers1PopfCli_IrqPc);
+                    break;
+                }
+            }
+            break;
+    }
 
     Bs3PitDisable();
@@ -73 +167 @@
         Bs3TestFailedF("delta %c%RU64 ns (%RI32 ms), max %RU32 ns", cNsDelta < 0 ? '-' : '+', cNsDeltaAbs,
                        (int32_t)((uint64_t)cNsDelta / RT_NS_1MS), cNsMaxDiviation);
+    else if (g_Bs3PitIrqRip.u32 == 0)
+        Bs3TestFailedF("g_Bs3PitIrqRip.u32 is zero!\n");
 
     return 0;
@@ -80 +176 @@
 BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz)(uint8_t bMode)
 {
-    return bs3Timers1_Pit(bMode, 100, RT_NS_10MS);
+    return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_SIMPLE);
 }
 
@@ -86 +182 @@
 BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_1000Hz)(uint8_t bMode)
 {
-    return bs3Timers1_Pit(bMode, 1000, RT_NS_10MS);
+    return bs3Timers1_Pit(bMode, 1000, RT_NS_10MS, BS3TIMERSIRQLOOP_SIMPLE);
 }
 
@@ -92 +188 @@
 BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_2000Hz)(uint8_t bMode)
 {
-    return bs3Timers1_Pit(bMode, 2000, RT_NS_10MS*2);
+    return bs3Timers1_Pit(bMode, 2000, RT_NS_10MS*2, BS3TIMERSIRQLOOP_SIMPLE);
 }
 
@@ -98 +194 @@
 BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_4000Hz)(uint8_t bMode)
 {
-    return bs3Timers1_Pit(bMode, 4000, RT_NS_10MS*4);
-}
-
+    return bs3Timers1_Pit(bMode, 4000, RT_NS_10MS*4, BS3TIMERSIRQLOOP_SIMPLE);
+}
+
+
+BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_wait1)(uint8_t bMode)
+{
+    return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_STI_HLT_CLI);
+}
+
+
+BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_wait2)(uint8_t bMode)
+{
+    return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_STI_STI_CLI);
+}
+
+
+BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_wait3)(uint8_t bMode)
+{
+    return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_POPF_CLI);
+}
+
+
+/**
+ * Negative test loop, i.e. no interrupts delivered.
+ *
+ * This is for testing interrupt disabling and inhibition
+ */
+static uint8_t bs3Timers1_PitNegative(uint8_t bMode, uint16_t uHz, BS3TIMERSNOIRQLOOP enmLoop)
+{
+    uint64_t uNsStart;
+
+    ASMIntDisable(); /* paranoia */
+    Bs3PitSetupAndEnablePeriodTimer(uHz);
+    uNsStart  = Bs3TestNow();
+
+    switch (enmLoop)
+    {
+        default:
+        case BS3TIMERSNOIRQLOOP_SIMPLE:
+            while (Bs3TestNow() - uNsStart < RT_NS_1SEC * 2)
+                ASMNopPause();
+            break;
+
+        case BS3TIMERSNOIRQLOOP_STI_CLI:
+            while (Bs3TestNow() - uNsStart < RT_NS_1SEC * 2)
+                bs3Timers1StiCli();
+            break;
+    }
+
+    Bs3PitDisable();
+
+    if (g_cBs3PitTicks > 0)
+        Bs3TestFailedF("g_cBs3PitTicks=%RU32, expected zero!\n", g_cBs3PitTicks);
+
+    ASMIntEnable();
+    ASMNopPause();
+    ASMIntDisable();
+
+    return 0;
+}
+
+
+BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_negative1)(uint8_t bMode)
+{
+    return bs3Timers1_PitNegative(bMode, 100, BS3TIMERSNOIRQLOOP_SIMPLE);
+}
+
+
+BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_negative2)(uint8_t bMode)
+{
+    return bs3Timers1_PitNegative(bMode, 100, BS3TIMERSNOIRQLOOP_STI_CLI);
+}
+

trunk/src/VBox/ValidationKit/bootsectors/bs3-timers-1.c

@@ -50 +50 @@
 FNBS3TESTDOMODE             bs3Timers1_Pit_2000Hz_f16;
 FNBS3TESTDOMODE             bs3Timers1_Pit_4000Hz_f16;
+FNBS3TESTDOMODE             bs3Timers1_Pit_100Hz_wait1_f16;
+FNBS3TESTDOMODE             bs3Timers1_Pit_100Hz_wait2_f16;
+FNBS3TESTDOMODE             bs3Timers1_Pit_100Hz_wait3_f16;
+FNBS3TESTDOMODE             bs3Timers1_Pit_100Hz_negative1_f16;
+FNBS3TESTDOMODE             bs3Timers1_Pit_100Hz_negative2_f16;
 
 
@@ -57 +62 @@
 static const BS3TESTMODEBYONEENTRY g_aModeByOneTests[] =
 {
-    { "pit-100Hz",      bs3Timers1_Pit_100Hz_f16,  BS3TESTMODEBYONEENTRY_F_MINIMAL },
-    { "pit-1000Hz",     bs3Timers1_Pit_1000Hz_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
-    { "pit-2000Hz",     bs3Timers1_Pit_2000Hz_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
-    { "pit-4000Hz",     bs3Timers1_Pit_4000Hz_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+#if 0
+    { "pit-100Hz",          bs3Timers1_Pit_100Hz_f16,  BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-1000Hz",         bs3Timers1_Pit_1000Hz_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-2000Hz",         bs3Timers1_Pit_2000Hz_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-4000Hz",         bs3Timers1_Pit_4000Hz_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-100Hz-wait1",    bs3Timers1_Pit_100Hz_wait1_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+#endif
+    { "pit-100Hz-wait2",    bs3Timers1_Pit_100Hz_wait2_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-100Hz-wait3",    bs3Timers1_Pit_100Hz_wait3_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-100Hz-neg1",     bs3Timers1_Pit_100Hz_negative1_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
+    { "pit-100Hz-neg2",     bs3Timers1_Pit_100Hz_negative2_f16, BS3TESTMODEBYONEENTRY_F_MINIMAL },
 };
 

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-PitIrqHandler.c

@@ -47 +47 @@
 *********************************************************************************************************************************/
 #if ARCH_BITS == 16
+/** The RIP/EIP value of where the PIT IRQ handle will return to. */
+BS3REG volatile     g_Bs3PitIrqRip;
 /** Nano seconds (approx) since last the PIT timer was started. */
 uint64_t volatile   g_cBs3PitNs    = 0;
@@ -70 +72 @@
         g_cBs3PitNs += g_cBs3PitIntervalNs;
         g_cBs3PitTicks++;
+        g_Bs3PitIrqRip.u = pTrapFrame->Ctx.rip.u;
     }
     NOREF(pTrapFrame);

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-pit.c

@@ -75 +75 @@
 
     /*
-     * Reset the counters.
+     * Reset the counters and IRQ PC.
      */
     g_cBs3PitNs         = 0;
     g_cBs3PitMs         = 0;
     g_cBs3PitTicks      = 0;
+    g_Bs3PitIrqRip.u    = 0;
 
     /*

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3kit.h

@@ -2516 +2516 @@
 BS3_CMN_PROTO_STUB(void BS3_FAR *, Bs3PagingSetupCanonicalTraps,(void));
 
-/**
- * Waits for the keyboard controller to become ready.
- */
-BS3_CMN_PROTO_NOSB(void, Bs3KbdWait,(void));
-
-/**
- * Sends a read command to the keyboard controller and gets the result.
- *
- * The caller is responsible for making sure the keyboard controller is ready
- * for a command (call #Bs3KbdWait if unsure).
- *
- * @returns The value read is returned (in al).
- * @param   bCmd            The read command.
- */
-BS3_CMN_PROTO_NOSB(uint8_t, Bs3KbdRead,(uint8_t bCmd));
-
-/**
- * Sends a write command to the keyboard controller and then sends the data.
- *
- * The caller is responsible for making sure the keyboard controller is ready
- * for a command (call #Bs3KbdWait if unsure).
- *
- * @param   bCmd           The write command.
- * @param   bData          The data to write.
- */
-BS3_CMN_PROTO_NOSB(void, Bs3KbdWrite,(uint8_t bCmd, uint8_t bData));
-
-
-/**
- * Configures the PIC, once only.
- *
- * Subsequent calls to this function will not do anything.
- *
- * The PIC will be programmed to use IDT/IVT vectors 0x70 thru 0x7f, auto
- * end-of-interrupt, and all IRQs masked.  The individual PIC users will have to
- * use #Bs3PicUpdateMask unmask their IRQ once they've got all the handlers
- * installed.
- *
- * @param   fForcedReInit   Force a reinitialization.
- */
-BS3_CMN_PROTO_STUB(void, Bs3PicSetup,(bool fForcedReInit));
-
-/**
- * Updates the PIC masks.
- *
- * @returns The new mask - master in low, slave in high byte.
- * @param   fAndMask    Things to keep as-is. Master in low, slave in high byte.
- * @param   fOrMask     Things to start masking. Ditto wrt bytes.
- */
-BS3_CMN_PROTO_STUB(uint16_t, Bs3PicUpdateMask,(uint16_t fAndMask, uint16_t fOrMask));
-
-/**
- * Disables all IRQs on the PIC.
- */
-BS3_CMN_PROTO_STUB(void, Bs3PicMaskAll,(void));
-
-
-/**
- * Sets up the PIT for periodic callback.
- *
- * @param   cHzDesired      The desired Hz.  Zero means max interval length
- *                          (18.2Hz).  Plase check the various PIT globals for
- *                          the actual interval length.
- */
-BS3_CMN_PROTO_STUB(void, Bs3PitSetupAndEnablePeriodTimer,(uint16_t cHzDesired));
-
-/**
- * Disables the PIT if active.
- */
-BS3_CMN_PROTO_STUB(void, Bs3PitDisable,(void));
-
-/** Nanoseconds (approx) since last the PIT timer was started. */
-extern uint64_t volatile    g_cBs3PitNs;
-/** Milliseconds seconds (very approx) since last the PIT timer was started. */
-extern uint64_t volatile    g_cBs3PitMs;
-/** Number of ticks since last the PIT timer was started.  */
-extern uint32_t volatile    g_cBs3PitTicks;
-/** The current interval in nanoseconds.
- * This is 0 if not yet started (cleared by Bs3PitDisable). */
-extern uint32_t             g_cBs3PitIntervalNs;
-/** The current interval in milliseconds (approximately).
- * This is 0 if not yet started (cleared by Bs3PitDisable). */
-extern uint16_t             g_cBs3PitIntervalMs;
-/** The current PIT frequency (approximately).
- * 0 if not yet started (cleared by Bs3PitDisable; used for checking the
- * state internally). */
-extern uint16_t volatile    g_cBs3PitIntervalHz;
-
 
 /**
@@ -4504 +4416 @@
 
 
+/** @defgroup grp_bs3kit_kbd    Keyboard
+ * @{
+ */
+
+/**
+ * Waits for the keyboard controller to become ready.
+ */
+BS3_CMN_PROTO_NOSB(void, Bs3KbdWait,(void));
+
+/**
+ * Sends a read command to the keyboard controller and gets the result.
+ *
+ * The caller is responsible for making sure the keyboard controller is ready
+ * for a command (call #Bs3KbdWait if unsure).
+ *
+ * @returns The value read is returned (in al).
+ * @param   bCmd            The read command.
+ */
+BS3_CMN_PROTO_NOSB(uint8_t, Bs3KbdRead,(uint8_t bCmd));
+
+/**
+ * Sends a write command to the keyboard controller and then sends the data.
+ *
+ * The caller is responsible for making sure the keyboard controller is ready
+ * for a command (call #Bs3KbdWait if unsure).
+ *
+ * @param   bCmd           The write command.
+ * @param   bData          The data to write.
+ */
+BS3_CMN_PROTO_NOSB(void, Bs3KbdWrite,(uint8_t bCmd, uint8_t bData));
+
+/** @} */
+
+
+/** @defgroup grp_bs3kit_pic    PIC
+ * @{
+ */
+
+/**
+ * Configures the PIC, once only.
+ *
+ * Subsequent calls to this function will not do anything.
+ *
+ * The PIC will be programmed to use IDT/IVT vectors 0x70 thru 0x7f, auto
+ * end-of-interrupt, and all IRQs masked.  The individual PIC users will have to
+ * use #Bs3PicUpdateMask unmask their IRQ once they've got all the handlers
+ * installed.
+ *
+ * @param   fForcedReInit   Force a reinitialization.
+ */
+BS3_CMN_PROTO_STUB(void, Bs3PicSetup,(bool fForcedReInit));
+
+/**
+ * Updates the PIC masks.
+ *
+ * @returns The new mask - master in low, slave in high byte.
+ * @param   fAndMask    Things to keep as-is. Master in low, slave in high byte.
+ * @param   fOrMask     Things to start masking. Ditto wrt bytes.
+ */
+BS3_CMN_PROTO_STUB(uint16_t, Bs3PicUpdateMask,(uint16_t fAndMask, uint16_t fOrMask));
+
+/**
+ * Disables all IRQs on the PIC.
+ */
+BS3_CMN_PROTO_STUB(void, Bs3PicMaskAll,(void));
+
+/** @} */
+
+
+/** @defgroup grp_bs3kit_pit    PIT
+ * @{
+ */
+
+/**
+ * Sets up the PIT for periodic callback.
+ *
+ * @param   cHzDesired      The desired Hz.  Zero means max interval length
+ *                          (18.2Hz).  Plase check the various PIT globals for
+ *                          the actual interval length.
+ */
+BS3_CMN_PROTO_STUB(void, Bs3PitSetupAndEnablePeriodTimer,(uint16_t cHzDesired));
+
+/**
+ * Disables the PIT if active.
+ */
+BS3_CMN_PROTO_STUB(void, Bs3PitDisable,(void));
+
+/** The RIP/EIP value of where the PIT IRQ handle will return to. */
+extern BS3REG volatile      g_Bs3PitIrqRip;
+/** Nanoseconds (approx) since last the PIT timer was started. */
+extern uint64_t volatile    g_cBs3PitNs;
+/** Milliseconds seconds (very approx) since last the PIT timer was started. */
+extern uint64_t volatile    g_cBs3PitMs;
+/** Number of ticks since last the PIT timer was started.  */
+extern uint32_t volatile    g_cBs3PitTicks;
+/** The current interval in nanoseconds.
+ * This is 0 if not yet started (cleared by Bs3PitDisable). */
+extern uint32_t             g_cBs3PitIntervalNs;
+/** The current interval in milliseconds (approximately).
+ * This is 0 if not yet started (cleared by Bs3PitDisable). */
+extern uint16_t             g_cBs3PitIntervalMs;
+/** The current PIT frequency (approximately).
+ * 0 if not yet started (cleared by Bs3PitDisable; used for checking the
+ * state internally). */
+extern uint16_t volatile    g_cBs3PitIntervalHz;
+
+/** @} */
+
+
 /** @} */