Changeset 100804 in vbox
- Timestamp:
- Aug 5, 2023 1:01:32 AM (16 months ago)
- Location:
- trunk
- Files:
-
- 7 edited
-
include/VBox/err.h (modified) (1 diff)
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src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h (modified) (3 diffs)
-
src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h (modified) (20 diffs)
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src/VBox/VMM/VMMAll/IEMAllThrdPython.py (modified) (1 diff)
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src/VBox/VMM/VMMR3/EM.cpp (modified) (1 diff)
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src/VBox/VMM/include/IEMInline.h (modified) (2 diffs)
-
src/VBox/VMM/include/IEMMc.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/err.h
r100791 r100804 2499 2499 * VERR, VERW). This is not used outside the instruction implementations. */ 2500 2500 #define VINF_IEM_SELECTOR_NOT_OK (5305) 2501 /** Recompiler: Translation block allocation failed. */ 2502 #define VERR_IEM_TB_ALLOC_FAILED (-5309) 2501 /** Returns by rep-prefixed string instruction if they yield because of 2502 * pending FFs. The status code is internal to IEM. */ 2503 #define VINF_IEM_YIELD_PENDING_FF (5306) 2503 2504 /** Recompiled execution: Break out of current TB execution. */ 2504 2505 #define VINF_IEM_REEXEC_BREAK (5310) 2505 2506 /** Recompilation: End translation block. */ 2506 2507 #define VINF_IEM_RECOMPILE_END_TB (5311) 2508 /** Recompiler: Translation block allocation failed. */ 2509 #define VERR_IEM_TB_ALLOC_FAILED (-5312) 2507 2510 2508 2511 /** Restart the current instruction. For testing only. */ -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h
r100052 r100804 92 92 LogFlow(("%s: Leaving early (outer)! ffcpu=%#RX64 ffvm=%#x\n", \ 93 93 __FUNCTION__, (uint64_t)(a_pVCpu)->fLocalForcedActions, (a_pVM)->fGlobalForcedActions)); \ 94 return VINF_ SUCCESS; \94 return VINF_IEM_YIELD_PENDING_FF; \ 95 95 } \ 96 96 } while (0) … … 111 111 LogFlow(("%s: Leaving early (inner)! ffcpu=%#RX64 ffvm=%#x\n", \ 112 112 __FUNCTION__, (uint64_t)(a_pVCpu)->fLocalForcedActions, (a_pVM)->fGlobalForcedActions)); \ 113 return VINF_ SUCCESS; \113 return VINF_IEM_YIELD_PENDING_FF; \ 114 114 } \ 115 115 } while (0) … … 131 131 LogFlow(("%s: Leaving early (inner)! ffcpu=%#RX64 (ffvm=%#x)\n", \ 132 132 __FUNCTION__, (uint64_t)(a_pVCpu)->fLocalForcedActions, (a_pVM)->fGlobalForcedActions)); \ 133 return VINF_ SUCCESS; \133 return VINF_IEM_YIELD_PENDING_FF; \ 134 134 } \ 135 135 } while (0) -
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r100787 r100804 3078 3078 switch (pVCpu->iem.s.enmEffAddrMode) 3079 3079 { 3080 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op8_addr16, false); 3081 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op8_addr32, false); 3082 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op8_addr64, false); 3080 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3081 iemCImpl_rep_ins_op8_addr16, false); 3082 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3083 iemCImpl_rep_ins_op8_addr32, false); 3084 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3085 iemCImpl_rep_ins_op8_addr64, false); 3083 3086 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3084 3087 } … … 3089 3092 switch (pVCpu->iem.s.enmEffAddrMode) 3090 3093 { 3091 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op8_addr16, false); 3092 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op8_addr32, false); 3093 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op8_addr64, false); 3094 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3095 iemCImpl_ins_op8_addr16, false); 3096 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3097 iemCImpl_ins_op8_addr32, false); 3098 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3099 iemCImpl_ins_op8_addr64, false); 3094 3100 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3095 3101 } … … 3113 3119 switch (pVCpu->iem.s.enmEffAddrMode) 3114 3120 { 3115 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op16_addr16, false); 3116 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op16_addr32, false); 3117 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op16_addr64, false); 3121 case IEMMODE_16BIT: 3122 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3123 iemCImpl_rep_ins_op16_addr16, false); 3124 case IEMMODE_32BIT: 3125 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3126 iemCImpl_rep_ins_op16_addr32, false); 3127 case IEMMODE_64BIT: 3128 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3129 iemCImpl_rep_ins_op16_addr64, false); 3118 3130 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3119 3131 } … … 3123 3135 switch (pVCpu->iem.s.enmEffAddrMode) 3124 3136 { 3125 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op32_addr16, false); 3126 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op32_addr32, false); 3127 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_ins_op32_addr64, false); 3137 case IEMMODE_16BIT: 3138 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3139 iemCImpl_rep_ins_op32_addr16, false); 3140 case IEMMODE_32BIT: 3141 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3142 iemCImpl_rep_ins_op32_addr32, false); 3143 case IEMMODE_64BIT: 3144 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3145 iemCImpl_rep_ins_op32_addr64, false); 3128 3146 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3129 3147 } … … 3140 3158 switch (pVCpu->iem.s.enmEffAddrMode) 3141 3159 { 3142 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op16_addr16, false); 3143 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op16_addr32, false); 3144 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op16_addr64, false); 3160 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3161 iemCImpl_ins_op16_addr16, false); 3162 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3163 iemCImpl_ins_op16_addr32, false); 3164 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3165 iemCImpl_ins_op16_addr64, false); 3145 3166 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3146 3167 } … … 3150 3171 switch (pVCpu->iem.s.enmEffAddrMode) 3151 3172 { 3152 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op32_addr16, false); 3153 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op32_addr32, false); 3154 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_ins_op32_addr64, false); 3173 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3174 iemCImpl_ins_op32_addr16, false); 3175 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3176 iemCImpl_ins_op32_addr32, false); 3177 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3178 iemCImpl_ins_op32_addr64, false); 3155 3179 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3156 3180 } … … 3174 3198 switch (pVCpu->iem.s.enmEffAddrMode) 3175 3199 { 3176 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3177 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3178 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3200 case IEMMODE_16BIT: 3201 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3202 iemCImpl_rep_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3203 case IEMMODE_32BIT: 3204 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3205 iemCImpl_rep_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3206 case IEMMODE_64BIT: 3207 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3208 iemCImpl_rep_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3179 3209 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3180 3210 } … … 3185 3215 switch (pVCpu->iem.s.enmEffAddrMode) 3186 3216 { 3187 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3188 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3189 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3217 case IEMMODE_16BIT: 3218 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3219 iemCImpl_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3220 case IEMMODE_32BIT: 3221 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3222 iemCImpl_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3223 case IEMMODE_64BIT: 3224 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3225 iemCImpl_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3190 3226 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3191 3227 } … … 3209 3245 switch (pVCpu->iem.s.enmEffAddrMode) 3210 3246 { 3211 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3212 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3213 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3247 case IEMMODE_16BIT: 3248 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3249 iemCImpl_rep_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3250 case IEMMODE_32BIT: 3251 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3252 iemCImpl_rep_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3253 case IEMMODE_64BIT: 3254 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3255 iemCImpl_rep_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3214 3256 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3215 3257 } … … 3219 3261 switch (pVCpu->iem.s.enmEffAddrMode) 3220 3262 { 3221 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3222 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3223 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT, iemCImpl_rep_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3263 case IEMMODE_16BIT: 3264 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3265 iemCImpl_rep_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3266 case IEMMODE_32BIT: 3267 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3268 iemCImpl_rep_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3269 case IEMMODE_64BIT: 3270 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3271 iemCImpl_rep_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3224 3272 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3225 3273 } … … 3236 3284 switch (pVCpu->iem.s.enmEffAddrMode) 3237 3285 { 3238 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3239 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3240 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3286 case IEMMODE_16BIT: 3287 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3288 iemCImpl_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3289 case IEMMODE_32BIT: 3290 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3291 iemCImpl_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3292 case IEMMODE_64BIT: 3293 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3294 iemCImpl_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3241 3295 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3242 3296 } … … 3246 3300 switch (pVCpu->iem.s.enmEffAddrMode) 3247 3301 { 3248 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3249 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3250 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3302 case IEMMODE_16BIT: 3303 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3304 iemCImpl_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3305 case IEMMODE_32BIT: 3306 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3307 iemCImpl_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3308 case IEMMODE_64BIT: 3309 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3310 iemCImpl_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3251 3311 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3252 3312 } … … 11446 11506 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11447 11507 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11448 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_in, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11508 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11509 iemCImpl_in, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11449 11510 } 11450 11511 … … 11456 11517 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11457 11518 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11458 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11519 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11520 iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11459 11521 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11460 11522 } … … 11467 11529 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11468 11530 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11469 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_out, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11531 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11532 iemCImpl_out, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11470 11533 } 11471 11534 … … 11477 11540 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11478 11541 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11479 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11542 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11543 iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11480 11544 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11481 11545 } … … 11592 11656 IEMOP_MNEMONIC(in_AL_DX, "in AL,DX"); 11593 11657 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11594 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_in_eAX_DX, 1, pVCpu->iem.s.enmEffAddrMode); 11658 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11659 iemCImpl_in_eAX_DX, 1, pVCpu->iem.s.enmEffAddrMode); 11595 11660 } 11596 11661 … … 11601 11666 IEMOP_MNEMONIC(in_eAX_DX, "in eAX,DX"); 11602 11667 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11603 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT ,11668 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11604 11669 iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11605 11670 pVCpu->iem.s.enmEffAddrMode); … … 11612 11677 IEMOP_MNEMONIC(out_DX_AL, "out DX,AL"); 11613 11678 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11614 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_out_DX_eAX, 1, pVCpu->iem.s.enmEffAddrMode); 11679 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11680 iemCImpl_out_DX_eAX, 1, pVCpu->iem.s.enmEffAddrMode); 11615 11681 } 11616 11682 … … 11621 11687 IEMOP_MNEMONIC(out_DX_eAX, "out DX,eAX"); 11622 11688 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11623 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT ,11689 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 11624 11690 iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11625 11691 pVCpu->iem.s.enmEffAddrMode); -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r100801 r100804 214 214 'IEM_CIMPL_F_VMEXIT': False, 215 215 'IEM_CIMPL_F_FPU': False, 216 'IEM_CIMPL_F_REP': True, 216 'IEM_CIMPL_F_REP': False, 217 'IEM_CIMPL_F_IO': False, 217 218 'IEM_CIMPL_F_END_TB': True, 218 219 'IEM_CIMPL_F_XCPT': True, -
trunk/src/VBox/VMM/VMMR3/EM.cpp
r100786 r100804 206 206 /** @cfgm{/EM/IemRecompiled, bool, true} 207 207 * Whether IEM bulk execution is recompiled or interpreted. */ 208 rc = CFGMR3QueryBoolDef(pCfgEM, "IemRecompiled", &pVM->em.s.fIemRecompiled, true);208 rc = CFGMR3QueryBoolDef(pCfgEM, "IemRecompiled", &pVM->em.s.fIemRecompiled, false); 209 209 AssertLogRelRCReturn(rc, rc); 210 210 #endif -
trunk/src/VBox/VMM/include/IEMInline.h
r100734 r100804 46 46 if (rcStrict != VINF_SUCCESS) 47 47 { 48 if (RT_SUCCESS(rcStrict)) 48 /* Deal with the cases that should be treated as VINF_SUCCESS first. */ 49 if ( rcStrict == VINF_IEM_YIELD_PENDING_FF 50 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX /** @todo r=bird: Why do we need TWO status codes here? */ 51 || rcStrict == VINF_VMX_VMEXIT 52 #endif 53 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM 54 || rcStrict == VINF_SVM_VMEXIT 55 #endif 56 ) 57 { 58 if (pVCpu->iem.s.rcPassUp == VINF_SUCCESS) 59 rcStrict = VINF_SUCCESS; 60 else 61 { 62 pVCpu->iem.s.cRetPassUpStatus++; 63 rcStrict = pVCpu->iem.s.rcPassUp; 64 } 65 } 66 else if (RT_SUCCESS(rcStrict)) 49 67 { 50 68 AssertMsg( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST) … … 71 89 || rcStrict == VINF_PATM_CHECK_PATCH_PAGE 72 90 /* nested hw.virt codes: */ 73 || rcStrict == VINF_VMX_VMEXIT74 91 || rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE 75 92 || rcStrict == VINF_VMX_MODIFIES_BEHAVIOR 76 || rcStrict == VINF_SVM_VMEXIT77 93 , ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 78 94 /** @todo adjust for VINF_EM_RAW_EMULATE_INSTR. */ 79 95 int32_t const rcPassUp = pVCpu->iem.s.rcPassUp; 80 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX81 if ( rcStrict == VINF_VMX_VMEXIT82 && rcPassUp == VINF_SUCCESS)83 rcStrict = VINF_SUCCESS;84 else85 #endif86 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM87 if ( rcStrict == VINF_SVM_VMEXIT88 && rcPassUp == VINF_SUCCESS)89 rcStrict = VINF_SUCCESS;90 else91 #endif92 96 if (rcPassUp == VINF_SUCCESS) 93 97 pVCpu->iem.s.cRetInfStatuses++; -
trunk/src/VBox/VMM/include/IEMMc.h
r100788 r100804 1271 1271 /** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */ 1272 1272 #define IEM_CIMPL_F_VMEXIT RT_BIT_32(10) 1273 /** May modify FPU state. */ 1273 /** May modify FPU state. 1274 * @todo Not sure if this is useful yet. */ 1274 1275 #define IEM_CIMPL_F_FPU RT_BIT_32(11) 1275 /** REP prefixed instruction which may yield before updating PC. */ 1276 /** REP prefixed instruction which may yield before updating PC. 1277 * @todo Not sure if this is useful, REP functions now return non-zero 1278 * status if they don't update the PC. */ 1276 1279 #define IEM_CIMPL_F_REP RT_BIT_32(12) 1277 /** Force end of TB after the instruction. */ 1278 #define IEM_CIMPL_F_END_TB RT_BIT_32(13) 1280 /** I/O instruction. 1281 * @todo Not sure if this is useful yet. */ 1282 #define IEM_CIMPL_F_IO RT_BIT_32(13) 1283 /** Force end of TB after the instruction. */ 1284 #define IEM_CIMPL_F_END_TB RT_BIT_32(14) 1279 1285 /** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */ 1280 1286 #define IEM_CIMPL_F_XCPT \
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