- Timestamp:
- Aug 9, 2023 5:52:37 PM (19 months ago)
- svn:sync-xref-src-repo-rev:
- 158741
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 7 edited
-
VMMAll/IEMAllAImplC.cpp (modified) (3 diffs)
-
VMMAll/IEMAllInstPython.py (modified) (1 diff)
-
VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (24 diffs)
-
include/IEMInternal.h (modified) (1 diff)
-
include/IEMMc.h (modified) (1 diff)
-
testcase/tstIEMAImpl.cpp (modified) (3 diffs)
-
testcase/tstIEMCheckMc.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r100831 r100840 1147 1147 */ 1148 1148 1149 IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))1149 IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t const *puDst, uint64_t uSrc, uint32_t *pfEFlags)) 1150 1150 { 1151 1151 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're … … 1161 1161 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) 1162 1162 1163 IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))1163 IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t const *puDst, uint32_t uSrc, uint32_t *pfEFlags)) 1164 1164 { 1165 1165 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're … … 1173 1173 } 1174 1174 1175 IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))1175 IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t const *puDst, uint16_t uSrc, uint32_t *pfEFlags)) 1176 1176 { 1177 1177 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r100826 r100840 2859 2859 'IEM_MC_REF_GREG_I64_CONST': (McBlock.parseMcGeneric, False), 2860 2860 'IEM_MC_REF_GREG_U16': (McBlock.parseMcGeneric, False), 2861 'IEM_MC_REF_GREG_U16_CONST': (McBlock.parseMcGeneric, False), 2861 2862 'IEM_MC_REF_GREG_U32': (McBlock.parseMcGeneric, False), 2863 'IEM_MC_REF_GREG_U32_CONST': (McBlock.parseMcGeneric, False), 2862 2864 'IEM_MC_REF_GREG_U64': (McBlock.parseMcGeneric, False), 2865 'IEM_MC_REF_GREG_U64_CONST': (McBlock.parseMcGeneric, False), 2863 2866 'IEM_MC_REF_GREG_U8': (McBlock.parseMcGeneric, False), 2867 'IEM_MC_REF_GREG_U8_CONST': (McBlock.parseMcGeneric, False), 2864 2868 'IEM_MC_REF_LOCAL': (McBlock.parseMcGeneric, False), 2865 2869 'IEM_MC_REF_MREG_U32_CONST': (McBlock.parseMcGeneric, False), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r100769 r100840 8927 8927 * iemOp_bts_Ev_Gv. 8928 8928 */ 8929 #define IEMOP_BODY_BIT_Ev_Gv(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_fRW) \ 8929 8930 #define IEMOP_BODY_BIT_Ev_Gv_RW(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64) \ 8930 8931 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 8931 8932 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF); \ … … 9000 9001 { \ 9001 9002 case IEMMODE_16BIT: \ 9002 IEM_MC_BEGIN(3, 2); \9003 IEM_MC_BEGIN(3, 4); \ 9003 9004 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 9004 9005 IEM_MC_ARG(uint16_t, u16Src, 1); \ … … 9006 9007 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9007 9008 IEM_MC_LOCAL(int16_t, i16AddrAdj); \ 9009 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9008 9010 \ 9009 9011 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ … … 9017 9019 IEM_MC_FETCH_EFLAGS(EFlags); \ 9018 9020 \ 9019 IEM_MC_MEM_MAP (pu16Dst, a_fRW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); \9021 IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9020 9022 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 9021 IEM_MC_MEM_COMMIT_AND_UNMAP (pu16Dst, a_fRW); \9023 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(pu16Dst, bUnmapInfo); \ 9022 9024 \ 9023 9025 IEM_MC_COMMIT_EFLAGS(EFlags); \ … … 9027 9029 \ 9028 9030 case IEMMODE_32BIT: \ 9029 IEM_MC_BEGIN(3, 2); \9031 IEM_MC_BEGIN(3, 4); \ 9030 9032 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 9031 9033 IEM_MC_ARG(uint32_t, u32Src, 1); \ … … 9033 9035 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9034 9036 IEM_MC_LOCAL(int32_t, i32AddrAdj); \ 9037 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9035 9038 \ 9036 9039 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ … … 9044 9047 IEM_MC_FETCH_EFLAGS(EFlags); \ 9045 9048 \ 9046 IEM_MC_MEM_MAP (pu32Dst, a_fRW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); \9049 IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9047 9050 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 9048 IEM_MC_MEM_COMMIT_AND_UNMAP (pu32Dst, a_fRW); \9051 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(pu32Dst, bUnmapInfo); \ 9049 9052 \ 9050 9053 IEM_MC_COMMIT_EFLAGS(EFlags); \ … … 9054 9057 \ 9055 9058 case IEMMODE_64BIT: \ 9056 IEM_MC_BEGIN(3, 2); \9059 IEM_MC_BEGIN(3, 5); \ 9057 9060 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 9058 9061 IEM_MC_ARG(uint64_t, u64Src, 1); \ … … 9060 9063 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9061 9064 IEM_MC_LOCAL(int64_t, i64AddrAdj); \ 9065 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9062 9066 \ 9063 9067 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ … … 9071 9075 IEM_MC_FETCH_EFLAGS(EFlags); \ 9072 9076 \ 9073 IEM_MC_MEM_MAP (pu64Dst, a_fRW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); \9077 IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9074 9078 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 9075 IEM_MC_MEM_COMMIT_AND_UNMAP (pu64Dst, a_fRW); \9079 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(pu64Dst, bUnmapInfo); \ 9076 9080 \ 9077 9081 IEM_MC_COMMIT_EFLAGS(EFlags); \ … … 9086 9090 { \ 9087 9091 (void)0 9088 9089 #define IEMOP_BODY_BIT_Ev_Gv_NO_LOCK() \ 9090 IEMOP_HLP_DONE_DECODING(); \ 9091 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 9092 } \ 9093 } \ 9094 (void)0 9095 9092 /* Separate macro to work around parsing issue in IEMAllInstPython.py */ 9096 9093 #define IEMOP_BODY_BIT_Ev_Gv_LOCKED(a_fnLockedU16, a_fnLockedU32, a_fnLockedU64) \ 9097 9094 switch (pVCpu->iem.s.enmEffOpSize) \ 9098 9095 { \ 9099 9096 case IEMMODE_16BIT: \ 9100 IEM_MC_BEGIN(3, 2); \9097 IEM_MC_BEGIN(3, 4); \ 9101 9098 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 9102 9099 IEM_MC_ARG(uint16_t, u16Src, 1); \ … … 9104 9101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9105 9102 IEM_MC_LOCAL(int16_t, i16AddrAdj); \ 9103 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9106 9104 \ 9107 9105 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ … … 9115 9113 IEM_MC_FETCH_EFLAGS(EFlags); \ 9116 9114 \ 9117 IEM_MC_MEM_MAP (pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); \9115 IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9118 9116 IEM_MC_CALL_VOID_AIMPL_3(a_fnLockedU16, pu16Dst, u16Src, pEFlags); \ 9119 IEM_MC_MEM_COMMIT_AND_UNMAP (pu16Dst, IEM_ACCESS_DATA_RW); \9117 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(pu16Dst, bUnmapInfo); \ 9120 9118 \ 9121 9119 IEM_MC_COMMIT_EFLAGS(EFlags); \ … … 9125 9123 \ 9126 9124 case IEMMODE_32BIT: \ 9127 IEM_MC_BEGIN(3, 2); \9125 IEM_MC_BEGIN(3, 4); \ 9128 9126 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 9129 9127 IEM_MC_ARG(uint32_t, u32Src, 1); \ … … 9131 9129 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9132 9130 IEM_MC_LOCAL(int32_t, i32AddrAdj); \ 9131 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9133 9132 \ 9134 9133 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ … … 9142 9141 IEM_MC_FETCH_EFLAGS(EFlags); \ 9143 9142 \ 9144 IEM_MC_MEM_MAP (pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); \9143 IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9145 9144 IEM_MC_CALL_VOID_AIMPL_3(a_fnLockedU32, pu32Dst, u32Src, pEFlags); \ 9146 IEM_MC_MEM_COMMIT_AND_UNMAP (pu32Dst, IEM_ACCESS_DATA_RW); \9145 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(pu32Dst, bUnmapInfo); \ 9147 9146 \ 9148 9147 IEM_MC_COMMIT_EFLAGS(EFlags); \ … … 9152 9151 \ 9153 9152 case IEMMODE_64BIT: \ 9154 IEM_MC_BEGIN(3, 2); \9153 IEM_MC_BEGIN(3, 4); \ 9155 9154 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 9156 9155 IEM_MC_ARG(uint64_t, u64Src, 1); \ … … 9158 9157 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9159 9158 IEM_MC_LOCAL(int64_t, i64AddrAdj); \ 9159 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9160 9160 \ 9161 9161 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ … … 9169 9169 IEM_MC_FETCH_EFLAGS(EFlags); \ 9170 9170 \ 9171 IEM_MC_MEM_MAP (pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); \9171 IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9172 9172 IEM_MC_CALL_VOID_AIMPL_3(a_fnLockedU64, pu64Dst, u64Src, pEFlags); \ 9173 IEM_MC_MEM_COMMIT_AND_UNMAP (pu64Dst, IEM_ACCESS_DATA_RW); \9173 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(pu64Dst, bUnmapInfo); \ 9174 9174 \ 9175 9175 IEM_MC_COMMIT_EFLAGS(EFlags); \ … … 9184 9184 (void)0 9185 9185 9186 /* Read-only version (bt). */ 9187 #define IEMOP_BODY_BIT_Ev_Gv_RO(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64) \ 9188 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 9189 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF); \ 9190 \ 9191 if (IEM_IS_MODRM_REG_MODE(bRm)) \ 9192 { \ 9193 /* register destination. */ \ 9194 switch (pVCpu->iem.s.enmEffOpSize) \ 9195 { \ 9196 case IEMMODE_16BIT: \ 9197 IEM_MC_BEGIN(3, 0); \ 9198 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9199 IEM_MC_ARG(uint16_t const *, pu16Dst, 0); \ 9200 IEM_MC_ARG(uint16_t, u16Src, 1); \ 9201 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 9202 \ 9203 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9204 IEM_MC_AND_LOCAL_U16(u16Src, 0xf); \ 9205 IEM_MC_REF_GREG_U16_CONST(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9206 IEM_MC_REF_EFLAGS(pEFlags); \ 9207 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 9208 \ 9209 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9210 IEM_MC_END(); \ 9211 break; \ 9212 \ 9213 case IEMMODE_32BIT: \ 9214 IEM_MC_BEGIN(3, 0); \ 9215 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9216 IEM_MC_ARG(uint32_t const *, pu32Dst, 0); \ 9217 IEM_MC_ARG(uint32_t, u32Src, 1); \ 9218 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 9219 \ 9220 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9221 IEM_MC_AND_LOCAL_U32(u32Src, 0x1f); \ 9222 IEM_MC_REF_GREG_U32_CONST(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9223 IEM_MC_REF_EFLAGS(pEFlags); \ 9224 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 9225 \ 9226 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9227 IEM_MC_END(); \ 9228 break; \ 9229 \ 9230 case IEMMODE_64BIT: \ 9231 IEM_MC_BEGIN(3, 0); \ 9232 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9233 IEM_MC_ARG(uint64_t const *, pu64Dst, 0); \ 9234 IEM_MC_ARG(uint64_t, u64Src, 1); \ 9235 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 9236 \ 9237 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9238 IEM_MC_AND_LOCAL_U64(u64Src, 0x3f); \ 9239 IEM_MC_REF_GREG_U64_CONST(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9240 IEM_MC_REF_EFLAGS(pEFlags); \ 9241 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 9242 \ 9243 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9244 IEM_MC_END(); \ 9245 break; \ 9246 \ 9247 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 9248 } \ 9249 } \ 9250 else \ 9251 { \ 9252 /* memory destination. */ \ 9253 /** @todo test negative bit offsets! */ \ 9254 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \ 9255 { \ 9256 switch (pVCpu->iem.s.enmEffOpSize) \ 9257 { \ 9258 case IEMMODE_16BIT: \ 9259 IEM_MC_BEGIN(3, 4); \ 9260 IEM_MC_ARG(uint16_t const *, pu16Dst, 0); \ 9261 IEM_MC_ARG(uint16_t, u16Src, 1); \ 9262 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 9263 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9264 IEM_MC_LOCAL(int16_t, i16AddrAdj); \ 9265 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9266 \ 9267 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 9268 IEMOP_HLP_DONE_DECODING(); \ 9269 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9270 IEM_MC_ASSIGN(i16AddrAdj, u16Src); \ 9271 IEM_MC_AND_ARG_U16(u16Src, 0x0f); \ 9272 IEM_MC_SAR_LOCAL_S16(i16AddrAdj, 4); \ 9273 IEM_MC_SHL_LOCAL_S16(i16AddrAdj, 1); \ 9274 IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(GCPtrEffDst, i16AddrAdj); \ 9275 IEM_MC_FETCH_EFLAGS(EFlags); \ 9276 \ 9277 IEM_MC_MEM_MAP_U16_RO(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9278 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 9279 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(pu16Dst, bUnmapInfo); \ 9280 \ 9281 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9282 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9283 IEM_MC_END(); \ 9284 break; \ 9285 \ 9286 case IEMMODE_32BIT: \ 9287 IEM_MC_BEGIN(3, 4); \ 9288 IEM_MC_ARG(uint32_t const *, pu32Dst, 0); \ 9289 IEM_MC_ARG(uint32_t, u32Src, 1); \ 9290 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 9291 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9292 IEM_MC_LOCAL(int32_t, i32AddrAdj); \ 9293 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9294 \ 9295 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 9296 IEMOP_HLP_DONE_DECODING(); \ 9297 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9298 IEM_MC_ASSIGN(i32AddrAdj, u32Src); \ 9299 IEM_MC_AND_ARG_U32(u32Src, 0x1f); \ 9300 IEM_MC_SAR_LOCAL_S32(i32AddrAdj, 5); \ 9301 IEM_MC_SHL_LOCAL_S32(i32AddrAdj, 2); \ 9302 IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(GCPtrEffDst, i32AddrAdj); \ 9303 IEM_MC_FETCH_EFLAGS(EFlags); \ 9304 \ 9305 IEM_MC_MEM_MAP_U32_RO(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9306 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 9307 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(pu32Dst, bUnmapInfo); \ 9308 \ 9309 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9310 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9311 IEM_MC_END(); \ 9312 break; \ 9313 \ 9314 case IEMMODE_64BIT: \ 9315 IEM_MC_BEGIN(3, 4); \ 9316 IEM_MC_ARG(uint64_t const *, pu64Dst, 0); \ 9317 IEM_MC_ARG(uint64_t, u64Src, 1); \ 9318 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 9319 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9320 IEM_MC_LOCAL(int64_t, i64AddrAdj); \ 9321 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9322 \ 9323 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 9324 IEMOP_HLP_DONE_DECODING(); \ 9325 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9326 IEM_MC_ASSIGN(i64AddrAdj, u64Src); \ 9327 IEM_MC_AND_ARG_U64(u64Src, 0x3f); \ 9328 IEM_MC_SAR_LOCAL_S64(i64AddrAdj, 6); \ 9329 IEM_MC_SHL_LOCAL_S64(i64AddrAdj, 3); \ 9330 IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(GCPtrEffDst, i64AddrAdj); \ 9331 IEM_MC_FETCH_EFLAGS(EFlags); \ 9332 \ 9333 IEM_MC_MEM_MAP_U64_RO(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9334 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 9335 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(pu64Dst, bUnmapInfo); \ 9336 \ 9337 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9338 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9339 IEM_MC_END(); \ 9340 break; \ 9341 \ 9342 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 9343 } \ 9344 } \ 9345 else \ 9346 { \ 9347 IEMOP_HLP_DONE_DECODING(); \ 9348 IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \ 9349 } \ 9350 } \ 9351 (void)0 9352 9186 9353 9187 9354 /** Opcode 0x0f 0xa3. */ … … 9190 9357 IEMOP_MNEMONIC(bt_Ev_Gv, "bt Ev,Gv"); 9191 9358 IEMOP_HLP_MIN_386(); 9192 IEMOP_BODY_BIT_Ev_Gv(iemAImpl_bt_u16, iemAImpl_bt_u32, iemAImpl_bt_u64, IEM_ACCESS_DATA_R); 9193 IEMOP_BODY_BIT_Ev_Gv_NO_LOCK(); 9359 IEMOP_BODY_BIT_Ev_Gv_RO(iemAImpl_bt_u16, iemAImpl_bt_u32, iemAImpl_bt_u64); 9194 9360 } 9195 9361 … … 9546 9712 IEMOP_MNEMONIC(bts_Ev_Gv, "bts Ev,Gv"); 9547 9713 IEMOP_HLP_MIN_386(); 9548 IEMOP_BODY_BIT_Ev_Gv ( iemAImpl_bts_u16, iemAImpl_bts_u32, iemAImpl_bts_u64, IEM_ACCESS_DATA_RW);9714 IEMOP_BODY_BIT_Ev_Gv_RW( iemAImpl_bts_u16, iemAImpl_bts_u32, iemAImpl_bts_u64); 9549 9715 IEMOP_BODY_BIT_Ev_Gv_LOCKED(iemAImpl_bts_u16_locked, iemAImpl_bts_u32_locked, iemAImpl_bts_u64_locked); 9550 9716 } … … 10305 10471 IEMOP_MNEMONIC(btr_Ev_Gv, "btr Ev,Gv"); 10306 10472 IEMOP_HLP_MIN_386(); 10307 IEMOP_BODY_BIT_Ev_Gv ( iemAImpl_btr_u16, iemAImpl_btr_u32, iemAImpl_btr_u64, IEM_ACCESS_DATA_RW);10473 IEMOP_BODY_BIT_Ev_Gv_RW( iemAImpl_btr_u16, iemAImpl_btr_u32, iemAImpl_btr_u64); 10308 10474 IEMOP_BODY_BIT_Ev_Gv_LOCKED(iemAImpl_btr_u16_locked, iemAImpl_btr_u32_locked, iemAImpl_btr_u64_locked); 10309 10475 } … … 10823 10989 IEMOP_MNEMONIC(btc_Ev_Gv, "btc Ev,Gv"); 10824 10990 IEMOP_HLP_MIN_386(); 10825 IEMOP_BODY_BIT_Ev_Gv ( iemAImpl_btc_u16, iemAImpl_btc_u32, iemAImpl_btc_u64, IEM_ACCESS_DATA_RW);10991 IEMOP_BODY_BIT_Ev_Gv_RW( iemAImpl_btc_u16, iemAImpl_btc_u32, iemAImpl_btc_u64); 10826 10992 IEMOP_BODY_BIT_Ev_Gv_LOCKED(iemAImpl_btc_u16_locked, iemAImpl_btc_u32_locked, iemAImpl_btc_u64_locked); 10827 10993 } -
trunk/src/VBox/VMM/include/IEMInternal.h
r100831 r100840 1836 1836 /** @name Bit operations operations (thrown in with the binary ops). 1837 1837 * @{ */ 1838 FNIEMAIMPLBIN U16 iemAImpl_bt_u16;1839 FNIEMAIMPLBIN U32 iemAImpl_bt_u32;1840 FNIEMAIMPLBIN U64 iemAImpl_bt_u64;1838 FNIEMAIMPLBINROU16 iemAImpl_bt_u16; 1839 FNIEMAIMPLBINROU32 iemAImpl_bt_u32; 1840 FNIEMAIMPLBINROU64 iemAImpl_bt_u64; 1841 1841 FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked; 1842 1842 FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked; -
trunk/src/VBox/VMM/include/IEMMc.h
r100831 r100840 271 271 272 272 #define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg)) 273 #define IEM_MC_REF_GREG_U8_CONST(a_pu8Dst, a_iGReg) (a_pu8Dst) = (uint8_t const *)iemGRegRefU8( pVCpu, (a_iGReg)) 273 274 #define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg)) 275 #define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) (a_pu16Dst) = (uint16_t const *)iemGRegRefU16(pVCpu, (a_iGReg)) 274 276 /** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit. 275 277 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */ 276 278 #define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg)) 277 #define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg)) 278 #define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg)) 279 #define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) (a_pu32Dst) = (uint32_t const *)iemGRegRefU32(pVCpu, (a_iGReg)) 280 #define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg)) 281 #define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg)) 279 282 #define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg)) 280 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg)) 281 #define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg)) 283 #define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) (a_pu64Dst) = (uint64_t const *)iemGRegRefU64(pVCpu, (a_iGReg)) 284 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg)) 285 #define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg)) 282 286 /** @note Not for IOPL or IF testing or modification. 283 287 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */ -
trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp
r100831 r100840 1440 1440 ENTRY(and_u16), 1441 1441 ENTRY(and_u16_locked), 1442 ENTRY_PFN_CAST(cmp_u16, PFNIEMAIMPLBINU16),1443 ENTRY_PFN_CAST(test_u16, PFNIEMAIMPLBINU16),1444 ENTRY_ EX(bt_u16, 1),1442 ENTRY_PFN_CAST(cmp_u16, PFNIEMAIMPLBINU16), 1443 ENTRY_PFN_CAST(test_u16, PFNIEMAIMPLBINU16), 1444 ENTRY_PFN_CAST_EX(bt_u16, PFNIEMAIMPLBINU16, 1), 1445 1445 ENTRY_EX(btc_u16, 1), 1446 1446 ENTRY_EX(btc_u16_locked, 1), … … 1479 1479 ENTRY(and_u32), 1480 1480 ENTRY(and_u32_locked), 1481 ENTRY_PFN_CAST(cmp_u32, PFNIEMAIMPLBINU32),1482 ENTRY_PFN_CAST(test_u32, PFNIEMAIMPLBINU32),1483 ENTRY_ EX(bt_u32, 1),1481 ENTRY_PFN_CAST(cmp_u32, PFNIEMAIMPLBINU32), 1482 ENTRY_PFN_CAST(test_u32, PFNIEMAIMPLBINU32), 1483 ENTRY_PFN_CAST_EX(bt_u32, PFNIEMAIMPLBINU32, 1), 1484 1484 ENTRY_EX(btc_u32, 1), 1485 1485 ENTRY_EX(btc_u32_locked, 1), … … 1517 1517 ENTRY(and_u64), 1518 1518 ENTRY(and_u64_locked), 1519 ENTRY_PFN_CAST(cmp_u64, PFNIEMAIMPLBINU64),1520 ENTRY_PFN_CAST(test_u64, PFNIEMAIMPLBINU64),1521 ENTRY_ EX(bt_u64, 1),1519 ENTRY_PFN_CAST(cmp_u64, PFNIEMAIMPLBINU64), 1520 ENTRY_PFN_CAST(test_u64, PFNIEMAIMPLBINU64), 1521 ENTRY_PFN_CAST_EX(bt_u64, PFNIEMAIMPLBINU64, 1), 1522 1522 ENTRY_EX(btc_u64, 1), 1523 1523 ENTRY_EX(btc_u64_locked, 1), -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r100826 r100840 675 675 #define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu16Dst) = (uint16_t *)((uintptr_t)0); CHK_PTYPE(uint16_t *, a_pu16Dst); (void)fMcBegin; } while (0) 676 676 #define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu32Dst) = (uint32_t *)((uintptr_t)0); CHK_PTYPE(uint32_t *, a_pu32Dst); (void)fMcBegin; } while (0) 677 #define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); (void)fMcBegin; } while (0) 678 #define IEM_MC_REF_GREG_U8_CONST(a_pu8Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu8Dst) = (uint8_t const *)((uintptr_t)0); CHK_PTYPE(uint8_t const *, a_pu8Dst); (void)fMcBegin; } while (0) 679 #define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu16Dst) = (uint16_t const *)((uintptr_t)0); CHK_PTYPE(uint16_t const *, a_pu16Dst); (void)fMcBegin; } while (0) 680 #define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); (void)fMcBegin; } while (0) 681 #define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fMcBegin; } while (0) 677 682 #define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi32Dst) = (int32_t *)((uintptr_t)0); CHK_PTYPE(int32_t *, a_pi32Dst); (void)fMcBegin; } while (0) 683 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi64Dst) = (int64_t *)((uintptr_t)0); CHK_PTYPE(int64_t *, a_pi64Dst); (void)fMcBegin; } while (0) 678 684 #define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi32Dst) = (int32_t const *)((uintptr_t)0); CHK_PTYPE(int32_t const *, a_pi32Dst); (void)fMcBegin; } while (0) 679 #define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); (void)fMcBegin; } while (0)680 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi64Dst) = (int64_t *)((uintptr_t)0); CHK_PTYPE(int64_t *, a_pi64Dst); (void)fMcBegin; } while (0)681 685 #define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi64Dst) = (int64_t const *)((uintptr_t)0); CHK_PTYPE(int64_t const *, a_pi64Dst); (void)fMcBegin; } while (0) 682 686 #define IEM_MC_REF_EFLAGS(a_pEFlags) do { (a_pEFlags) = (uint32_t *)((uintptr_t)0); CHK_PTYPE(uint32_t *, a_pEFlags); (void)fMcBegin; } while (0)
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