Changeset 100849 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Aug 10, 2023 12:42:19 AM (18 months ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllMemRWTmplInline.cpp.h
r100848 r100849 51 51 #ifdef IEM_WITH_SETJMP 52 52 53 53 54 /********************************************************************************************************************************* 54 55 * Fetches * … … 78 79 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrEff); 79 80 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 80 if (pTlbe->uTag == uTag) 81 { 82 /* 83 * Check TLB page table level access flags. 84 */ 85 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 86 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 87 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 88 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 89 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 90 { 91 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 92 81 if (RT_LIKELY(pTlbe->uTag == uTag)) 82 { 83 /* 84 * Check TLB page table level access flags. 85 */ 86 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 87 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 88 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 89 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 90 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 91 { 93 92 # if TMPL_MEM_TYPE_ALIGN != 0 94 93 /* … … 98 97 AssertCompile(X86_CR0_AM == X86_EFL_AC); 99 98 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 100 if ( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN)101 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0102 & pVCpu->cpum.GstCtx.eflags.u103 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */104 & X86_CR0_AM))99 if (RT_LIKELY( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN) 100 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 101 & pVCpu->cpum.GstCtx.eflags.u 102 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 103 & X86_CR0_AM) )) 105 104 # endif 106 105 { … … 108 107 * Fetch and return the dword 109 108 */ 109 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 110 110 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 111 111 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 114 114 return uRet; 115 115 } 116 # if TMPL_MEM_TYPE_ALIGN != 0117 Log10Func(("Raising #AC for %RGv\n", GCPtrEff));118 iemRaiseAlignmentCheckExceptionJmp(pVCpu);119 # endif120 116 } 121 117 } … … 149 145 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrMem); 150 146 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 151 if (pTlbe->uTag == uTag) 152 { 153 /* 154 * Check TLB page table level access flags. 155 */ 156 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 157 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 158 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 159 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 160 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 161 { 162 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 163 147 if (RT_LIKELY(pTlbe->uTag == uTag)) 148 { 149 /* 150 * Check TLB page table level access flags. 151 */ 152 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 153 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 154 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 155 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 156 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 157 { 164 158 # if TMPL_MEM_TYPE_ALIGN != 0 165 159 /* … … 169 163 AssertCompile(X86_CR0_AM == X86_EFL_AC); 170 164 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 171 if ( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN)172 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0173 & pVCpu->cpum.GstCtx.eflags.u174 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */175 & X86_CR0_AM))165 if (RT_LIKELY( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN) 166 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 167 & pVCpu->cpum.GstCtx.eflags.u 168 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 169 & X86_CR0_AM) )) 176 170 # endif 177 171 { … … 179 173 * Fetch and return the dword 180 174 */ 175 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 181 176 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 182 177 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 185 180 return uRet; 186 181 } 187 # if TMPL_MEM_TYPE_ALIGN != 0188 Log10Func(("Raising #AC for %RGv\n", GCPtrMem));189 iemRaiseAlignmentCheckExceptionJmp(pVCpu);190 # endif191 182 } 192 183 } … … 229 220 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrEff); 230 221 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 231 if (pTlbe->uTag == uTag) 232 { 233 /* 234 * Check TLB page table level access flags. 235 */ 236 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 237 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 238 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 239 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 240 | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 241 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 242 { 243 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 244 222 if (RT_LIKELY(pTlbe->uTag == uTag)) 223 { 224 /* 225 * Check TLB page table level access flags. 226 */ 227 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 228 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 229 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 230 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 231 | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 232 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 233 { 245 234 # if TMPL_MEM_TYPE_ALIGN != 0 246 235 /* … … 250 239 AssertCompile(X86_CR0_AM == X86_EFL_AC); 251 240 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 252 if ( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN)253 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0254 & pVCpu->cpum.GstCtx.eflags.u255 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */256 & X86_CR0_AM))241 if (RT_LIKELY( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN) 242 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 243 & pVCpu->cpum.GstCtx.eflags.u 244 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 245 & X86_CR0_AM) )) 257 246 # endif 258 247 { … … 260 249 * Store the dword and return. 261 250 */ 251 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 262 252 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 263 253 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 266 256 return; 267 257 } 268 # if TMPL_MEM_TYPE_ALIGN != 0269 Log10Func(("Raising #AC for %RGv\n", GCPtrEff));270 iemRaiseAlignmentCheckExceptionJmp(pVCpu);271 # endif272 258 } 273 259 } … … 302 288 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrMem); 303 289 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 304 if (pTlbe->uTag == uTag) 305 { 306 /* 307 * Check TLB page table level access flags. 308 */ 309 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 310 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 311 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 312 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 313 | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 314 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 315 { 316 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 317 290 if (RT_LIKELY(pTlbe->uTag == uTag)) 291 { 292 /* 293 * Check TLB page table level access flags. 294 */ 295 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 296 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 297 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 298 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 299 | IEMTLBE_F_NO_MAPPINGR3 | fNoUser)) 300 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 301 { 318 302 # if TMPL_MEM_TYPE_ALIGN != 0 319 303 /* … … 323 307 AssertCompile(X86_CR0_AM == X86_EFL_AC); 324 308 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 325 if ( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN)326 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0327 & pVCpu->cpum.GstCtx.eflags.u328 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */329 & X86_CR0_AM))309 if (RT_LIKELY( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN) 310 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 311 & pVCpu->cpum.GstCtx.eflags.u 312 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 313 & X86_CR0_AM) )) 330 314 # endif 331 315 { … … 333 317 * Store the dword and return. 334 318 */ 319 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 335 320 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 336 321 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 339 324 return; 340 325 } 341 # if TMPL_MEM_TYPE_ALIGN != 0342 Log10Func(("Raising #AC for %RGv\n", GCPtrMem));343 iemRaiseAlignmentCheckExceptionJmp(pVCpu);344 # endif345 326 } 346 327 } … … 383 364 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrEff); 384 365 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 385 if (pTlbe->uTag == uTag) 386 { 387 /* 388 * Check TLB page table level access flags. 389 */ 390 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 391 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 392 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 393 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE | IEMTLBE_F_PG_NO_READ 394 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 395 | fNoUser)) 396 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 397 { 398 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 399 366 if (RT_LIKELY(pTlbe->uTag == uTag)) 367 { 368 /* 369 * Check TLB page table level access flags. 370 */ 371 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 372 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 373 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 374 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE | IEMTLBE_F_PG_NO_READ 375 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 376 | fNoUser)) 377 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 378 { 400 379 # if TMPL_MEM_TYPE_ALIGN != 0 401 380 /* … … 405 384 AssertCompile(X86_CR0_AM == X86_EFL_AC); 406 385 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 407 if ( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN)408 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0409 & pVCpu->cpum.GstCtx.eflags.u410 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */411 & X86_CR0_AM))386 if (RT_LIKELY( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN) 387 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 388 & pVCpu->cpum.GstCtx.eflags.u 389 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 390 & X86_CR0_AM) )) 412 391 # endif 413 392 { … … 415 394 * Return the address. 416 395 */ 396 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 417 397 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 418 398 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 422 402 return (TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK]; 423 403 } 424 # if TMPL_MEM_TYPE_ALIGN != 0425 Log10Func(("Raising #AC for %RGv\n", GCPtrEff));426 iemRaiseAlignmentCheckExceptionJmp(pVCpu);427 # endif428 404 } 429 405 } … … 458 434 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrMem); 459 435 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 460 if (pTlbe->uTag == uTag) 461 { 462 /* 463 * Check TLB page table level access flags. 464 */ 465 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 466 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 467 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 468 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE | IEMTLBE_F_PG_NO_READ 469 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 470 | fNoUser)) 471 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 472 { 473 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 474 436 if (RT_LIKELY(pTlbe->uTag == uTag)) 437 { 438 /* 439 * Check TLB page table level access flags. 440 */ 441 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 442 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 443 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 444 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE | IEMTLBE_F_PG_NO_READ 445 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 446 | fNoUser)) 447 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 448 { 475 449 # if TMPL_MEM_TYPE_ALIGN != 0 476 450 /* … … 480 454 AssertCompile(X86_CR0_AM == X86_EFL_AC); 481 455 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 482 if ( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN)483 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0484 & pVCpu->cpum.GstCtx.eflags.u485 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */486 & X86_CR0_AM))456 if (RT_LIKELY( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN) 457 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 458 & pVCpu->cpum.GstCtx.eflags.u 459 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 460 & X86_CR0_AM) )) 487 461 # endif 488 462 { … … 490 464 * Return the address. 491 465 */ 466 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 492 467 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 493 468 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 497 472 return (TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK]; 498 473 } 499 # if TMPL_MEM_TYPE_ALIGN != 0500 Log10Func(("Raising #AC for %RGv\n", GCPtrMem));501 iemRaiseAlignmentCheckExceptionJmp(pVCpu);502 # endif503 474 } 504 475 } … … 534 505 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrEff); 535 506 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 536 if (pTlbe->uTag == uTag) 537 { 538 /* 539 * Check TLB page table level access flags. 540 */ 541 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 542 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 543 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 544 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 545 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 546 | fNoUser)) 547 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 548 { 549 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 550 507 if (RT_LIKELY(pTlbe->uTag == uTag)) 508 { 509 /* 510 * Check TLB page table level access flags. 511 */ 512 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 513 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 514 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 515 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 516 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 517 | fNoUser)) 518 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 519 { 551 520 # if TMPL_MEM_TYPE_ALIGN != 0 552 521 /* … … 556 525 AssertCompile(X86_CR0_AM == X86_EFL_AC); 557 526 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 558 if ( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN)559 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0560 & pVCpu->cpum.GstCtx.eflags.u561 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */562 & X86_CR0_AM))527 if (RT_LIKELY( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN) 528 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 529 & pVCpu->cpum.GstCtx.eflags.u 530 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 531 & X86_CR0_AM) )) 563 532 # endif 564 533 { … … 566 535 * Return the address. 567 536 */ 537 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 568 538 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 569 539 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 573 543 return (TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK]; 574 544 } 575 # if TMPL_MEM_TYPE_ALIGN != 0576 Log10Func(("Raising #AC for %RGv\n", GCPtrEff));577 iemRaiseAlignmentCheckExceptionJmp(pVCpu);578 # endif579 545 } 580 546 } … … 609 575 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrMem); 610 576 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 611 if (pTlbe->uTag == uTag) 612 { 613 /* 614 * Check TLB page table level access flags. 615 */ 616 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 617 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 618 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 619 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 620 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 621 | fNoUser)) 622 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 623 { 624 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 625 577 if (RT_LIKELY(pTlbe->uTag == uTag)) 578 { 579 /* 580 * Check TLB page table level access flags. 581 */ 582 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 583 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 584 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 585 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE 586 | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_WRITE 587 | fNoUser)) 588 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 589 { 626 590 # if TMPL_MEM_TYPE_ALIGN != 0 627 591 /* … … 631 595 AssertCompile(X86_CR0_AM == X86_EFL_AC); 632 596 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 633 if ( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN)634 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0635 & pVCpu->cpum.GstCtx.eflags.u636 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */637 & X86_CR0_AM))597 if (RT_LIKELY( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN) 598 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 599 & pVCpu->cpum.GstCtx.eflags.u 600 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 601 & X86_CR0_AM) )) 638 602 # endif 639 603 { … … 641 605 * Return the address. 642 606 */ 607 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 643 608 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 644 609 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 648 613 return (TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK]; 649 614 } 650 # if TMPL_MEM_TYPE_ALIGN != 0651 Log10Func(("Raising #AC for %RGv\n", GCPtrMem));652 iemRaiseAlignmentCheckExceptionJmp(pVCpu);653 # endif654 615 } 655 616 } … … 685 646 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrEff); 686 647 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 687 if (pTlbe->uTag == uTag) 688 { 689 /* 690 * Check TLB page table level access flags. 691 */ 692 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 693 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 694 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 695 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 696 | IEMTLBE_F_PT_NO_ACCESSED | fNoUser)) 697 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 698 { 699 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 700 648 if (RT_LIKELY(pTlbe->uTag == uTag)) 649 { 650 /* 651 * Check TLB page table level access flags. 652 */ 653 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 654 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 655 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 656 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 657 | IEMTLBE_F_PT_NO_ACCESSED | fNoUser)) 658 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 659 { 701 660 # if TMPL_MEM_TYPE_ALIGN != 0 702 661 /* … … 706 665 AssertCompile(X86_CR0_AM == X86_EFL_AC); 707 666 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 708 if ( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN)709 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0710 & pVCpu->cpum.GstCtx.eflags.u711 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */712 & X86_CR0_AM))667 if (RT_LIKELY( !(GCPtrEff & TMPL_MEM_TYPE_ALIGN) 668 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 669 & pVCpu->cpum.GstCtx.eflags.u 670 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 671 & X86_CR0_AM) )) 713 672 # endif 714 673 { … … 716 675 * Return the address. 717 676 */ 677 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 718 678 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 719 679 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 723 683 return (TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK]; 724 684 } 725 # if TMPL_MEM_TYPE_ALIGN != 0726 Log10Func(("Raising #AC for %RGv\n", GCPtrEff));727 iemRaiseAlignmentCheckExceptionJmp(pVCpu);728 # endif729 685 } 730 686 } … … 759 715 uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrMem); 760 716 PIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag); 761 if (pTlbe->uTag == uTag) 762 { 763 /* 764 * Check TLB page table level access flags. 765 */ 766 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 767 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 768 if ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 769 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 770 | IEMTLBE_F_PT_NO_ACCESSED | fNoUser)) 771 == pVCpu->iem.s.DataTlb.uTlbPhysRev) 772 { 773 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 774 717 if (RT_LIKELY(pTlbe->uTag == uTag)) 718 { 719 /* 720 * Check TLB page table level access flags. 721 */ 722 AssertCompile(IEMTLBE_F_PT_NO_USER == 4); 723 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER; 724 if (RT_LIKELY( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3 725 | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ 726 | IEMTLBE_F_PT_NO_ACCESSED | fNoUser)) 727 == pVCpu->iem.s.DataTlb.uTlbPhysRev)) 728 { 775 729 # if TMPL_MEM_TYPE_ALIGN != 0 776 730 /* … … 780 734 AssertCompile(X86_CR0_AM == X86_EFL_AC); 781 735 AssertCompile(((3U + 1U) << 16) == X86_CR0_AM); 782 if ( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN)783 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0784 & pVCpu->cpum.GstCtx.eflags.u785 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */786 & X86_CR0_AM))736 if (RT_LIKELY( !(GCPtrMem & TMPL_MEM_TYPE_ALIGN) 737 || !( (uint32_t)pVCpu->cpum.GstCtx.cr0 738 & pVCpu->cpum.GstCtx.eflags.u 739 & ((IEM_GET_CPL(pVCpu) + 1U) << 16) /* IEM_GET_CPL(pVCpu) == 3 ? X86_CR0_AM : 0 */ 740 & X86_CR0_AM) )) 787 741 # endif 788 742 { … … 790 744 * Return the address. 791 745 */ 746 STAM_STATS({pVCpu->iem.s.DataTlb.cTlbHits++;}); 792 747 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */ 793 748 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK)); … … 797 752 return (TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK]; 798 753 } 799 # if TMPL_MEM_TYPE_ALIGN != 0800 Log10Func(("Raising #AC for %RGv\n", GCPtrMem));801 iemRaiseAlignmentCheckExceptionJmp(pVCpu);802 # endif803 754 } 804 755 }
Note:
See TracChangeset
for help on using the changeset viewer.
