Changeset 101102 in vbox for trunk/include/iprt/armv8.h
- Timestamp:
- Sep 13, 2023 11:40:43 AM (15 months ago)
- File:
-
- 1 edited
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trunk/include/iprt/armv8.h (modified) (88 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/iprt/armv8.h
r101083 r101102 1150 1150 /* Bit 0 - 3 - Reserved. */ 1151 1151 /** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */ 1152 #define ARMV8_ID_AA64ISAR0_EL1_AES 1153 #define ARMV8_ID_AA64ISAR0_EL1_AES_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_AES) >> 4)1152 #define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1153 #define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4 1154 1154 /** No AES instructions implemented. */ 1155 1155 # define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0 … … 1159 1159 # define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2 1160 1160 /** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */ 1161 #define ARMV8_ID_AA64ISAR0_EL1_SHA1 1162 #define ARMV8_ID_AA64ISAR0_EL1_SHA1_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SHA1) >> 8)1161 #define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1162 #define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8 1163 1163 /** No SHA1 instructions implemented. */ 1164 1164 # define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0 … … 1166 1166 # define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1 1167 1167 /** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */ 1168 #define ARMV8_ID_AA64ISAR0_EL1_SHA2 1169 #define ARMV8_ID_AA64ISAR0_EL1_SHA2_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SHA2) >> 12)1168 #define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1169 #define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12 1170 1170 /** No SHA2 instructions implemented. */ 1171 1171 # define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0 … … 1175 1175 # define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2 1176 1176 /** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */ 1177 #define ARMV8_ID_AA64ISAR0_EL1_CRC32 1178 #define ARMV8_ID_AA64ISAR0_EL1_CRC32_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_CRC32) >> 16)1177 #define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1178 #define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16 1179 1179 /** No CRC32 instructions implemented. */ 1180 1180 # define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0 … … 1182 1182 # define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1 1183 1183 /** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */ 1184 #define ARMV8_ID_AA64ISAR0_EL1_ATOMIC 1185 #define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_ATOMIC) >> 20)1184 #define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1185 #define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20 1186 1186 /** No Atomic instructions implemented. */ 1187 1187 # define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0 … … 1189 1189 # define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2 1190 1190 /** Bit 24 - 27 - Indicates support for TME instructions. */ 1191 #define ARMV8_ID_AA64ISAR0_EL1_TME 1192 #define ARMV8_ID_AA64ISAR0_EL1_TME_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_TME) >> 24)1191 #define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1192 #define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24 1193 1193 /** TME instructions are not implemented. */ 1194 1194 # define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0 … … 1196 1196 # define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1 1197 1197 /** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */ 1198 #define ARMV8_ID_AA64ISAR0_EL1_RDM 1199 #define ARMV8_ID_AA64ISAR0_EL1_RDM_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_RDM) >> 28)1198 #define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1199 #define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28 1200 1200 /** No RDMA instructions implemented. */ 1201 1201 # define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0 1202 1202 /** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */ 1203 # define ARMV8_ID_AA64ISAR0_EL1_R AS_SUPPORTED 11203 # define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1 1204 1204 /** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */ 1205 #define ARMV8_ID_AA64ISAR0_EL1_SHA3 1206 #define ARMV8_ID_AA64ISAR0_EL1_SHA3_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SHA3) >> 32)1205 #define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1206 #define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32 1207 1207 /** No SHA3 instructions implemented. */ 1208 1208 # define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0 … … 1210 1210 # define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1 1211 1211 /** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */ 1212 #define ARMV8_ID_AA64ISAR0_EL1_SM3 1213 #define ARMV8_ID_AA64ISAR0_EL1_SM3_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SM3) >> 36)1212 #define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1213 #define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36 1214 1214 /** No SM3 instructions implemented. */ 1215 1215 # define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0 … … 1217 1217 # define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1 1218 1218 /** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */ 1219 #define ARMV8_ID_AA64ISAR0_EL1_SM4 1220 #define ARMV8_ID_AA64ISAR0_EL1_SM4_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_SM4) >> 40)1219 #define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1220 #define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40 1221 1221 /** No SM4 instructions implemented. */ 1222 1222 # define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0 … … 1224 1224 # define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1 1225 1225 /** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */ 1226 #define ARMV8_ID_AA64ISAR0_EL1_DP 1227 #define ARMV8_ID_AA64ISAR0_EL1_DP_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_DP) >> 44)1226 #define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1227 #define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44 1228 1228 /** No Dot Product instructions implemented. */ 1229 1229 # define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0 … … 1231 1231 # define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1 1232 1232 /** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */ 1233 #define ARMV8_ID_AA64ISAR0_EL1_FHM 1234 #define ARMV8_ID_AA64ISAR0_EL1_FHM_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_DIT) >> 48)1233 #define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1234 #define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48 1235 1235 /** FMLAL and FMLSL instructions are not implemented. */ 1236 1236 # define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0 … … 1238 1238 # define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1 1239 1239 /** Bit 52 - 55 - Indicates support for flag manipulation instructions. */ 1240 #define ARMV8_ID_AA64ISAR0_EL1_TS 1241 #define ARMV8_ID_AA64ISAR0_EL1_TS_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_TS) >> 52)1240 #define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1241 #define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52 1242 1242 /** No flag manipulation instructions implemented. */ 1243 1243 # define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0 … … 1247 1247 # define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2 1248 1248 /** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */ 1249 #define ARMV8_ID_AA64ISAR0_EL1_TLB 1250 #define ARMV8_ID_AA64ISAR0_EL1_TLB_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_TLB) >> 56)1249 #define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1250 #define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56 1251 1251 /** Outer Sahreable and TLB range maintenance instructions are not implemented. */ 1252 1252 # define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0 … … 1256 1256 # define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2 1257 1257 /** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */ 1258 #define ARMV8_ID_AA64ISAR0_EL1_RNDR 1259 #define ARMV8_ID_AA64ISAR0_EL1_RNDR_ GET(a_IdAa64Isar0El1) (((a_IdAa64Isar0El1) & ARMV8_ID_AA64ISAR0_EL1_RNDR) >> 60)1258 #define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1259 #define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60 1260 1260 /** No Random Number instructions implemented. */ 1261 1261 # define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0 … … 1268 1268 * @{ */ 1269 1269 /** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */ 1270 #define ARMV8_ID_AA64ISAR1_EL1_DPB 1271 #define ARMV8_ID_AA64ISAR1_EL1_DPB_ GET(a_IdAa64Isar1El1) ((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_DPB)1270 #define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1271 #define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0 1272 1272 /** DC CVAP not supported. */ 1273 1273 # define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0 … … 1277 1277 # define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2 1278 1278 /** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */ 1279 #define ARMV8_ID_AA64ISAR1_EL1_APA 1280 #define ARMV8_ID_AA64ISAR1_EL1_APA_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_APA) >> 4)1279 #define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1280 #define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4 1281 1281 /** Address Authentication using the QARMA5 algorithm is not implemented. */ 1282 1282 # define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0 … … 1292 1292 # define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5 1293 1293 /** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */ 1294 #define ARMV8_ID_AA64ISAR1_EL1_API 1295 #define ARMV8_ID_AA64ISAR1_EL1_API_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_API) >> 8)1294 #define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1295 #define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8 1296 1296 /** Address Authentication using the QARMA5 algorithm is not implemented. */ 1297 1297 # define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0 … … 1307 1307 # define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5 1308 1308 /** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */ 1309 #define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS 1310 #define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_FJCVTZS) >> 12)1309 #define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1310 #define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12 1311 1311 /** No FJCVTZS instruction implemented. */ 1312 1312 # define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0 … … 1314 1314 # define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1 1315 1315 /** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */ 1316 #define ARMV8_ID_AA64ISAR1_EL1_FCMA 1317 #define ARMV8_ID_AA64ISAR1_EL1_FCMA_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_FCMA) >> 16)1316 #define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1317 #define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16 1318 1318 /** No FCMLA and FCADD instructions implemented. */ 1319 1319 # define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0 … … 1321 1321 # define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1 1322 1322 /** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */ 1323 #define ARMV8_ID_AA64ISAR1_EL1_LRCPC 1324 #define ARMV8_ID_AA64ISAR1_EL1_LRCPC_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_LRCPC) >> 20)1323 #define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1324 #define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 1325 1325 /** No RCpc instructions implemented. */ 1326 1326 # define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0 1327 1327 /** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */ 1328 1328 # define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1 1329 /** The no ffset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */1329 /** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */ 1330 1330 # define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2 1331 1331 /** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1332 #define ARMV8_ID_AA64ISAR1_EL1_GPA 1333 #define ARMV8_ID_AA64ISAR1_EL1_GPA_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_GPA) >> 24)1332 #define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1333 #define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24 1334 1334 /** Generic Authentication using the QARMA5 algorithm is not implemented. */ 1335 1335 # define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0 … … 1337 1337 # define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1 1338 1338 /** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1339 #define ARMV8_ID_AA64ISAR1_EL1_GPI 1340 #define ARMV8_ID_AA64ISAR1_EL1_GPI_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_GPI) >> 28)1339 #define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1340 #define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28 1341 1341 /** Generic Authentication using an implementation defined algorithm is not implemented. */ 1342 1342 # define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0 … … 1344 1344 # define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1 1345 1345 /** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */ 1346 #define ARMV8_ID_AA64ISAR1_EL1_FRINTTS 1347 #define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_FRINTTS) >> 32)1346 #define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1347 #define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 1348 1348 /** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */ 1349 1349 # define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0 … … 1351 1351 # define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1 1352 1352 /** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */ 1353 #define ARMV8_ID_AA64ISAR1_EL1_SB 1354 #define ARMV8_ID_AA64ISAR1_EL1_SB_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_SB) >> 36)1353 #define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1354 #define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36 1355 1355 /** No SB instructions implemented. */ 1356 1356 # define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0 … … 1358 1358 # define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1 1359 1359 /** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */ 1360 #define ARMV8_ID_AA64ISAR1_EL1_SPECRES 1361 #define ARMV8_ID_AA64ISAR1_EL1_SPECRES_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_SPECRES) >> 40)1360 #define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1361 #define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 1362 1362 /** Prediction invalidation instructions are not implemented. */ 1363 1363 # define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0 … … 1365 1365 # define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1 1366 1366 /** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */ 1367 #define ARMV8_ID_AA64ISAR1_EL1_BF16 1368 #define ARMV8_ID_AA64ISAR1_EL1_BF16_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_DP) >> 44)1367 #define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1368 #define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44 1369 1369 /** BFloat16 instructions are not implemented. */ 1370 1370 # define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0 … … 1374 1374 # define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2 1375 1375 /** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */ 1376 #define ARMV8_ID_AA64ISAR1_EL1_DGH 1377 #define ARMV8_ID_AA64ISAR1_EL1_DGH_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_DGH) >> 48)1376 #define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1377 #define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48 1378 1378 /** Data Gathering Hint instructions are not implemented. */ 1379 1379 # define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0 … … 1381 1381 # define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1 1382 1382 /** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */ 1383 #define ARMV8_ID_AA64ISAR1_EL1_I8MM 1384 #define ARMV8_ID_AA64ISAR1_EL1_I8MM_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_I8MM) >> 52)1383 #define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1384 #define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52 1385 1385 /** No Int8 matrix multiplication instructions implemented. */ 1386 1386 # define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0 … … 1388 1388 # define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1 1389 1389 /** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */ 1390 #define ARMV8_ID_AA64ISAR1_EL1_XS 1391 #define ARMV8_ID_AA64ISAR1_EL1_XS_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_XS) >> 56)1390 #define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1391 #define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56 1392 1392 /** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */ 1393 1393 # define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0 … … 1395 1395 # define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1 1396 1396 /** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */ 1397 #define ARMV8_ID_AA64ISAR1_EL1_LS64 1398 #define ARMV8_ID_AA64ISAR1_EL1_LS64_ GET(a_IdAa64Isar1El1) (((a_IdAa64Isar1El1) & ARMV8_ID_AA64ISAR1_EL1_LS64) >> 60)1397 #define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1398 #define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60 1399 1399 /** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */ 1400 1400 # define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0 … … 1411 1411 * @{ */ 1412 1412 /** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */ 1413 #define ARMV8_ID_AA64ISAR2_EL1_WFXT 1414 #define ARMV8_ID_AA64ISAR2_EL1_WFXT_ GET(a_IdAa64Isar2El1) ((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_WFXT)1413 #define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1414 #define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0 1415 1415 /** WFET and WFIT are not supported. */ 1416 1416 # define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0 1417 1417 /** WFET and WFIT are supported (FEAT_WFxT). */ 1418 1418 # define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2 1419 /** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */1420 #define ARMV8_ID_AA64ISAR2_EL1_RPRES 1421 #define ARMV8_ID_AA64ISAR2_EL1_RPRES_ GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_RPRES) >> 4)1419 /** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */ 1420 #define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1421 #define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4 1422 1422 /** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */ 1423 1423 # define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0 … … 1425 1425 # define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1 1426 1426 /** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */ 1427 #define ARMV8_ID_AA64ISAR2_EL1_GPA3 1428 #define ARMV8_ID_AA64ISAR2_EL1_GPA3_ GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_API) >> 8)1427 #define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1428 #define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8 1429 1429 /** Generic Authentication using the QARMA3 algorithm is not implemented. */ 1430 1430 # define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0 … … 1432 1432 # define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1 1433 1433 /** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */ 1434 #define ARMV8_ID_AA64ISAR2_EL1_APA3 1435 #define ARMV8_ID_AA64ISAR2_EL1_APA3_ GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_APA3) >> 12)1434 #define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1435 #define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12 1436 1436 /** Address Authentication using the QARMA3 algorithm is not implemented. */ 1437 1437 # define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0 … … 1447 1447 # define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5 1448 1448 /** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */ 1449 #define ARMV8_ID_AA64ISAR2_EL1_MOPS 1450 #define ARMV8_ID_AA64ISAR2_EL1_MOPS_ GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_MOPS) >> 16)1449 #define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1450 #define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16 1451 1451 /** No Memory Copy and Memory Set instructions implemented. */ 1452 1452 # define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0 … … 1454 1454 # define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1 1455 1455 /** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */ 1456 #define ARMV8_ID_AA64ISAR2_EL1_BC 1457 #define ARMV8_ID_AA64ISAR2_EL1_BC_ GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_BC) >> 20)1456 #define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1457 #define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20 1458 1458 /** BC instruction is not implemented. */ 1459 1459 # define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0 1460 1460 /** BC instruction is implemented (FEAT_HBC). */ 1461 1461 # define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1 1462 /** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */1463 #define ARMV8_ID_AA64ISAR2_EL1_PACFRAC 1464 #define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_ GET(a_IdAa64Isar2El1) (((a_IdAa64Isar2El1) & ARMV8_ID_AA64ISAR2_EL1_PACFRAC) >> 24)1462 /** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */ 1463 #define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1464 #define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24 1465 1465 /** ConstPACField() returns FALSE. */ 1466 1466 # define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0 … … 1474 1474 * @{ */ 1475 1475 /** Bit 0 - 3 - EL0 Exception level handling. */ 1476 #define ARMV8_ID_AA64PFR0_EL1_EL0 1477 #define ARMV8_ID_AA64PFR0_EL1_EL0_ GET(a_IdAa64Pfr0El1) ((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL0)1476 #define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1477 #define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0 1478 1478 /** EL0 can be executed in AArch64 state only. */ 1479 1479 # define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1 … … 1481 1481 # define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2 1482 1482 /** Bit 4 - 7 - EL1 Exception level handling. */ 1483 #define ARMV8_ID_AA64PFR0_EL1_EL1 1484 #define ARMV8_ID_AA64PFR0_EL1_EL1_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL1) >> 4)1483 #define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1484 #define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4 1485 1485 /** EL1 can be executed in AArch64 state only. */ 1486 1486 # define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1 … … 1488 1488 # define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2 1489 1489 /** Bit 8 - 11 - EL2 Exception level handling. */ 1490 #define ARMV8_ID_AA64PFR0_EL1_EL2 1491 #define ARMV8_ID_AA64PFR0_EL1_EL2_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL2) >> 8)1490 #define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1491 #define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8 1492 1492 /** EL2 is not implemented. */ 1493 1493 # define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0 … … 1497 1497 # define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2 1498 1498 /** Bit 12 - 15 - EL3 Exception level handling. */ 1499 #define ARMV8_ID_AA64PFR0_EL1_EL3 1500 #define ARMV8_ID_AA64PFR0_EL1_EL3_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL3) >> 12)1499 #define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1500 #define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12 1501 1501 /** EL3 is not implemented. */ 1502 1502 # define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0 … … 1506 1506 # define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2 1507 1507 /** Bit 16 - 19 - Floating-point support. */ 1508 #define ARMV8_ID_AA64PFR0_EL1_FP 1509 #define ARMV8_ID_AA64PFR0_EL1_FP_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_EL3) >> 16)1508 #define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1509 #define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16 1510 1510 /** Floating-point is implemented and support single and double precision. */ 1511 1511 # define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0 … … 1515 1515 # define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf 1516 1516 /** Bit 20 - 23 - Advanced SIMD support. */ 1517 #define ARMV8_ID_AA64PFR0_EL1_ADVSIMD 1518 #define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_ADVSIMD) >> 20)1517 #define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1518 #define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20 1519 1519 /** Advanced SIMD is implemented and support single and double precision. */ 1520 1520 # define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0 … … 1524 1524 # define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf 1525 1525 /** Bit 24 - 27 - System register GIC CPU interface support. */ 1526 #define ARMV8_ID_AA64PFR0_EL1_GIC 1527 #define ARMV8_ID_AA64PFR0_EL1_GIC_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_GIC) >> 24)1526 #define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1527 #define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24 1528 1528 /** GIC CPU interface system registers are not implemented. */ 1529 1529 # define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0 … … 1533 1533 # define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3 1534 1534 /** Bit 28 - 31 - RAS Extension version. */ 1535 #define ARMV8_ID_AA64PFR0_EL1_RAS 1536 #define ARMV8_ID_AA64PFR0_EL1_RAS_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_RAS) >> 28)1535 #define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1536 #define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28 1537 1537 /** No RAS extension. */ 1538 1538 # define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0 … … 1542 1542 # define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2 1543 1543 /** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */ 1544 #define ARMV8_ID_AA64PFR0_EL1_SVE 1545 #define ARMV8_ID_AA64PFR0_EL1_SVE_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_SVE) >> 32)1544 #define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1545 #define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32 1546 1546 /** SVE is not supported. */ 1547 1547 # define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0 … … 1549 1549 # define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1 1550 1550 /** Bit 36 - 39 - Secure EL2 support. */ 1551 #define ARMV8_ID_AA64PFR0_EL1_SEL2 1552 #define ARMV8_ID_AA64PFR0_EL1_SEL2_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_SEL2) >> 36)1551 #define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1552 #define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36 1553 1553 /** Secure EL2 is not supported. */ 1554 1554 # define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0 … … 1556 1556 # define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1 1557 1557 /** Bit 40 - 43 - MPAM support. */ 1558 #define ARMV8_ID_AA64PFR0_EL1_MPAM 1559 #define ARMV8_ID_AA64PFR0_EL1_MPAM_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_MPAM) >> 40)1558 #define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1559 #define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40 1560 1560 /** MPAM extension major version number is 0. */ 1561 1561 # define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0 … … 1563 1563 # define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1 1564 1564 /** Bit 44 - 47 - Activity Monitor Extension support. */ 1565 #define ARMV8_ID_AA64PFR0_EL1_AMU 1566 #define ARMV8_ID_AA64PFR0_EL1_AMU_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_AMU) >> 44)1565 #define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1566 #define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44 1567 1567 /** Activity Monitor extension is not implemented. */ 1568 1568 # define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0 … … 1572 1572 # define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2 1573 1573 /** Bit 48 - 51 - Data Independent Timing support. */ 1574 #define ARMV8_ID_AA64PFR0_EL1_DIT 1575 #define ARMV8_ID_AA64PFR0_EL1_DIT_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_DIT) >> 48)1574 #define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1575 #define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48 1576 1576 /** AArch64 does not guarantee constant execution time of any instructions. */ 1577 1577 # define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0 … … 1579 1579 # define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1 1580 1580 /** Bit 52 - 55 - Realm Management Extension support. */ 1581 #define ARMV8_ID_AA64PFR0_EL1_RME 1582 #define ARMV8_ID_AA64PFR0_EL1_RME_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_RME) >> 52)1581 #define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1582 #define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52 1583 1583 /** Realm Management Extension not implemented. */ 1584 1584 # define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0 … … 1586 1586 # define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1 1587 1587 /** Bit 56 - 59 - Speculative use out of context branch targets support. */ 1588 #define ARMV8_ID_AA64PFR0_EL1_CSV2 1589 #define ARMV8_ID_AA64PFR0_EL1_CSV2_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_CSV2) >> 56)1588 #define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1589 #define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56 1590 1590 /** Implementation does not disclose whether FEAT_CSV2 is implemented. */ 1591 1591 # define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0 … … 1597 1597 # define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3 1598 1598 /** Bit 60 - 63 - Speculative use of faulting data support. */ 1599 #define ARMV8_ID_AA64PFR0_EL1_CSV3 1600 #define ARMV8_ID_AA64PFR0_EL1_CSV3_ GET(a_IdAa64Pfr0El1) (((a_IdAa64Pfr0El1) & ARMV8_ID_AA64PFR0_EL1_CSV3) >> 60)1599 #define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1600 #define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60 1601 1601 /** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */ 1602 1602 # define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0 … … 1609 1609 * @{ */ 1610 1610 /** Bit 0 - 3 - Branch Target Identification support. */ 1611 #define ARMV8_ID_AA64PFR1_EL1_BT 1612 #define ARMV8_ID_AA64PFR1_EL1_BT_ GET(a_IdAa64Pfr1El1) ((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_BT)1611 #define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1612 #define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0 1613 1613 /** The Branch Target Identification mechanism is not implemented. */ 1614 1614 # define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0 … … 1616 1616 # define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1 1617 1617 /** Bit 4 - 7 - Speculative Store Bypassing control support. */ 1618 #define ARMV8_ID_AA64PFR1_EL1_SSBS 1619 #define ARMV8_ID_AA64PFR1_EL1_SSBS_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_SSBS) >> 4)1618 #define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1619 #define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4 1620 1620 /** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */ 1621 1621 # define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0 … … 1626 1626 # define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2 1627 1627 /** Bit 8 - 11 - Memory Tagging Extension support. */ 1628 #define ARMV8_ID_AA64PFR1_EL1_MTE 1629 #define ARMV8_ID_AA64PFR1_EL1_MTE_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_MTE) >> 8)1628 #define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1629 #define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8 1630 1630 /** MTE is not implemented. */ 1631 1631 # define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0 … … 1637 1637 # define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3 1638 1638 /** Bit 12 - 15 - RAS Extension fractional field. */ 1639 #define ARMV8_ID_AA64PFR1_EL1_RASFRAC 1640 #define ARMV8_ID_AA64PFR1_EL1_RASFRAC_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_RASFRAC) >> 12)1639 #define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1640 #define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12 1641 1641 /** RAS Extension is implemented. */ 1642 1642 # define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0 … … 1644 1644 # define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1 1645 1645 /** Bit 16 - 19 - MPAM minor version number. */ 1646 #define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC 1647 #define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_MPAMFRAC) >> 16)1646 #define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1647 #define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16 1648 1648 /** The minor version of number of the MPAM extension is 0. */ 1649 1649 # define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0 … … 1652 1652 /* Bit 20 - 23 - Reserved. */ 1653 1653 /** Bit 24 - 27 - Scalable Matrix Extension support. */ 1654 #define ARMV8_ID_AA64PFR1_EL1_SME 1655 #define ARMV8_ID_AA64PFR1_EL1_SME_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_SME) >> 24)1654 #define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1655 #define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24 1656 1656 /** Scalable Matrix Extensions are not implemented. */ 1657 1657 # define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0 … … 1661 1661 # define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2 1662 1662 /** Bit 28 - 31 - Random Number trap to EL3 support. */ 1663 #define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP 1664 #define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_RNDRTRAP) >> 28)1663 #define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1664 #define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28 1665 1665 /** Trapping of RNDR and RNDRRS to EL3 is not supported. */ 1666 1666 # define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0 … … 1668 1668 # define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1 1669 1669 /** Bit 32 - 35 - CSV2 fractional field. */ 1670 #define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC 1671 #define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_CSV2FRAC) >> 32)1670 #define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1671 #define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32 1672 1672 /** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */ 1673 1673 # define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0 … … 1677 1677 # define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2 1678 1678 /** Bit 36 - 39 - Non-maskable Interrupt support. */ 1679 #define ARMV8_ID_AA64PFR1_EL1_NMI 1680 #define ARMV8_ID_AA64PFR1_EL1_NMI_ GET(a_IdAa64Pfr1El1) (((a_IdAa64Pfr1El1) & ARMV8_ID_AA64PFR1_EL1_NMI) >> 36)1679 #define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1680 #define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36 1681 1681 /** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */ 1682 1682 # define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0 … … 1689 1689 * @{ */ 1690 1690 /** Bit 0 - 3 - Physical Address range supported. */ 1691 #define ARMV8_ID_AA64MMFR0_EL1_PARANGE 1692 #define ARMV8_ID_AA64MMFR0_EL1_PARANGE_ GET(a_IdAa64Mmfr0El1) ((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_PARANGE)1691 #define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1692 #define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0 1693 1693 /** Physical Address range is 32 bits, 4GiB. */ 1694 1694 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0 … … 1706 1706 # define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6 1707 1707 /** Bit 4 - 7 - Number of ASID bits. */ 1708 #define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS 1709 #define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_ASIDBITS) >> 4)1708 #define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1709 #define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4 1710 1710 /** ASID bits is 8. */ 1711 1711 # define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0 … … 1713 1713 # define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2 1714 1714 /** Bit 8 - 11 - Indicates support for mixed-endian configuration. */ 1715 #define ARMV8_ID_AA64MMFR0_EL1_BIGEND 1716 #define ARMV8_ID_AA64MMFR0_EL1_BIGEND_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_BIGEND) >> 8)1715 #define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1716 #define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8 1717 1717 /** No mixed-endian support. */ 1718 1718 # define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0 … … 1720 1720 # define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1 1721 1721 /** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */ 1722 #define ARMV8_ID_AA64MMFR0_EL1_SNSMEM 1723 #define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_SNSMEM) >> 12)1722 #define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1723 #define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12 1724 1724 /** No distinction between Secure and Non-secure Memory supported. */ 1725 1725 # define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0 … … 1727 1727 # define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1 1728 1728 /** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */ 1729 #define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0 1730 #define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0) >> 16)1729 #define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1730 #define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16 1731 1731 /** No mixed-endian support at EL0. */ 1732 1732 # define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0 … … 1734 1734 # define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1 1735 1735 /** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */ 1736 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16 1737 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN16) >> 20)1736 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1737 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20 1738 1738 /** 16KiB granule size not supported. */ 1739 1739 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0 … … 1743 1743 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2 1744 1744 /** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */ 1745 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64 1746 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN64) >> 24)1745 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1746 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24 1747 1747 /** 64KiB granule supported. */ 1748 1748 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0 … … 1750 1750 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf 1751 1751 /** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */ 1752 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4 1753 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN4) >> 28)1752 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1753 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28 1754 1754 /** 4KiB granule supported. */ 1755 1755 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0 … … 1759 1759 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf 1760 1760 /** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */ 1761 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2 1762 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2) >> 32)1761 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1762 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32 1763 1763 /** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */ 1764 1764 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0 … … 1770 1770 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3 1771 1771 /** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */ 1772 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2 1773 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2) >> 36)1772 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1773 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36 1774 1774 /** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */ 1775 1775 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0 … … 1779 1779 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2 1780 1780 /** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */ 1781 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2 1782 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2) >> 40)1781 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1782 #define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40 1783 1783 /** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */ 1784 1784 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0 … … 1790 1790 # define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3 1791 1791 /** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */ 1792 #define ARMV8_ID_AA64MMFR0_EL1_EXS 1793 #define ARMV8_ID_AA64MMFR0_EL1_EXS_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_EXS) >> 44)1792 #define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1793 #define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44 1794 1794 /** All exception entries and exits are context synchronization events. */ 1795 1795 # define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0 … … 1798 1798 /* Bit 48 - 55 - Reserved. */ 1799 1799 /** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */ 1800 #define ARMV8_ID_AA64MMFR0_EL1_FGT 1801 #define ARMV8_ID_AA64MMFR0_EL1_FGT_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_FGT) >> 56)1800 #define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1801 #define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56 1802 1802 /** Fine-grained trap controls are not implemented. */ 1803 1803 # define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0 … … 1805 1805 # define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1 1806 1806 /** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */ 1807 #define ARMV8_ID_AA64MMFR0_EL1_ECV 1808 #define ARMV8_ID_AA64MMFR0_EL1_ECV_ GET(a_IdAa64Mmfr0El1) (((a_IdAa64Mmfr0El1) & ARMV8_ID_AA64MMFR0_EL1_ECV) >> 60)1807 #define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 1808 #define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60 1809 1809 /** Enhanced Counter Virtualization is not implemented. */ 1810 1810 # define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0 … … 1819 1819 * @{ */ 1820 1820 /** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */ 1821 #define ARMV8_ID_AA64MMFR1_EL1_HAFDBS 1822 #define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_ GET(a_IdAa64Mmfr1El1) ((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_HAFDBS)1821 #define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1822 #define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0 1823 1823 /** Hardware update of the Access flag and dirty state are not supported. */ 1824 1824 # define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0 … … 1828 1828 # define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2 1829 1829 /** Bit 4 - 7 - EL1 Exception level handling. */ 1830 #define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS 1831 #define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_VMIDBITS) >> 4)1830 #define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1831 #define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4 1832 1832 /** VMID bits is 8. */ 1833 1833 # define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0 … … 1835 1835 # define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2 1836 1836 /** Bit 8 - 11 - Virtualization Host Extensions support. */ 1837 #define ARMV8_ID_AA64MMFR1_EL1_VHE 1838 #define ARMV8_ID_AA64MMFR1_EL1_VHE_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_VHE) >> 8)1837 #define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1838 #define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8 1839 1839 /** Virtualization Host Extensions are not supported. */ 1840 1840 # define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0 … … 1842 1842 # define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1 1843 1843 /** Bit 12 - 15 - Hierarchical Permission Disables. */ 1844 #define ARMV8_ID_AA64MMFR1_EL1_HPDS 1845 #define ARMV8_ID_AA64MMFR1_EL1_HPDS_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_HPDS) >> 12)1844 #define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1845 #define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12 1846 1846 /** Disabling of hierarchical controls not supported. */ 1847 1847 # define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0 … … 1851 1851 # define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2 1852 1852 /** Bit 16 - 19 - LORegions support. */ 1853 #define ARMV8_ID_AA64MMFR1_EL1_LO 1854 #define ARMV8_ID_AA64MMFR1_EL1_LO_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_LO) >> 16)1853 #define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1854 #define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16 1855 1855 /** LORegions not supported. */ 1856 1856 # define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0 … … 1858 1858 # define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1 1859 1859 /** Bit 20 - 23 - Privileged Access Never support. */ 1860 #define ARMV8_ID_AA64MMFR1_EL1_PAN 1861 #define ARMV8_ID_AA64MMFR1_EL1_PAN_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_PAN) >> 20)1860 #define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1861 #define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20 1862 1862 /** PAN not supported. */ 1863 1863 # define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0 … … 1869 1869 # define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3 1870 1870 /** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */ 1871 #define ARMV8_ID_AA64MMFR1_EL1_SPECSEI 1872 #define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_SPECSEI) >> 24)1871 #define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1872 #define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24 1873 1873 /** The PE never generates an SError interrupt due to an External abort on a speculative read. */ 1874 1874 # define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0 … … 1876 1876 # define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1 1877 1877 /** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */ 1878 #define ARMV8_ID_AA64MMFR1_EL1_XNX 1879 #define ARMV8_ID_AA64MMFR1_EL1_XNX_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_XNX) >> 28)1878 #define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1879 #define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28 1880 1880 /** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */ 1881 1881 # define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0 … … 1883 1883 # define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1 1884 1884 /** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */ 1885 #define ARMV8_ID_AA64MMFR1_EL1_TWED 1886 #define ARMV8_ID_AA64MMFR1_EL1_TWED_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_TWED) >> 32)1885 #define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1886 #define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32 1887 1887 /** Configurable delayed trapping of WFE is not supported. */ 1888 1888 # define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0 … … 1890 1890 # define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1 1891 1891 /** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */ 1892 #define ARMV8_ID_AA64MMFR1_EL1_ETS 1893 #define ARMV8_ID_AA64MMFR1_EL1_ETS_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_ETS) >> 36)1892 #define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 1893 #define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36 1894 1894 /** Enhanced Translation Synchronization is not supported. */ 1895 1895 # define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0 … … 1897 1897 # define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1 1898 1898 /** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */ 1899 #define ARMV8_ID_AA64MMFR1_EL1_HCX 1900 #define ARMV8_ID_AA64MMFR1_EL1_HCX_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_MPAM) >> 40)1899 #define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 1900 #define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40 1901 1901 /** HCRX_EL2 and its associated EL3 trap are not supported. */ 1902 1902 # define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0 … … 1904 1904 # define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1 1905 1905 /** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */ 1906 #define ARMV8_ID_AA64MMFR1_EL1_AFP 1907 #define ARMV8_ID_AA64MMFR1_EL1_AFP_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_AFP) >> 44)1906 #define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 1907 #define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44 1908 1908 /** The FPCR.{AH,FIZ,NEP} fields are not supported. */ 1909 1909 # define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0 … … 1911 1911 # define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1 1912 1912 /** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */ 1913 #define ARMV8_ID_AA64MMFR1_EL1_NTLBPA 1914 #define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_NTLBPA) >> 48)1913 #define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 1914 #define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48 1915 1915 /** The intermediate caching of translation table walks might include non-coherent physical translation caches. */ 1916 1916 # define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0 … … 1918 1918 # define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1 1919 1919 /** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */ 1920 #define ARMV8_ID_AA64MMFR1_EL1_TIDCP1 1921 #define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_TIDCP1_GET) >> 52)1920 #define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 1921 #define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52 1922 1922 /** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */ 1923 1923 # define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0 … … 1925 1925 # define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1 1926 1926 /** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */ 1927 #define ARMV8_ID_AA64MMFR1_EL1_CMOW 1928 #define ARMV8_ID_AA64MMFR1_EL1_CMOW_ GET(a_IdAa64Mmfr1El1) (((a_IdAa64Mmfr1El1) & ARMV8_ID_AA64MMFR1_EL1_CMOW) >> 56)1927 #define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 1928 #define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56 1929 1929 /** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */ 1930 1930 # define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
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