- Timestamp:
- Sep 20, 2023 9:03:53 AM (15 months ago)
- File:
-
- 1 edited
-
trunk/include/iprt/armv8.h (modified) (1 diff)
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- Unmodified
- Added
- Removed
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trunk/include/iprt/armv8.h
r101102 r101185 1935 1935 1936 1936 1937 /** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2. 1938 * @{ */ 1939 /** Bit 0 - 3 - Indicates support for Common not Private translations. */ 1940 #define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 1941 #define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0 1942 /** Common not Private translations are not supported. */ 1943 # define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0 1944 /** Support for Common not Private translations (FEAT_TTNCP). */ 1945 # define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1 1946 /** Bit 4 - 7 - Indicates support for User Access Override. */ 1947 #define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 1948 #define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4 1949 /** User Access Override is not supported. */ 1950 # define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0 1951 /** User Access Override is supported (FEAT_UAO). */ 1952 # define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1 1953 /** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */ 1954 #define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 1955 #define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8 1956 /** LSMAOE and nTLSMD bits are not supported. */ 1957 # define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0 1958 /** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */ 1959 # define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1 1960 /** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */ 1961 #define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 1962 #define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12 1963 /** IESB bit is not supported. */ 1964 # define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0 1965 /** IESB bit is supported (FEAT_IESB). */ 1966 # define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1 1967 /** Bit 16 - 19 - Indicates support for larger virtual address. */ 1968 #define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19)) 1969 #define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16 1970 /** Virtual address range is 48 bits. */ 1971 # define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0 1972 /** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */ 1973 # define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1 1974 /** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */ 1975 #define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 1976 #define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20 1977 /** CCSIDR_EL1 register format is 32-bit. */ 1978 # define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0 1979 /** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */ 1980 # define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1 1981 /** Bit 24 - 27 - Indicates support for nested virtualization. */ 1982 #define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27)) 1983 #define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24 1984 /** Nested virtualization is not supported. */ 1985 # define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0 1986 /** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */ 1987 # define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1 1988 /** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */ 1989 # define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2 1990 /** Bit 28 - 31 - Indicates support for small translation tables. */ 1991 #define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 1992 #define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28 1993 /** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */ 1994 # define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0 1995 /** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */ 1996 # define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1 1997 /** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */ 1998 #define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 1999 #define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32 2000 /** Unaligned single-copy atomicity and atomic functions are not supported. */ 2001 # define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0 2002 /** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */ 2003 # define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1 2004 /** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */ 2005 #define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 2006 #define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36 2007 /** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */ 2008 # define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0 2009 /** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */ 2010 # define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1 2011 /** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */ 2012 #define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 2013 #define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40 2014 /** HCR_EL2.FWB bit is not supported. */ 2015 # define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0 2016 /** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */ 2017 # define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1 2018 /* Bit 44 - 47 - Reserved. */ 2019 /** Bit 48 - 51 - Indicates support for TTL field in address operations. */ 2020 #define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 2021 #define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48 2022 /** TLB maintenance instructions by address have bits [47:44] Res0. */ 2023 # define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0 2024 /** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */ 2025 # define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1 2026 /** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when 2027 * changing block size for a translation. */ 2028 #define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 2029 #define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52 2030 /** Level 0 support for changing block size is supported (FEAT_BBM). */ 2031 # define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0 2032 /** Level 1 support for changing block size is supported (FEAT_BBM). */ 2033 # define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1 2034 /** Level 2 support for changing block size is supported (FEAT_BBM). */ 2035 # define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2 2036 /** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */ 2037 #define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59)) 2038 #define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56 2039 /** Enhanced Virtualization Traps are not supported. */ 2040 # define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0 2041 /** Enhanced Virtualization Traps are supported (FEAT_EVT). */ 2042 # define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1 2043 /** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */ 2044 # define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2 2045 /** Bit 60 - 63 - Indicates support for E0PDx mechanism. */ 2046 #define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 2047 #define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60 2048 /** E0PDx mechanism is not supported. */ 2049 # define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0 2050 /** E0PDx mechanism is supported (FEAT_E0PD). */ 2051 # define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1 2052 /** @} */ 2053 2054 2055 /** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0. 2056 * @{ */ 2057 /** Bit 0 - 3 - Indicates the Debug Architecture version supported. */ 2058 #define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3)) 2059 #define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0 2060 /** Armv8 debug architecture version. */ 2061 # define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6 2062 /** Armv8 debug architecture version with virtualization host extensions. */ 2063 # define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7 2064 /** Armv8.2 debug architecture version (FEAT_Debugv8p2). */ 2065 # define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8 2066 /** Armv8.4 debug architecture version (FEAT_Debugv8p4). */ 2067 # define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9 2068 /** Armv8.8 debug architecture version (FEAT_Debugv8p8). */ 2069 # define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10 2070 /** Bit 4 - 7 - Indicates trace support. */ 2071 #define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)) 2072 #define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4 2073 /** Trace unit System registers not implemented. */ 2074 # define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0 2075 /** Trace unit System registers supported. */ 2076 # define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1 2077 /** Bit 8 - 11 - Performance Monitors Extension version. */ 2078 #define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11)) 2079 #define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8 2080 /** Performance Monitors Extension not supported. */ 2081 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0 2082 /** Performance Monitors Extension v3 supported (FEAT_PMUv3). */ 2083 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1 2084 /** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */ 2085 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4 2086 /** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */ 2087 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5 2088 /** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */ 2089 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6 2090 /** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */ 2091 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7 2092 /** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */ 2093 # define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8 2094 /** Bit 12 - 15 - Number of breakpoints, minus 1. */ 2095 #define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15)) 2096 #define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12 2097 /* Bit 16 - 19 - Reserved 0. */ 2098 /** Bit 20 - 23 - Number of watchpoints, minus 1. */ 2099 #define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)) 2100 #define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20 2101 /* Bit 24 - 27 - Reserved 0. */ 2102 /** Bit 28 - 31 - Number of context-aware breakpoints. */ 2103 #define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31)) 2104 #define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28 2105 /** Bit 32 - 35 - Statistical Profiling Extension version. */ 2106 #define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35)) 2107 #define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32 2108 /** Statistical Profiling Extension not implemented. */ 2109 # define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0 2110 /** Statistical Profiling Extension supported (FEAT_SPE). */ 2111 # define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1 2112 /** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */ 2113 # define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2 2114 /** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */ 2115 # define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3 2116 /** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */ 2117 # define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4 2118 /** Bit 36 - 39 - OS Double Lock implemented. */ 2119 #define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39)) 2120 #define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36 2121 /** OS Double Lock is not implemented. */ 2122 # define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf 2123 /** OS Double Lock is supported (FEAT_DoubleLock). */ 2124 # define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0 2125 /** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */ 2126 #define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43)) 2127 #define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40 2128 /** Armv8.4 self-hosted Trace Extension not implemented. */ 2129 # define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0 2130 /** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */ 2131 # define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1 2132 /** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */ 2133 #define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47)) 2134 #define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44 2135 /** Trace Buffer Extension is not implemented. */ 2136 # define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0 2137 /** Trace Buffer Extension is supported (FEAT_TRBE). */ 2138 # define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1 2139 /** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */ 2140 #define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51)) 2141 #define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48 2142 /** Multi-threaded PMU extension is not implemented. */ 2143 # define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0 2144 /** Multi-threaded PMU extension is supported (FEAT_MTPMU). */ 2145 # define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1 2146 /** Multi-threaded PMU extension is not implemented. */ 2147 # define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf 2148 /** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */ 2149 #define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55)) 2150 #define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52 2151 /** Branch Record Buffer extension is not implemented. */ 2152 # define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0 2153 /** Branch Record Buffer extension is supported (FEAT_BRBE). */ 2154 # define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1 2155 /** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */ 2156 # define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2 2157 /* Bit 56 - 59 - Reserved. */ 2158 /** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */ 2159 #define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63)) 2160 #define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60 2161 /** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */ 2162 # define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0 2163 /** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */ 2164 # define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1 2165 /** @} */ 2166 1937 2167 /** @} */ 1938 2168
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