Changeset 101246 in vbox

Timestamp:

Sep 22, 2023 11:47:21 PM (14 months ago)

Author:

vboxsync

Message:

iprt/armv8.h,iprt/formats/dwarf.h: Arm register names. bugref:10370

Location:

trunk/include/iprt

Files:

• armv8.h (modified) (1 diff)
• formats/dwarf.h (modified) (2 diffs)

trunk/include/iprt/armv8.h

@@ -52 +52 @@
  */
 
-/** @name The AArch64 register encoding.
+/** @name The AArch64 register encoding - deprecated.
+ *  @deprecated  Use ARMV8_A64_REG_XXX instead.
+ *  @todo correct code and drop these remaining ones.
  * @{ */
 #define ARMV8_AARCH64_REG_X0                        0
-#define ARMV8_AARCH64_REG_W0                        ARMV8_AARCH64_REG_X0
 #define ARMV8_AARCH64_REG_X1                        1
-#define ARMV8_AARCH64_REG_W1                        ARMV8_AARCH64_REG_X1
 #define ARMV8_AARCH64_REG_X2                        2
-#define ARMV8_AARCH64_REG_W2                        ARMV8_AARCH64_REG_X2
 #define ARMV8_AARCH64_REG_X3                        3
-#define ARMV8_AARCH64_REG_W3                        ARMV8_AARCH64_REG_X3
-#define ARMV8_AARCH64_REG_X4                        4
-#define ARMV8_AARCH64_REG_W4                        ARMV8_AARCH64_REG_X4
-#define ARMV8_AARCH64_REG_X5                        5
-#define ARMV8_AARCH64_REG_W5                        ARMV8_AARCH64_REG_X5
-#define ARMV8_AARCH64_REG_X6                        6
-#define ARMV8_AARCH64_REG_W6                        ARMV8_AARCH64_REG_X6
-#define ARMV8_AARCH64_REG_X7                        7
-#define ARMV8_AARCH64_REG_W7                        ARMV8_AARCH64_REG_X7
-#define ARMV8_AARCH64_REG_X8                        8
-#define ARMV8_AARCH64_REG_W8                        ARMV8_AARCH64_REG_X8
-#define ARMV8_AARCH64_REG_X9                        9
-#define ARMV8_AARCH64_REG_W9                        ARMV8_AARCH64_REG_X9
-#define ARMV8_AARCH64_REG_X10                       10
-#define ARMV8_AARCH64_REG_W10                       ARMV8_AARCH64_REG_X10
-#define ARMV8_AARCH64_REG_X11                       11
-#define ARMV8_AARCH64_REG_W11                       ARMV8_AARCH64_REG_X11
-#define ARMV8_AARCH64_REG_X12                       12
-#define ARMV8_AARCH64_REG_W12                       ARMV8_AARCH64_REG_X12
-#define ARMV8_AARCH64_REG_X13                       13
-#define ARMV8_AARCH64_REG_W13                       ARMV8_AARCH64_REG_X13
-#define ARMV8_AARCH64_REG_X14                       14
-#define ARMV8_AARCH64_REG_W14                       ARMV8_AARCH64_REG_X14
-#define ARMV8_AARCH64_REG_X15                       15
-#define ARMV8_AARCH64_REG_W15                       ARMV8_AARCH64_REG_X15
-#define ARMV8_AARCH64_REG_X16                       16
-#define ARMV8_AARCH64_REG_W16                       ARMV8_AARCH64_REG_X16
-#define ARMV8_AARCH64_REG_X17                       17
-#define ARMV8_AARCH64_REG_W17                       ARMV8_AARCH64_REG_X17
-#define ARMV8_AARCH64_REG_X18                       18
-#define ARMV8_AARCH64_REG_W18                       ARMV8_AARCH64_REG_X18
-#define ARMV8_AARCH64_REG_X19                       19
-#define ARMV8_AARCH64_REG_W19                       ARMV8_AARCH64_REG_X19
-#define ARMV8_AARCH64_REG_X20                       20
-#define ARMV8_AARCH64_REG_W20                       ARMV8_AARCH64_REG_X20
-#define ARMV8_AARCH64_REG_X21                       21
-#define ARMV8_AARCH64_REG_W21                       ARMV8_AARCH64_REG_X21
-#define ARMV8_AARCH64_REG_X22                       22
-#define ARMV8_AARCH64_REG_W22                       ARMV8_AARCH64_REG_X22
-#define ARMV8_AARCH64_REG_X23                       23
-#define ARMV8_AARCH64_REG_W23                       ARMV8_AARCH64_REG_X23
-#define ARMV8_AARCH64_REG_X24                       24
-#define ARMV8_AARCH64_REG_W24                       ARMV8_AARCH64_REG_X24
-#define ARMV8_AARCH64_REG_X25                       25
-#define ARMV8_AARCH64_REG_W25                       ARMV8_AARCH64_REG_X25
-#define ARMV8_AARCH64_REG_X26                       26
-#define ARMV8_AARCH64_REG_W26                       ARMV8_AARCH64_REG_X26
-#define ARMV8_AARCH64_REG_X27                       27
-#define ARMV8_AARCH64_REG_W27                       ARMV8_AARCH64_REG_X27
-#define ARMV8_AARCH64_REG_X28                       28
-#define ARMV8_AARCH64_REG_W28                       ARMV8_AARCH64_REG_X28
-#define ARMV8_AARCH64_REG_X29                       29
-#define ARMV8_AARCH64_REG_W29                       ARMV8_AARCH64_REG_X29
-#define ARMV8_AARCH64_REG_X30                       30
-#define ARMV8_AARCH64_REG_W30                       ARMV8_AARCH64_REG_X30
-/** The zero register. */
 #define ARMV8_AARCH64_REG_ZR                        31
 /** @} */
+
+/** @name The AArch64 general purpose register encoding.
+ * @{ */
+#define ARMV8_A64_REG_X0                            0
+#define ARMV8_A64_REG_X1                            1
+#define ARMV8_A64_REG_X2                            2
+#define ARMV8_A64_REG_X3                            3
+#define ARMV8_A64_REG_X4                            4
+#define ARMV8_A64_REG_X5                            5
+#define ARMV8_A64_REG_X6                            6
+#define ARMV8_A64_REG_X7                            7
+#define ARMV8_A64_REG_X8                            8
+#define ARMV8_A64_REG_X9                            9
+#define ARMV8_A64_REG_X10                           10
+#define ARMV8_A64_REG_X11                           11
+#define ARMV8_A64_REG_X12                           12
+#define ARMV8_A64_REG_X13                           13
+#define ARMV8_A64_REG_X14                           14
+#define ARMV8_A64_REG_X15                           15
+#define ARMV8_A64_REG_X16                           16
+#define ARMV8_A64_REG_X17                           17
+#define ARMV8_A64_REG_X18                           18
+#define ARMV8_A64_REG_X19                           19
+#define ARMV8_A64_REG_X20                           20
+#define ARMV8_A64_REG_X21                           21
+#define ARMV8_A64_REG_X22                           22
+#define ARMV8_A64_REG_X23                           23
+#define ARMV8_A64_REG_X24                           24
+#define ARMV8_A64_REG_X25                           25
+#define ARMV8_A64_REG_X26                           26
+#define ARMV8_A64_REG_X27                           27
+#define ARMV8_A64_REG_X28                           28
+#define ARMV8_A64_REG_X29                           29
+#define ARMV8_A64_REG_X30                           30
+/** @} */
+
+/** @name The AArch64 32-bit general purpose register names.
+ * @{ */
+#define ARMV8_A64_REG_W0                            ARMV8_A64_REG_X0
+#define ARMV8_A64_REG_W1                            ARMV8_A64_REG_X1
+#define ARMV8_A64_REG_W2                            ARMV8_A64_REG_X2
+#define ARMV8_A64_REG_W3                            ARMV8_A64_REG_X3
+#define ARMV8_A64_REG_W4                            ARMV8_A64_REG_X4
+#define ARMV8_A64_REG_W5                            ARMV8_A64_REG_X5
+#define ARMV8_A64_REG_W6                            ARMV8_A64_REG_X6
+#define ARMV8_A64_REG_W7                            ARMV8_A64_REG_X7
+#define ARMV8_A64_REG_W8                            ARMV8_A64_REG_X8
+#define ARMV8_A64_REG_W9                            ARMV8_A64_REG_X9
+#define ARMV8_A64_REG_W10                           ARMV8_A64_REG_X10
+#define ARMV8_A64_REG_W11                           ARMV8_A64_REG_X11
+#define ARMV8_A64_REG_W12                           ARMV8_A64_REG_X12
+#define ARMV8_A64_REG_W13                           ARMV8_A64_REG_X13
+#define ARMV8_A64_REG_W14                           ARMV8_A64_REG_X14
+#define ARMV8_A64_REG_W15                           ARMV8_A64_REG_X15
+#define ARMV8_A64_REG_W16                           ARMV8_A64_REG_X16
+#define ARMV8_A64_REG_W17                           ARMV8_A64_REG_X17
+#define ARMV8_A64_REG_W18                           ARMV8_A64_REG_X18
+#define ARMV8_A64_REG_W19                           ARMV8_A64_REG_X19
+#define ARMV8_A64_REG_W20                           ARMV8_A64_REG_X20
+#define ARMV8_A64_REG_W21                           ARMV8_A64_REG_X21
+#define ARMV8_A64_REG_W22                           ARMV8_A64_REG_X22
+#define ARMV8_A64_REG_W23                           ARMV8_A64_REG_X23
+#define ARMV8_A64_REG_W24                           ARMV8_A64_REG_X24
+#define ARMV8_A64_REG_W25                           ARMV8_A64_REG_X25
+#define ARMV8_A64_REG_W26                           ARMV8_A64_REG_X26
+#define ARMV8_A64_REG_W27                           ARMV8_A64_REG_X27
+#define ARMV8_A64_REG_W28                           ARMV8_A64_REG_X28
+#define ARMV8_A64_REG_W29                           ARMV8_A64_REG_X29
+#define ARMV8_A64_REG_W30                           ARMV8_A64_REG_X30
+/** @} */
+
+/** @name The AArch64 register 31.
+ * @note Register 31 typically refers to the zero register, but can also in
+ *       select case (by instruction and opecode field) refer the to stack
+ *       pointer of the current exception level.  ARM typically uses \<Xn|SP\>
+ *       to indicate that register 31 is taken as SP, if just \<Xn\> is used
+ *       31 will be the zero register.
+ * @{ */
+/** The stack pointer. */
+#define ARMV8_A64_REG_SP                            31
+/** The zero register.  Reads as zero, writes ignored. */
+#define ARMV8_A64_REG_XZR                           31
+/** The zero register, the 32-bit register name. */
+#define ARMV8_A64_REG_WZR                           ARMV8_A64_REG_XZR
+/** @} */
+
+/** @name AArch64 register aliases
+ * @{ */
+/** The link register is typically mapped to x30 as that's the default pick of
+ *  the RET instruction. */
+#define ARMV8_A64_REG_LR                            ARMV8_A64_REG_X30
+/** Frame base pointer is typically mapped to x29. */
+#define ARMV8_A64_REG_BP                            ARMV8_A64_REG_X29
+/* @} */
 
 

trunk/include/iprt/formats/dwarf.h

@@ -471 +471 @@
 
 /** @name DWREG_AMD64_XXX - AMD64 register number mappings.
- * @note This for some braindead reason the first 8 GPR are in intel encoding
- *       order, unlike the DWREG_X86_XXX variant.  Utter stupidity.
+ * @note This for some braindead reason the first 8 GPR are NOT in the intel
+ *       encoding order, unlike the DWREG_X86_XXX variant.  Utter stupidity.
  * @{ */
 #define DWREG_AMD64_RAX     0
@@ -539 +539 @@
 /** @} */
 
+
+/** @name DWREG_ARM64_XXX - ARM64 register number mappings.
+ * @{ */
+#define DWREG_ARM64_X0              0
+#define DWREG_ARM64_X1              1
+#define DWREG_ARM64_X2              2
+#define DWREG_ARM64_X3              3
+#define DWREG_ARM64_X4              4
+#define DWREG_ARM64_X5              5
+#define DWREG_ARM64_X6              6
+#define DWREG_ARM64_X7              7
+#define DWREG_ARM64_X8              8
+#define DWREG_ARM64_X9              9
+#define DWREG_ARM64_X10             10
+#define DWREG_ARM64_X11             11
+#define DWREG_ARM64_X12             12
+#define DWREG_ARM64_X13             13
+#define DWREG_ARM64_X14             14
+#define DWREG_ARM64_X15             15
+#define DWREG_ARM64_X16             16
+#define DWREG_ARM64_X17             17
+#define DWREG_ARM64_X18             18
+#define DWREG_ARM64_X19             19
+#define DWREG_ARM64_X20             20
+#define DWREG_ARM64_X21             21
+#define DWREG_ARM64_X22             22
+#define DWREG_ARM64_X23             23
+#define DWREG_ARM64_X24             24
+#define DWREG_ARM64_X25             25
+#define DWREG_ARM64_X26             26
+#define DWREG_ARM64_X27             27
+#define DWREG_ARM64_X28             28
+#define DWREG_ARM64_X29             29
+#define DWREG_ARM64_X30             30
+#define DWREG_ARM64_SP              31
+#define DWREG_ARM64_BP              DWREG_ARM64_X29
+#define DWREG_ARM64_LR              DWREG_ARM64_X30
+#define DWREG_ARM64_PC              32
+#define DWREG_ARM64_ELR_MODE        33
+#define DWREG_ARM64_RA_SIGN_STATE   34
+#define DWREG_ARM64_TPIDRRO_ELO     35
+#define DWREG_ARM64_TPIDR_ELO       36
+#define DWREG_ARM64_TPIDR_EL1       37
+#define DWREG_ARM64_TPIDR_EL2       38
+#define DWREG_ARM64_TPIDR_EL3       39
+/* 40-45 are reserved */
+#define DWREG_ARM64_VG              46
+#define DWREG_ARM64_FFR             47
+#define DWREG_ARM64_P0              48
+#define DWREG_ARM64_P1              49
+#define DWREG_ARM64_P2              50
+#define DWREG_ARM64_P3              51
+#define DWREG_ARM64_P4              52
+#define DWREG_ARM64_P5              53
+#define DWREG_ARM64_P6              54
+#define DWREG_ARM64_P7              55
+#define DWREG_ARM64_P8              56
+#define DWREG_ARM64_P9              57
+#define DWREG_ARM64_P10             58
+#define DWREG_ARM64_P11             59
+#define DWREG_ARM64_P12             60
+#define DWREG_ARM64_P13             61
+#define DWREG_ARM64_P14             62
+#define DWREG_ARM64_P15             63
+#define DWREG_ARM64_V0              64
+#define DWREG_ARM64_V1              65
+#define DWREG_ARM64_V2              66
+#define DWREG_ARM64_V3              67
+#define DWREG_ARM64_V4              68
+#define DWREG_ARM64_V5              69
+#define DWREG_ARM64_V6              70
+#define DWREG_ARM64_V7              71
+#define DWREG_ARM64_V8              72
+#define DWREG_ARM64_V9              73
+#define DWREG_ARM64_V10             74
+#define DWREG_ARM64_V11             75
+#define DWREG_ARM64_V12             76
+#define DWREG_ARM64_V13             77
+#define DWREG_ARM64_V14             78
+#define DWREG_ARM64_V15             79
+#define DWREG_ARM64_V16             80
+#define DWREG_ARM64_V17             81
+#define DWREG_ARM64_V18             82
+#define DWREG_ARM64_V19             83
+#define DWREG_ARM64_V20             84
+#define DWREG_ARM64_V21             85
+#define DWREG_ARM64_V22             86
+#define DWREG_ARM64_V23             87
+#define DWREG_ARM64_V24             88
+#define DWREG_ARM64_V25             89
+#define DWREG_ARM64_V26             90
+#define DWREG_ARM64_V27             91
+#define DWREG_ARM64_V28             92
+#define DWREG_ARM64_V29             93
+#define DWREG_ARM64_V30             94
+#define DWREG_ARM64_V31             95
+#define DWREG_ARM64_Z0              96
+#define DWREG_ARM64_Z1              97
+#define DWREG_ARM64_Z2              98
+#define DWREG_ARM64_Z3              99
+#define DWREG_ARM64_Z4              100
+#define DWREG_ARM64_Z5              101
+#define DWREG_ARM64_Z6              102
+#define DWREG_ARM64_Z7              103
+#define DWREG_ARM64_Z8              104
+#define DWREG_ARM64_Z9              105
+#define DWREG_ARM64_Z10             106
+#define DWREG_ARM64_Z11             107
+#define DWREG_ARM64_Z12             108
+#define DWREG_ARM64_Z13             109
+#define DWREG_ARM64_Z14             110
+#define DWREG_ARM64_Z15             111
+#define DWREG_ARM64_Z16             112
+#define DWREG_ARM64_Z17             113
+#define DWREG_ARM64_Z18             114
+#define DWREG_ARM64_Z19             115
+#define DWREG_ARM64_Z20             116
+#define DWREG_ARM64_Z21             117
+#define DWREG_ARM64_Z22             118
+#define DWREG_ARM64_Z23             119
+#define DWREG_ARM64_Z24             120
+#define DWREG_ARM64_Z25             121
+#define DWREG_ARM64_Z26             122
+#define DWREG_ARM64_Z27             123
+#define DWREG_ARM64_Z28             124
+#define DWREG_ARM64_Z29             125
+#define DWREG_ARM64_Z30             126
+#define DWREG_ARM64_Z31             127
+/** @} */
+
+
 #endif /* !IPRT_INCLUDED_formats_dwarf_h */