Changeset 101308 in vbox for trunk/include/VBox
- Timestamp:
- Sep 29, 2023 5:57:20 AM (16 months ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/include/VBox/vmm/hm_vmx.h
r101059 r101308 2540 2540 /** Enables XSAVES/XRSTORS instructions. */ 2541 2541 #define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20) 2542 /** Enables PASID translation. */ 2543 #define VMX_PROC_CTLS2_PASID_TRANSLATE RT_BIT(21) 2542 2544 /** Enables supervisor/user mode based EPT execute permission for linear 2543 2545 * addresses. */ … … 2552 2554 /** Enables TPAUSE, UMONITOR and UMWAIT instructions. */ 2553 2555 #define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26) 2556 /** Enables PCONFIG instruction. */ 2557 #define VMX_PROC_CTLS2_PCONFIG RT_BIT(27) 2554 2558 /** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */ 2555 2559 #define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28) 2560 /** Enables VMM Bus-lock detection. */ 2561 #define VMX_PROC_CTLS2_BUS_LOCK_DETECT RT_BIT(30) 2562 /** Enables instruction timeout VM-exits. */ 2563 #define VMX_PROC_CTLS2_INSTR_TIMEOUT RT_BIT(31) 2564 2556 2565 2557 2566 /** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based … … 2599 2608 #define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20 2600 2609 #define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000) 2601 #define VMX_BF_PROC_CTLS2_ RSVD_21_SHIFT212602 #define VMX_BF_PROC_CTLS2_ RSVD_21_MASKUINT32_C(0x00200000)2610 #define VMX_BF_PROC_CTLS2_PASID_TRANSLATE_SHIFT 21 2611 #define VMX_BF_PROC_CTLS2_PASID_TRANSLATE_MASK UINT32_C(0x00200000) 2603 2612 #define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22 2604 2613 #define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000) … … 2611 2620 #define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26 2612 2621 #define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000) 2613 #define VMX_BF_PROC_CTLS2_ RSVD_27_SHIFT 272614 #define VMX_BF_PROC_CTLS2_ RSVD_27_MASK UINT32_C(0x08000000)2622 #define VMX_BF_PROC_CTLS2_PCONFIG_SHIFT 27 2623 #define VMX_BF_PROC_CTLS2_PCONFIG_MASK UINT32_C(0x08000000) 2615 2624 #define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28 2616 2625 #define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000) 2617 #define VMX_BF_PROC_CTLS2_RSVD_29_31_SHIFT 29 2618 #define VMX_BF_PROC_CTLS2_RSVD_29_31_MASK UINT32_C(0xe0000000) 2626 #define VMX_BF_PROC_CTLS2_RSVD_29_SHIFT 29 2627 #define VMX_BF_PROC_CTLS2_RSVD_29_MASK UINT32_C(0x20000000) 2628 #define VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_SHIFT 30 2629 #define VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_MASK UINT32_C(0x40000000) 2630 #define VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_SHIFT 31 2631 #define VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_MASK UINT32_C(0x80000000) 2619 2632 2620 2633 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX, 2621 2634 (VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT, 2622 2635 UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC, 2623 VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, RSVD_21,2624 MODE_BASED_EPT_PERM, SPP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, RSVD_27, ENCLV_EXIT,2625 RSVD_29_31));2636 VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, 2637 PASID_TRANSLATE, MODE_BASED_EPT_PERM, SPP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, PCONFIG, 2638 ENCLV_EXIT, RSVD_29, BUSLOCK_DETECT, INSTR_TIMEOUT)); 2626 2639 /** @} */ 2627 2640 … … 2632 2645 /** VM-exit when executing LOADIWKEY. */ 2633 2646 #define VMX_PROC_CTLS3_LOADIWKEY_EXIT RT_BIT_64(0) 2647 /** Enables hypervisor-managed linear-address translation (HLAT). */ 2648 #define VMX_PROC_CTLS3_HLAT RT_BIT_64(1) 2649 /** Enables EPT paging-write control. */ 2650 #define VMX_PROC_CTLS3_EPT_PAGING_WRITE RT_BIT_64(2) 2651 /** Enables Guest-paging verification. */ 2652 #define VMX_PROC_CTLS3_GST_PAGING_VERIFY RT_BIT_64(3) 2653 /** Enables IPI virtualization. */ 2654 #define VMX_PROC_CTLS3_IPI_VIRT RT_BIT_64(4) 2655 /** Virtualize IA32_SPEC_CTRL. */ 2656 #define VMX_PROC_CTLS3_VIRT_SPEC_CTRL RT_BIT_64(7) 2634 2657 2635 2658 /** Bit fields for Tertiary processor-based VM-execution controls field in the VMCS. */ 2636 2659 #define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT 0 2637 2660 #define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_MASK UINT64_C(0x0000000000000001) 2638 #define VMX_BF_PROC_CTLS3_RSVD_1_63_SHIFT 1 2639 #define VMX_BF_PROC_CTLS3_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe) 2661 #define VMX_BF_PROC_CTLS3_HLAT_SHIFT 1 2662 #define VMX_BF_PROC_CTLS3_HLAT_MASK UINT64_C(0x0000000000000002) 2663 #define VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_SHIFT 2 2664 #define VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_MASK UINT64_C(0x0000000000000004) 2665 #define VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_SHIFT 3 2666 #define VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_MASK UINT64_C(0x0000000000000008) 2667 #define VMX_BF_PROC_CTLS3_IPI_VIRT_SHIFT 4 2668 #define VMX_BF_PROC_CTLS3_IPI_VIRT_MASK UINT64_C(0x0000000000000010) 2669 #define VMX_BF_PROC_CTLS3_RSVD_5_6_SHIFT 5 2670 #define VMX_BF_PROC_CTLS3_RSVD_5_6_MASK UINT64_C(0x0000000000000060) 2671 #define VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_SHIFT 7 2672 #define VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_MASK UINT64_C(0x0000000000000080) 2673 #define VMX_BF_PROC_CTLS3_RSVD_8_63_SHIFT 8 2674 #define VMX_BF_PROC_CTLS3_RSVD_8_63_MASK UINT64_C(0xffffffffffffff00) 2640 2675 2641 2676 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS3_, UINT64_C(0), UINT64_MAX, 2642 (LOADIWKEY_EXIT, RSVD_1_63)); 2677 (LOADIWKEY_EXIT, HLAT, EPT_PAGING_WRITE, GST_PAGING_VERIFY, IPI_VIRT, RSVD_5_6, VIRT_SPEC_CTRL, 2678 RSVD_8_63)); 2643 2679 /** @} */ 2644 2680
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