Index: /trunk/include/VBox/vmm/hm_vmx.h
===================================================================
--- /trunk/include/VBox/vmm/hm_vmx.h	(revision 101310)
+++ /trunk/include/VBox/vmm/hm_vmx.h	(revision 101311)
@@ -2704,6 +2704,10 @@
 /** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
 #define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR                        RT_BIT(18)
+/** Whether the guest UINV is loaded on VM-entry. */
+#define VMX_ENTRY_CTLS_LOAD_UINV                                RT_BIT(19)
 /** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
 #define VMX_ENTRY_CTLS_LOAD_CET_STATE                           RT_BIT(20)
+/** Whether the guest IA32_LBR_CTL MSR is loaded on VM-entry. */
+#define VMX_ENTRY_CTLS_LOAD_LBR_CTL_MSR                         RT_BIT(21)
 /** Whether the guest IA32_PKRS MSR is loaded on VM-entry. */
 #define VMX_ENTRY_CTLS_LOAD_PKRS_MSR                            RT_BIT(22)
@@ -2739,10 +2743,10 @@
 #define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT               18
 #define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK                UINT32_C(0x00040000)
-#define VMX_BF_ENTRY_CTLS_RSVD_19_SHIFT                         19
-#define VMX_BF_ENTRY_CTLS_RSVD_19_MASK                          UINT32_C(0x00080000)
+#define VMX_BF_ENTRY_CTLS_LOAD_UINV_SHIFT                       19
+#define VMX_BF_ENTRY_CTLS_LOAD_UINV_MASK                        UINT32_C(0x00080000)
 #define VMX_BF_ENTRY_CTLS_LOAD_CET_SHIFT                        20
 #define VMX_BF_ENTRY_CTLS_LOAD_CET_MASK                         UINT32_C(0x00100000)
-#define VMX_BF_ENTRY_CTLS_RSVD_21_SHIFT                         21
-#define VMX_BF_ENTRY_CTLS_RSVD_21_MASK                          UINT32_C(0x00200000)
+#define VMX_BF_ENTRY_CTLS_LOAD_LBR_CTL_MSR_SHIFT                21
+#define VMX_BF_ENTRY_CTLS_LOAD_LBR_CTL_MSR_MASK                 UINT32_C(0x00200000)
 #define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_SHIFT                   22
 #define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_MASK                    UINT32_C(0x00400000)
@@ -2753,5 +2757,5 @@
                             (RSVD_0_1, LOAD_DEBUG, RSVD_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, RSVD_12,
                              LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
-                             LOAD_RTIT_CTL_MSR, RSVD_19, LOAD_CET, RSVD_21, LOAD_PKRS_MSR, RSVD_23_31));
+                             LOAD_RTIT_CTL_MSR, LOAD_UINV, LOAD_CET, LOAD_LBR_CTL_MSR, LOAD_PKRS_MSR, RSVD_23_31));
 /** @} */
 
@@ -2785,4 +2789,8 @@
 /** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
 #define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR                        RT_BIT(25)
+/** Whether IA32_LBR_CTL MSR is cleared on VM-exit. */
+#define VMX_EXIT_CTLS_CLEAR_LBR_CTL_MSR                         RT_BIT(26)
+/** Whether UINV is cleared on VM-exit. */
+#define VMX_EXIT_CTLS_CLEAR_UINV                                RT_BIT(27)
 /** Whether CET-related MSRs and SPP are loaded on VM-exit. */
 #define VMX_EXIT_CTLS_LOAD_CET_STATE                            RT_BIT(28)
@@ -2832,6 +2840,8 @@
 #define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT               25
 #define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK                UINT32_C(0x02000000)
-#define VMX_BF_EXIT_CTLS_RSVD_26_27_SHIFT                       26
-#define VMX_BF_EXIT_CTLS_RSVD_26_27_MASK                        UINT32_C(0x0c000000)
+#define VMX_BF_EXIT_CTLS_CLEAR_LBR_CTL_MSR_SHIFT                26
+#define VMX_BF_EXIT_CTLS_CLEAR_LBR_CTL_MSR_MASK                 UINT32_C(0x04000000)
+#define VMX_BF_EXIT_CTLS_CLEAR_UINV_SHIFT                       27
+#define VMX_BF_EXIT_CTLS_CLEAR_UINV_MASK                        UINT32_C(0x08000000)
 #define VMX_BF_EXIT_CTLS_LOAD_CET_SHIFT                         28
 #define VMX_BF_EXIT_CTLS_LOAD_CET_MASK                          UINT32_C(0x10000000)
@@ -2845,6 +2855,6 @@
                             (RSVD_0_1, SAVE_DEBUG, RSVD_3_8, HOST_ADDR_SPACE_SIZE, RSVD_10_11, LOAD_PERF_MSR, RSVD_13_14,
                              ACK_EXT_INT, RSVD_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
-                             SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, RSVD_26_27,
-                             LOAD_CET, LOAD_PKRS_MSR, SAVE_PERF_MSR, USE_SECONDARY_CTLS));
+                             SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, CLEAR_LBR_CTL_MSR,
+                             CLEAR_UINV, LOAD_CET, LOAD_PKRS_MSR, SAVE_PERF_MSR, USE_SECONDARY_CTLS));
 /** @} */
 
