VirtualBox

Changeset 101375 in vbox


Ignore:
Timestamp:
Oct 6, 2023 8:24:29 AM (18 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
159378
Message:

ValidationKit/bootsectors: Implement testcases for vmpsadbw instructions, bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r100608 r101375  
    31443144EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM1, FSxBX, 000h
    31453145
     3146EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM1, XMM2, XMM3,  0FFh
     3147EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM1, XMM2, FSxBX, 0FFh
     3148EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM1, XMM2, XMM3,  000h
     3149EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM1, XMM2, FSxBX, 000h
     3150
     3151EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM1, YMM2, YMM3,  0FFh
     3152EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM1, YMM2, FSxBX, 0FFh
     3153EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM1, YMM2, YMM3,  000h
     3154EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM1, YMM2, FSxBX, 000h
     3155
    31463156 %if TMPL_BITS == 64
    31473157EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, XMM9,  0FFh
    … …  
    31493159EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, XMM9,  000h
    31503160EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, FSxBX, 000h
     3161
     3162EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM8, XMM9, XMM10, 0FFh
     3163EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM8, XMM9, FSxBX, 0FFh
     3164EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM8, XMM9, XMM10, 000h
     3165EMIT_INSTR_PLUS_ICEBP   vmpsadbw, XMM8, XMM9, FSxBX, 000h
     3166
     3167EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM8, YMM9, YMM10, 0FFh
     3168EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM8, YMM9, FSxBX, 0FFh
     3169EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM8, YMM9, YMM10, 000h
     3170EMIT_INSTR_PLUS_ICEBP   vmpsadbw, YMM8, YMM9, FSxBX, 000h
    31513171 %endif
    31523172

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r100608 r101375  
    78057805extern FNBS3FAR             bs3CpuInstr3_mpsadbw_XMM8_FSxBX_000h_icebp_c64;
    78067806
     7807BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp);
     7808BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp);
     7809BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp);
     7810BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp);
     7811extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_XMM8_XMM9_XMM10_0FFh_icebp_c64;
     7812extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_XMM8_XMM9_FSxBX_0FFh_icebp_c64;
     7813extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_XMM8_XMM9_XMM10_000h_icebp_c64;
     7814extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_XMM8_XMM9_FSxBX_000h_icebp_c64;
     7815
     7816BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp);
     7817BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp);
     7818BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp);
     7819BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp);
     7820extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_YMM8_YMM9_YMM10_0FFh_icebp_c64;
     7821extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_YMM8_YMM9_FSxBX_0FFh_icebp_c64;
     7822extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_YMM8_YMM9_YMM10_000h_icebp_c64;
     7823extern FNBS3FAR             bs3CpuInstr3_vmpsadbw_YMM8_YMM9_FSxBX_000h_icebp_c64;
     7824
    78077825BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_mpsadbw(uint8_t bMode)
    78087826{
    … …  
    78127830            /*src1*/ RTUINT256_INIT_C(  0, 0, 0, 0),
    78137831            /* => */ RTUINT256_INIT_C(  0, 0, 0, 0) },
    7814         {   /*src2*/ RTUINT256_INIT_C(  0, 1, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
    7815             /*src1*/ RTUINT256_INIT_C(  2, 3, 0x9192939495969798, 0x8182838485868788),
    7816             /* => */ RTUINT256_INIT_C(  4, 5, 0x00fc00f800f400f0, 0x01040118012c0140) },
    7817         {   /*src2*/ RTUINT256_INIT_C(  6, 7, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
    7818             /*src1*/ RTUINT256_INIT_C(  8, 9, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
    7819             /* => */ RTUINT256_INIT_C(10, 11, 0x01bf010e01a700d1, 0x0155013300fa01c9) },
     7832        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
     7833            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
     7834            /* => */ RTUINT256_INIT_C(0x00fc00f800f400f0, 0x01040118012c0140, 0x00fc00f800f400f0, 0x01040118012c0140) },
     7835
     7836        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
     7837            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     7838            /* => */ RTUINT256_INIT_C(0x01c9025300f401c6, 0x016a00e1022f0223, 0x01bf010e01a700d1, 0x0155013300fa01c9) },
    78207839    };
    78217840    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] =
    … …  
    78247843            /*src1*/ RTUINT256_INIT_C(0,   0, 0, 0),
    78257844            /* => */ RTUINT256_INIT_C(0,   0, 0, 0) },
    7826         {   /*src2*/ RTUINT256_INIT_C(0,   1, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
    7827             /*src1*/ RTUINT256_INIT_C(2,   3, 0x9192939495969798, 0x8182838485868788),
    7828             /* => */ RTUINT256_INIT_C(4,   5, 0x00d400e800fc0110, 0x010c010801040100) },
    7829         {   /*src2*/ RTUINT256_INIT_C(6,   7, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
    7830             /*src1*/ RTUINT256_INIT_C(8,   9, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
    7831             /* => */ RTUINT256_INIT_C(10, 11, 0x0104015600b9016c, 0x01a6017b005b0130) },
     7845        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
     7846            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
     7847            /* => */ RTUINT256_INIT_C(0x00d400e800fc0110, 0x010c010801040100, 0x00d400e800fc0110, 0x010c010801040100) },
     7848
     7849        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
     7850            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     7851            /* => */ RTUINT256_INIT_C(0x00a401a1013100f7, 0x0180011e017400f7, 0x0104015600b9016c, 0x01a6017b005b0130) },
    78327852    };
    78337853
    … …  
    78387858        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c16,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78397859        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c16,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7860
     7861        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp_c16,    255,         RM_REG, T_AVX_128,    1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7862        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_128,    1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7863        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp_c16,    255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7864        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7865
     7866        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp_c16,    255,         RM_REG, T_AVX_128,    1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7867        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_128,    1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7868        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp_c16,    255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7869        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78407870    };
    78417871    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
    … …  
    78457875        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c32,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78467876        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c32,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7877
     7878        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp_c32,    255,         RM_REG, T_AVX_128,    1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7879        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_128,    1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7880        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp_c32,    255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7881        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7882
     7883        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp_c32,    255,         RM_REG, T_AVX_128,    1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7884        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_128,    1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7885        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp_c32,    255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7886        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78477887    };
    78487888    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
    … …  
    78577897        {  bs3CpuInstr3_mpsadbw_XMM8_XMM9_000h_icebp_c64,          255,         RM_REG, T_SSE4_1,     8, 8,   9, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78587898        {  bs3CpuInstr3_mpsadbw_XMM8_FSxBX_000h_icebp_c64,         255,         RM_MEM, T_SSE4_1,     8, 8, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7899
     7900        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp_c64,    255,         RM_REG, T_AVX_128,    1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7901        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,    1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7902        {  bs3CpuInstr3_vmpsadbw_XMM8_XMM9_XMM10_0FFh_icebp_c64,   255,         RM_REG, T_AVX_128,    8, 9,  10, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7903        {  bs3CpuInstr3_vmpsadbw_XMM8_XMM9_FSxBX_0FFh_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,    8, 9, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7904        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp_c64,    255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7905        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7906        {  bs3CpuInstr3_vmpsadbw_YMM8_YMM9_YMM10_0FFh_icebp_c64,   255,         RM_REG, T_AVX2_256,   8, 9,  10, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7907        {  bs3CpuInstr3_vmpsadbw_YMM8_YMM9_FSxBX_0FFh_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   8, 9, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
     7908
     7909        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp_c64,    255,         RM_REG, T_AVX_128,    1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7910        {  bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,    1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7911        {  bs3CpuInstr3_vmpsadbw_XMM8_XMM9_XMM10_000h_icebp_c64,   255,         RM_REG, T_AVX_128,    8, 9,  10, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7912        {  bs3CpuInstr3_vmpsadbw_XMM8_XMM9_FSxBX_000h_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,    8, 9, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7913        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp_c64,    255,         RM_REG, T_AVX2_256,   1, 2,   3, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7914        {  bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   1, 2, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7915        {  bs3CpuInstr3_vmpsadbw_YMM8_YMM9_YMM10_000h_icebp_c64,   255,         RM_REG, T_AVX2_256,   8, 9,  10, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     7916        {  bs3CpuInstr3_vmpsadbw_YMM8_YMM9_FSxBX_000h_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX2_256,   8, 9, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
    78597917    };
    78607918    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    1383513893#endif
    1383613894#if defined (ALL_TESTS)
    13837         { "mpsadbw",                                        bs3CpuInstr3_v_mpsadbw, 0 },
     13895        { "[v]mpsadbw",                                     bs3CpuInstr3_v_mpsadbw, 0 },
    1383813896
    1383913897#endif
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette