Changeset 101387 in vbox for trunk/src/VBox/VMM

Timestamp:

Oct 7, 2023 11:34:54 PM (16 months ago)

Author:

vboxsync

Message:

VMM/IEM: Added a new class of threaded function variants, the 16f/32f/64f variants that will clear RF (and vbox internal friends) and check for TF (and vbox internal friends). The variants w/o the 'f' after the bitcount will skip this test+branch. The motivation of this was to deal with this issue that the threaded recompiler level rather than try optimize away the test+branch++ code when generating native code, make the IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32 a very simple place to start emitting native code (compared to IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS). bugref:10371

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstCommon.cpp.h (modified) (6 diffs)
• VMMAll/IEMAllInstCommonBodyMacros.h (modified) (6 diffs)
• VMMAll/IEMAllInstOneByte.cpp.h (modified) (363 diffs)
• VMMAll/IEMAllInstPython.py (modified) (15 diffs)
• VMMAll/IEMAllInstThree0f38.cpp.h (modified) (47 diffs)
• VMMAll/IEMAllInstThree0f3a.cpp.h (modified) (48 diffs)
• VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (413 diffs)
• VMMAll/IEMAllInstVexMap1.cpp.h (modified) (129 diffs)
• VMMAll/IEMAllInstVexMap2.cpp.h (modified) (61 diffs)
• VMMAll/IEMAllInstVexMap3.cpp.h (modified) (30 diffs)
• VMMAll/IEMAllN8vePython.py (modified) (3 diffs)
• VMMAll/IEMAllN8veRecompiler.cpp (modified) (7 diffs)
• VMMAll/IEMAllThrdFuncs.cpp (modified) (6 diffs)
• VMMAll/IEMAllThrdPython.py (modified) (38 diffs)
• VMMAll/IEMAllThrdRecompiler.cpp (modified) (14 diffs)
• VMMAll/IEMAllThrdTables.h (modified) (2 diffs)
• include/IEMInline.h (modified) (4 diffs)
• include/IEMInternal.h (modified) (2 diffs)
• include/IEMMc.h (modified) (2 diffs)
• include/IEMN8veRecompiler.h (modified) (1 diff)
• testcase/tstIEMCheckMc.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstCommon.cpp.h

@@ -897 +897 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Value);
@@ -907 +907 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
@@ -917 +917 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
@@ -939 +939 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(5, 1, 0);
+            IEM_MC_BEGIN(5, 1, 0, 0);
             IEM_MC_ARG(uint16_t,        uSel,                                    0);
             IEM_MC_ARG(uint16_t,        offSeg,                                  1);
@@ -957 +957 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(5, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(5, 1, IEM_MC_F_MIN_386, 0);
             IEM_MC_ARG(uint16_t,        uSel,                                    0);
             IEM_MC_ARG(uint32_t,        offSeg,                                  1);
@@ -975 +975 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(5, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(5, 1, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint16_t,        uSel,                                    0);
             IEM_MC_ARG(uint64_t,        offSeg,                                  1);

trunk/src/VBox/VMM/VMMAll/IEMAllInstCommonBodyMacros.h

@@ -50 +50 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, a_f16BitMcFlag); \
+                IEM_MC_BEGIN(3, 0, a_f16BitMcFlag, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
@@ -66 +66 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
@@ -84 +84 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
@@ -110 +110 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 1, a_f16BitMcFlag); \
+                IEM_MC_BEGIN(3, 1, a_f16BitMcFlag, 0); \
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
                 IEM_MC_ARG(uint16_t,   u16Src,  1); \
@@ -128 +128 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0); \
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
                 IEM_MC_ARG(uint32_t,   u32Src,  1); \
@@ -148 +148 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
                 IEM_MC_ARG(uint64_t,   u64Src,  1); \

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -71 +71 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
-        IEM_MC_BEGIN(3, 0, 0); \
+        IEM_MC_BEGIN(3, 0, 0, 0); \
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0); \
         IEM_MC_ARG(uint8_t,    u8Src,   1); \
@@ -94 +94 @@
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \
         { \
-            IEM_MC_BEGIN(3, 3, 0); \
+            IEM_MC_BEGIN(3, 3, 0, 0); \
             IEM_MC_ARG(uint8_t *,  pu8Dst,           0); \
             IEM_MC_ARG(uint8_t,    u8Src,            1); \
@@ -131 +131 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
-        IEM_MC_BEGIN(3, 0, 0); \
+        IEM_MC_BEGIN(3, 0, 0, 0); \
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0); \
         IEM_MC_ARG(uint8_t,    u8Src,   1); \
@@ -154 +154 @@
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \
         { \
-            IEM_MC_BEGIN(3, 3, 0); \
+            IEM_MC_BEGIN(3, 3, 0, 0); \
             IEM_MC_ARG(uint8_t const *, pu8Dst,          0); \
             IEM_MC_ARG(uint8_t,         u8Src,           1); \
@@ -185 +185 @@
 
 #define IEMOP_BODY_BINARY_rm_r8_LOCKED(a_fnLockedU8) \
-            IEM_MC_BEGIN(3, 3, 0); \
+            IEM_MC_BEGIN(3, 3, 0, 0); \
             IEM_MC_ARG(uint8_t *,  pu8Dst,           0); \
             IEM_MC_ARG(uint8_t,    u8Src,            1); \
@@ -219 +219 @@
     if (IEM_IS_MODRM_REG_MODE(bRm)) \
     { \
-        IEM_MC_BEGIN(3, 0, 0); \
+        IEM_MC_BEGIN(3, 0, 0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0); \
@@ -238 +238 @@
          * We're accessing memory. \
          */ \
-        IEM_MC_BEGIN(3, 1, 0); \
+        IEM_MC_BEGIN(3, 1, 0, 0); \
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0); \
         IEM_MC_ARG(uint8_t,    u8Src,   1); \
@@ -272 +272 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, 0); \
+                IEM_MC_BEGIN(3, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
@@ -288 +288 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
@@ -305 +305 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
@@ -335 +335 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *, pu16Dst,          0); \
                     IEM_MC_ARG(uint16_t,   u16Src,           1); \
@@ -356 +356 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *, pu32Dst,          0); \
                     IEM_MC_ARG(uint32_t,   u32Src,           1); \
@@ -377 +377 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *, pu64Dst,          0); \
                     IEM_MC_ARG(uint64_t,   u64Src,           1); \
@@ -408 +408 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *, pu16Dst,          0); \
                     IEM_MC_ARG(uint16_t,   u16Src,           1); \
@@ -429 +429 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *, pu32Dst,          0); \
                     IEM_MC_ARG(uint32_t,   u32Src,           1); \
@@ -450 +450 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *, pu64Dst,          0); \
                     IEM_MC_ARG(uint64_t,   u64Src,           1); \
@@ -491 +491 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, 0); \
+                IEM_MC_BEGIN(3, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
@@ -507 +507 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
@@ -523 +523 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
@@ -553 +553 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t const *, pu16Dst,         0); \
                     IEM_MC_ARG(uint16_t,         u16Src,          1); \
@@ -574 +574 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t const *, pu32Dst,         0); \
                     IEM_MC_ARG(uint32_t,         u32Src,          1); \
@@ -595 +595 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t const *, pu64Dst,         0); \
                     IEM_MC_ARG(uint64_t,         u64Src,          1); \
@@ -634 +634 @@
     uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
     \
-    IEM_MC_BEGIN(3, 0, 0); \
+    IEM_MC_BEGIN(3, 0, 0, 0); \
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
     IEM_MC_ARG(uint8_t *,       pu8Dst,             0); \
@@ -658 +658 @@
             uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); \
             \
-            IEM_MC_BEGIN(3, 0, 0); \
+            IEM_MC_BEGIN(3, 0, 0, 0); \
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
@@ -676 +676 @@
             uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); \
             \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
@@ -696 +696 @@
             uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); \
             \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
@@ -1123 +1123 @@
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEMOP_HLP_NO_64BIT();
-    IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, iemCImpl_pop_Sreg, X86_SREG_SS, pVCpu->iem.s.enmEffOpSize);
+    IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_INHIBIT_SHADOW,
+                                iemCImpl_pop_Sreg, X86_SREG_SS, pVCpu->iem.s.enmEffOpSize);
 }
 
@@ -1768 +1769 @@
     { \
         case IEMMODE_16BIT: \
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_64BIT); \
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_64BIT, 0); \
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint16_t *,  pu16Dst, 0); \
@@ -1780 +1781 @@
             \
         case IEMMODE_32BIT: \
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT); \
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0); \
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
             IEM_MC_ARG(uint32_t *,  pu32Dst, 0); \
@@ -2195 +2196 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Value);
@@ -2205 +2206 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
@@ -2215 +2216 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
@@ -2277 +2278 @@
     if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_8086)
     {
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_ONLY_8086);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_ONLY_8086, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(uint16_t, u16Value);
@@ -2335 +2336 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t *, pu16Dst);
@@ -2345 +2346 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t *, pu32Dst);
@@ -2356 +2357 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t *, pu64Dst);
@@ -2428 +2429 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
                                    DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
@@ -2439 +2440 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
                                    DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
@@ -2450 +2451 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
                                    DISOPTYPE_HARMLESS | DISOPTYPE_X86_DEFAULT_64_OP_SIZE | DISOPTYPE_X86_REXB_EXTENDS_OPREG);
@@ -2605 +2606 @@
             if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
             {
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_186 | IEM_MC_F_NOT_64BIT);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_186 | IEM_MC_F_NOT_64BIT, 0);
                 IEM_MC_ARG(uint16_t,    u16Index,       0); /* Note! All operands are actually signed. Lazy unsigned bird. */
                 IEM_MC_ARG(uint16_t,    u16LowerBounds, 1);
@@ -2623 +2624 @@
             else /* 32-bit operands */
             {
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0);
                 IEM_MC_ARG(uint32_t,    u32Index,       0); /* Note! All operands are actually signed. Lazy unsigned bird. */
                 IEM_MC_ARG(uint32_t,    u32LowerBounds, 1);
@@ -2683 +2684 @@
     {
         /* Register */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_286 | IEM_MC_F_NOT_64BIT);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_286 | IEM_MC_F_NOT_64BIT, 0);
         IEMOP_HLP_DECODED_NL_2(OP_ARPL, IEMOPFORM_MR_REG, OP_PARM_Ew, OP_PARM_Gw, DISOPTYPE_HARMLESS);
         IEM_MC_ARG(uint16_t *,      pu16Dst,    0);
@@ -2700 +2701 @@
     {
         /* Memory */
-        IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_286 | IEM_MC_F_NOT_64BIT);
+        IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_286 | IEM_MC_F_NOT_64BIT, 0);
         IEM_MC_ARG(uint16_t *, pu16Dst,          0);
         IEM_MC_ARG(uint16_t,   u16Src,           1);
@@ -2742 +2743 @@
              * Register to register.
              */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
@@ -2755 +2756 @@
              * We're loading a register from memory.
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -2873 +2874 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_186);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_186, 0);
             uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -2882 +2883 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0);
             uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -2891 +2892 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
             uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -2923 +2924 @@
                 /* register operand */
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_186);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_186, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,            0);
@@ -2942 +2943 @@
             {
                 /* memory operand */
-                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_186);
+                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_186, 0);
                 IEM_MC_ARG(uint16_t *,      pu16Dst,            0);
                 IEM_MC_ARG(uint16_t,        u16Src,             1);
@@ -2972 +2973 @@
                 /* register operand */
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,            0);
@@ -2991 +2992 @@
             {
                 /* memory operand */
-                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,      pu32Dst,            0);
                 IEM_MC_ARG(uint32_t,        u32Src,             1);
@@ -3021 +3022 @@
                 /* register operand */
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,            0);
@@ -3040 +3041 @@
             {
                 /* memory operand */
-                IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,      pu64Dst,            0);
                 IEM_MC_ARG(uint64_t,        u64Src,             1);
@@ -3081 +3082 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_186);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_186, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_PUSH_U16(i8Imm);
@@ -3088 +3089 @@
             break;
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_PUSH_U32(i8Imm);
@@ -3095 +3096 @@
             break;
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_PUSH_U64(i8Imm);
@@ -3124 +3125 @@
             {
                 /* register operand */
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_186);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_186, 0);
                 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -3144 +3145 @@
             {
                 /* memory operand */
-                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_186);
+                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_186, 0);
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0);
                 IEM_MC_ARG(uint16_t,        u16Src,                     1);
@@ -3174 +3175 @@
                 /* register operand */
                 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0);
@@ -3193 +3194 @@
             {
                 /* memory operand */
-                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0);
                 IEM_MC_ARG(uint32_t,        u32Src,                     1);
@@ -3223 +3224 @@
                 /* register operand */
                 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0);
@@ -3242 +3243 @@
             {
                 /* memory operand */
-                IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0);
                 IEM_MC_ARG(uint64_t,        u64Src,                     1);
@@ -3531 +3532 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
@@ -3551 +3552 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
@@ -3570 +3571 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
@@ -3590 +3591 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
@@ -3610 +3611 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
@@ -3630 +3631 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
@@ -3650 +3651 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
@@ -3670 +3671 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
@@ -3690 +3691 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
@@ -3710 +3711 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
@@ -3730 +3731 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
@@ -3750 +3751 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
@@ -3770 +3771 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
@@ -3790 +3791 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
@@ -3810 +3811 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
@@ -3830 +3831 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
@@ -3850 +3851 @@
         /* register target */ \
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
-        IEM_MC_BEGIN(3, 0, 0); \
+        IEM_MC_BEGIN(3, 0, 0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
@@ -3868 +3869 @@
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \
         { \
-            IEM_MC_BEGIN(3, 3, 0); \
+            IEM_MC_BEGIN(3, 3, 0, 0); \
             IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
             IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
@@ -3893 +3894 @@
 
 #define IEMOP_BODY_BINARY_Eb_Ib_LOCKED(a_fnLockedU8) \
-            IEM_MC_BEGIN(3, 3, 0); \
+            IEM_MC_BEGIN(3, 3, 0, 0); \
             IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
             IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
@@ -3921 +3922 @@
         /* register target */ \
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
-        IEM_MC_BEGIN(3, 0, 0); \
+        IEM_MC_BEGIN(3, 0, 0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
@@ -3939 +3940 @@
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \
         { \
-            IEM_MC_BEGIN(3, 3, 0); \
+            IEM_MC_BEGIN(3, 3, 0, 0); \
             IEM_MC_ARG(uint8_t const *, pu8Dst,                 0); \
             IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
@@ -4101 +4102 @@
             { \
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); \
-                IEM_MC_BEGIN(3, 0, 0); \
+                IEM_MC_BEGIN(3, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
@@ -4119 +4120 @@
             { \
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
@@ -4138 +4139 @@
             { \
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
@@ -4165 +4166 @@
                 case IEMMODE_16BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,        u16Src,                 1); \
@@ -4189 +4190 @@
                 case IEMMODE_32BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,        u32Src,                 1); \
@@ -4213 +4214 @@
                 case IEMMODE_64BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,        u64Src,                 1); \
@@ -4247 +4248 @@
                 case IEMMODE_16BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,        u16Src,                 1); \
@@ -4271 +4272 @@
                 case IEMMODE_32BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,        u32Src,                 1); \
@@ -4295 +4296 @@
                 case IEMMODE_64BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,        u64Src,                 1); \
@@ -4333 +4334 @@
             { \
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); \
-                IEM_MC_BEGIN(3, 0, 0); \
+                IEM_MC_BEGIN(3, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
@@ -4351 +4352 @@
             { \
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
@@ -4369 +4370 @@
             { \
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
@@ -4396 +4397 @@
                 case IEMMODE_16BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t const *, pu16Dst,               0); \
                     IEM_MC_ARG(uint16_t,         u16Src,                1); \
@@ -4420 +4421 @@
                 case IEMMODE_32BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t const *, pu32Dst,               0); \
                     IEM_MC_ARG(uint32_t,         u32Src,                1); \
@@ -4444 +4445 @@
                 case IEMMODE_64BIT: \
                 { \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t const *, pu64Dst,               0); \
                     IEM_MC_ARG(uint64_t,         u64Src,                1); \
@@ -4620 +4621 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, 0); \
+                IEM_MC_BEGIN(3, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
@@ -4635 +4636 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
@@ -4651 +4652 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
@@ -4678 +4679 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
                     IEM_MC_ARG(uint16_t,        u16Src,                     1); \
@@ -4700 +4701 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
                     IEM_MC_ARG(uint32_t,        u32Src,                     1); \
@@ -4722 +4723 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
                     IEM_MC_ARG(uint64_t,        u64Src,                     1); \
@@ -4754 +4755 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
                     IEM_MC_ARG(uint16_t,        u16Src,                     1); \
@@ -4776 +4777 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
                     IEM_MC_ARG(uint32_t,        u32Src,                     1); \
@@ -4798 +4799 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
                     IEM_MC_ARG(uint64_t,        u64Src,                     1); \
@@ -4836 +4837 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, 0); \
+                IEM_MC_BEGIN(3, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
@@ -4851 +4852 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
@@ -4866 +4867 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
@@ -4893 +4894 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, 0); \
+                    IEM_MC_BEGIN(3, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t const *, pu16Dst,                   0); \
                     IEM_MC_ARG(uint16_t,         u16Src,                    1); \
@@ -4915 +4916 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t const *, pu32Dst,                   0); \
                     IEM_MC_ARG(uint32_t,         u32Src,                    1); \
@@ -4937 +4938 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t const *, pu64Dst,                   0); \
                     IEM_MC_ARG(uint64_t,         u64Src,                    1); \
@@ -5124 +5125 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(uint8_t, uTmp1);
@@ -5142 +5143 @@
          * We're accessing memory.
          */
-        IEM_MC_BEGIN(2, 4, 0);
+        IEM_MC_BEGIN(2, 4, 0, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_LOCAL(uint8_t, bUnmapInfo);
@@ -5182 +5183 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, 0);
+                IEM_MC_BEGIN(0, 2, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, uTmp1);
@@ -5197 +5198 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, uTmp1);
@@ -5212 +5213 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, uTmp1);
@@ -5237 +5238 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(2, 4, 0);
+                IEM_MC_BEGIN(2, 4, 0, 0);
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst);
                 IEM_MC_LOCAL(uint8_t,  bUnmapInfo);
@@ -5260 +5261 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(2, 4, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(2, 4, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst);
                 IEM_MC_LOCAL(uint8_t,  bUnmapInfo);
@@ -5283 +5284 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(2, 4, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(2, 4, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst);
                 IEM_MC_LOCAL(uint8_t,  bUnmapInfo);
@@ -5326 +5327 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(uint8_t, u8Value);
@@ -5339 +5340 @@
          * We're writing a register to memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint8_t, u8Value);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5369 +5370 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, 0);
+                IEM_MC_BEGIN(0, 1, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
@@ -5379 +5380 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
@@ -5389 +5390 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
@@ -5409 +5410 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, 0);
+                IEM_MC_BEGIN(0, 2, 0, 0);
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5421 +5422 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5433 +5434 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5464 +5465 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(uint8_t, u8Value);
@@ -5477 +5478 @@
          * We're loading a register from memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint8_t, u8Value);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5507 +5508 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, 0);
+                IEM_MC_BEGIN(0, 1, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
@@ -5517 +5518 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
@@ -5527 +5528 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
@@ -5547 +5548 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, 0);
+                IEM_MC_BEGIN(0, 2, 0, 0);
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5559 +5560 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5571 +5572 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -5628 +5629 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, 0);
+                IEM_MC_BEGIN(0, 1, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
@@ -5638 +5639 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
@@ -5648 +5649 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
@@ -5669 +5670 @@
         pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_16BIT;
 #endif
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint16_t,  u16Value);
         IEM_MC_LOCAL(RTGCPTR,   GCPtrEffDst);
@@ -5697 +5698 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc);
             IEM_MC_LOCAL(uint16_t, u16Cast);
@@ -5709 +5710 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Cast);
@@ -5721 +5722 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
@@ -5766 +5767 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(2, 0, 0);
+        /** @todo Only set IEM_CIMPL_F_INHIBIT_SHADOW when it actually applies... */
+        IEM_MC_BEGIN(2, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG_CONST(uint8_t, iSRegArg, iSegReg, 0);
@@ -5772 +5774 @@
         IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm));
         if (iSRegArg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu))
-            IEM_MC_CALL_CIMPL_2(               0, iemCImpl_load_SReg, iSRegArg, u16Value);
+            IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_INHIBIT_SHADOW,                    iemCImpl_load_SReg, iSRegArg, u16Value);
         else
-            IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE, iemCImpl_load_SReg, iSRegArg, u16Value);
+            IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_INHIBIT_SHADOW | IEM_CIMPL_F_MODE, iemCImpl_load_SReg, iSRegArg, u16Value);
         IEM_MC_END();
     }
@@ -5783 +5785 @@
          * regardless of operand size prefixes.
          */
-        IEM_MC_BEGIN(2, 1, 0);
+        /** @todo Only set IEM_CIMPL_F_INHIBIT_SHADOW when it actually applies... */
+        IEM_MC_BEGIN(2, 1, 0, 0);
         IEM_MC_ARG_CONST(uint8_t, iSRegArg, iSegReg, 0);
         IEM_MC_ARG(uint16_t,      u16Value,          1);
@@ -5791 +5794 @@
         IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
         if (iSRegArg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu))
-            IEM_MC_CALL_CIMPL_2(               0, iemCImpl_load_SReg, iSRegArg, u16Value);
+            IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_INHIBIT_SHADOW,                    iemCImpl_load_SReg, iSRegArg, u16Value);
         else
-            IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE, iemCImpl_load_SReg, iSRegArg, u16Value);
+            IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_INHIBIT_SHADOW | IEM_CIMPL_F_MODE, iemCImpl_load_SReg, iSRegArg, u16Value);
         IEM_MC_END();
     }
@@ -5835 +5838 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(2, 0, 0);
+            IEM_MC_BEGIN(2, 0, 0, 0);
             IEM_MC_ARG(uint8_t, iEffSeg,     0);
             IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
@@ -5846 +5849 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386, 0);
             IEM_MC_ARG(uint8_t, iEffSeg,     0);
             IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
@@ -5857 +5860 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint8_t, iEffSeg,     0);
             IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
@@ -6008 +6011 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Tmp1);
@@ -6021 +6024 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Tmp1);
@@ -6034 +6037 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Tmp1);
@@ -6082 +6085 @@
         IEMOP_MNEMONIC(nop, "nop");
     /** @todo testcase: lock nop; lock pause */
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING();
     IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -6168 +6171 @@
         case IEMMODE_16BIT:
             IEMOP_MNEMONIC(cbw, "cbw");
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 7) {
@@ -6181 +6184 @@
         case IEMMODE_32BIT:
             IEMOP_MNEMONIC(cwde, "cwde");
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 15) {
@@ -6194 +6197 @@
         case IEMMODE_64BIT:
             IEMOP_MNEMONIC(cdqe, "cdqe");
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 31) {
@@ -6219 +6222 @@
         case IEMMODE_16BIT:
             IEMOP_MNEMONIC(cwd, "cwd");
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 15) {
@@ -6232 +6235 @@
         case IEMMODE_32BIT:
             IEMOP_MNEMONIC(cdq, "cdq");
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 31) {
@@ -6245 +6248 @@
         case IEMMODE_64BIT:
             IEMOP_MNEMONIC(cqo, "cqo");
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 63) {
@@ -6287 +6290 @@
 {
     IEMOP_MNEMONIC(wait, "wait");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE();
@@ -6330 +6333 @@
         && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf)
         IEMOP_RAISE_INVALID_OPCODE_RET();
-    IEM_MC_BEGIN(0, 2, 0);
+    IEM_MC_BEGIN(0, 2, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint32_t, u32Flags);
@@ -6355 +6358 @@
         && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf)
         IEMOP_RAISE_INVALID_OPCODE_RET();
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint8_t, u8Flags);
@@ -6404 +6407 @@
      * Fetch AL.
      */
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint8_t, u8Tmp);
@@ -6432 +6435 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Tmp);
@@ -6442 +6445 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -6452 +6455 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6481 +6484 @@
      * Store AL.
      */
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint8_t, u8Tmp);
@@ -6509 +6512 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint16_t, u16Tmp);
@@ -6519 +6522 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -6529 +6532 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6544 +6547 @@
 /** Macro used by iemOp_movsb_Xb_Yb and iemOp_movswd_Xv_Yv */
 #define IEM_MOVS_CASE(ValBits, AddrBits, a_fMcFlags) \
-        IEM_MC_BEGIN(0, 2, a_fMcFlags); \
+        IEM_MC_BEGIN(0, 2, a_fMcFlags, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
@@ -6685 +6688 @@
 /** Macro used by iemOp_cmpsb_Xb_Yb and iemOp_cmpswd_Xv_Yv */
 #define IEM_CMPS_CASE(ValBits, AddrBits, a_fMcFlags) \
-        IEM_MC_BEGIN(3, 3, a_fMcFlags); \
+        IEM_MC_BEGIN(3, 3, a_fMcFlags, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint##ValBits##_t *, puValue1, 0); \
@@ -6903 +6906 @@
 /** Macro used by iemOp_stosb_Yb_AL and iemOp_stoswd_Yv_eAX */
 #define IEM_STOS_CASE(ValBits, AddrBits, a_fMcFlags) \
-        IEM_MC_BEGIN(0, 2, a_fMcFlags); \
+        IEM_MC_BEGIN(0, 2, a_fMcFlags, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
@@ -7040 +7043 @@
 /** Macro used by iemOp_lodsb_AL_Xb and iemOp_lodswd_eAX_Xv */
 #define IEM_LODS_CASE(ValBits, AddrBits, a_fMcFlags) \
-        IEM_MC_BEGIN(0, 2, a_fMcFlags); \
+        IEM_MC_BEGIN(0, 2, a_fMcFlags, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
@@ -7177 +7180 @@
 /** Macro used by iemOp_scasb_AL_Xb and iemOp_scaswd_eAX_Xv */
 #define IEM_SCAS_CASE(ValBits, AddrBits, a_fMcFlags) \
-        IEM_MC_BEGIN(3, 2, a_fMcFlags); \
+        IEM_MC_BEGIN(3, 2, a_fMcFlags, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
         IEM_MC_ARG(uint##ValBits##_t *, puRax,   0); \
@@ -7370 +7373 @@
 {
     uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL_CONST(uint8_t, u8Value,/*=*/ u8Imm);
@@ -7467 +7470 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7477 +7480 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7487 +7490 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             uint64_t u64Imm; IEM_OPCODE_GET_NEXT_U64(&u64Imm); /* 64-bit immediate! */
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7606 +7609 @@
         /* register */
         uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_186);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_186, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint8_t *,       pu8Dst,            0);
@@ -7620 +7623 @@
     {
         /* memory */
-        IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_186);
+        IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_186, 0);
         IEM_MC_ARG(uint8_t *,   pu8Dst,    0);
         IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -7672 +7675 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_186);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_186, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,           0);
@@ -7685 +7688 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,           0);
@@ -7699 +7702 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,           0);
@@ -7720 +7723 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 3, 0);
+                IEM_MC_BEGIN(3, 3, 0, 0);
                 IEM_MC_ARG(uint16_t *,  pu16Dst,    0);
                 IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -7742 +7745 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,  pu32Dst,    0);
                 IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -7764 +7767 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,  pu64Dst,    0);
                 IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -7964 +7967 @@
         /* register access */
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_RM(pVCpu, bRm), u8Imm);
@@ -7973 +7976 @@
     {
         /* memory access. */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
@@ -8001 +8004 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 0, 0);
+                IEM_MC_BEGIN(0, 0, 0, 0);
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8010 +8013 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8019 +8022 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8036 +8039 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, 0);
+                IEM_MC_BEGIN(0, 1, 0, 0);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2);
@@ -8047 +8050 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
@@ -8058 +8061 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
@@ -8206 +8209 @@
     {
         /* register */
-        IEM_MC_BEGIN(3, 0, 0);
+        IEM_MC_BEGIN(3, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint8_t *,       pu8Dst,             0);
@@ -8220 +8223 @@
     {
         /* memory */
-        IEM_MC_BEGIN(3, 3, 0);
+        IEM_MC_BEGIN(3, 3, 0, 0);
         IEM_MC_ARG(uint8_t *,       pu8Dst,             0);
         IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=*/1,   1);
@@ -8269 +8272 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, 0);
+                IEM_MC_BEGIN(3, 0, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,           0);
@@ -8282 +8285 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,           0);
@@ -8296 +8299 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,           0);
@@ -8317 +8320 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 3, 0);
+                IEM_MC_BEGIN(3, 3, 0, 0);
                 IEM_MC_ARG(uint16_t *,      pu16Dst,            0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=1*/1,  1);
@@ -8337 +8340 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,      pu32Dst,            0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=1*/1,  1);
@@ -8357 +8360 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,      pu64Dst,            0);
                 IEM_MC_ARG_CONST(uint8_t,   cShiftArg,/*=1*/1,  1);
@@ -8406 +8409 @@
     {
         /* register */
-        IEM_MC_BEGIN(3, 0, 0);
+        IEM_MC_BEGIN(3, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint8_t *,   pu8Dst,     0);
@@ -8421 +8424 @@
     {
         /* memory */
-        IEM_MC_BEGIN(3, 3, 0);
+        IEM_MC_BEGIN(3, 3, 0, 0);
         IEM_MC_ARG(uint8_t *,   pu8Dst,          0);
         IEM_MC_ARG(uint8_t,     cShiftArg,       1);
@@ -8470 +8473 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, 0);
+                IEM_MC_BEGIN(3, 0, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,    0);
@@ -8484 +8487 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,    0);
@@ -8499 +8502 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,    0);
@@ -8521 +8524 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 3, 0);
+                IEM_MC_BEGIN(3, 3, 0, 0);
                 IEM_MC_ARG(uint16_t *,  pu16Dst,    0);
                 IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -8542 +8545 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,  pu32Dst,    0);
                 IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -8563 +8566 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,  pu64Dst,    0);
                 IEM_MC_ARG(uint8_t,     cShiftArg,  1);
@@ -8624 +8627 @@
     IEMOP_HLP_NO_64BIT();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
@@ -8645 +8648 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(2, 0, 0);
+            IEM_MC_BEGIN(2, 0, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint8_t,  u8Tmp);
@@ -8658 +8661 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint8_t,  u8Tmp);
@@ -8671 +8674 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint8_t,  u8Tmp);
@@ -8697 +8700 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_st0_stN, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -8728 +8731 @@
 FNIEMOP_DEF_2(iemOpHlpFpuNoStore_st0_stN, uint8_t, bRm, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -8759 +8762 @@
 FNIEMOP_DEF_2(iemOpHlpFpuNoStore_st0_stN_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -8854 +8857 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_st0_m32r, uint8_t, bRm, PFNIEMAIMPLFPUR32, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -8903 +8906 @@
     IEMOP_MNEMONIC(fcom_st0_m32r, "fcom st0,m32r");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -8936 +8939 @@
     IEMOP_MNEMONIC(fcomp_st0_m32r, "fcomp st0,m32r");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -9043 +9046 @@
     IEMOP_MNEMONIC(fld_m32r, "fld m32r");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -9073 +9076 @@
 {
     IEMOP_MNEMONIC(fst_m32r, "fst m32r");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -9108 +9111 @@
 {
     IEMOP_MNEMONIC(fstp_m32r, "fstp m32r");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -9143 +9146 @@
 {
     IEMOP_MNEMONIC(fldenv, "fldenv m14/28byte");
-    IEM_MC_BEGIN(3, 0, 0);
+    IEM_MC_BEGIN(3, 0, 0, 0);
     IEM_MC_ARG_CONST(IEMMODE,           enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize,  0);
     IEM_MC_ARG(uint8_t,                 iEffSeg,                                    1);
@@ -9161 +9164 @@
 {
     IEMOP_MNEMONIC(fldcw_m2byte, "fldcw m2byte");
-    IEM_MC_BEGIN(1, 1, 0);
+    IEM_MC_BEGIN(1, 1, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_ARG(uint16_t,                u16Fsw,                                     0);
@@ -9178 +9181 @@
 {
     IEMOP_MNEMONIC(fstenv, "fstenv m14/m28byte");
-    IEM_MC_BEGIN(3, 0, 0);
+    IEM_MC_BEGIN(3, 0, 0, 0);
     IEM_MC_ARG_CONST(IEMMODE,           enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize,  0);
     IEM_MC_ARG(uint8_t,                 iEffSeg,                                    1);
@@ -9196 +9199 @@
 {
     IEMOP_MNEMONIC(fnstcw_m2byte, "fnstcw m2byte");
-    IEM_MC_BEGIN(2, 0, 0);
+    IEM_MC_BEGIN(2, 0, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fcw);
@@ -9214 +9217 @@
 {
     IEMOP_MNEMONIC(fnop, "fnop");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -9233 +9236 @@
     /** @todo Testcase: Check if this raises \#MF?  Intel mentioned it not. AMD
      *        indicates that it does. */
-    IEM_MC_BEGIN(0, 2, 0);
+    IEM_MC_BEGIN(0, 2, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value);
@@ -9259 +9262 @@
     /** @todo Testcase: Check if this raises \#MF?  Intel mentioned it not. AMD
      *        indicates that it does. */
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value1);
@@ -9292 +9295 @@
     if (!iDstReg)
     {
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL_CONST(uint16_t,        u16Fsw, /*=*/ 0);
@@ -9310 +9313 @@
     else
     {
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value);
@@ -9339 +9342 @@
 FNIEMOP_DEF_1(iemOpHlpFpu_st0, PFNIEMAIMPLFPUR80UNARY, pfnAImpl)
 {
-    IEM_MC_BEGIN(2, 1, 0);
+    IEM_MC_BEGIN(2, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -9380 +9383 @@
 {
     IEMOP_MNEMONIC(ftst_st0, "ftst st0");
-    IEM_MC_BEGIN(2, 1, 0);
+    IEM_MC_BEGIN(2, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -9405 +9408 @@
 {
     IEMOP_MNEMONIC(fxam_st0, "fxam st0");
-    IEM_MC_BEGIN(2, 1, 0);
+    IEM_MC_BEGIN(2, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -9430 +9433 @@
 FNIEMOP_DEF_1(iemOpHlpFpuPushConstant, PFNIEMAIMPLFPUR80LDCONST, pfnAImpl)
 {
-    IEM_MC_BEGIN(1, 1, 0);
+    IEM_MC_BEGIN(1, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -9528 +9531 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -9567 +9570 @@
 FNIEMOP_DEF_1(iemOpHlpFpuReplace_st0_push, PFNIEMAIMPLFPUR80UNARYTWO, pfnAImpl)
 {
-    IEM_MC_BEGIN(2, 1, 0);
+    IEM_MC_BEGIN(2, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULTTWO,           FpuResTwo);
@@ -9627 +9630 @@
     /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
      *        FINCSTP and FDECSTP. */
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
@@ -9649 +9652 @@
     /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
      *        FINCSTP and FDECSTP. */
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
@@ -9816 +9819 @@
 {
     IEMOP_MNEMONIC(fcmovb_st0_stN, "fcmovb st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -9842 +9845 @@
 {
     IEMOP_MNEMONIC(fcmove_st0_stN, "fcmove st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -9868 +9871 @@
 {
     IEMOP_MNEMONIC(fcmovbe_st0_stN, "fcmovbe st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -9894 +9897 @@
 {
     IEMOP_MNEMONIC(fcmovu_st0_stN, "fcmovu st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -9924 +9927 @@
 FNIEMOP_DEF_1(iemOpHlpFpuNoStore_st0_st1_pop_pop, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -9964 +9967 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_st0_m32i, uint8_t, bRm, PFNIEMAIMPLFPUI32, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
@@ -10013 +10016 @@
     IEMOP_MNEMONIC(ficom_st0_m32i, "ficom st0,m32i");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,                  u16Fsw);
@@ -10046 +10049 @@
     IEMOP_MNEMONIC(ficomp_st0_m32i, "ficomp st0,m32i");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,                  u16Fsw);
@@ -10154 +10157 @@
     IEMOP_MNEMONIC(fild_m32i, "fild m32i");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
@@ -10185 +10188 @@
 {
     IEMOP_MNEMONIC(fisttp_m32i, "fisttp m32i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10220 +10223 @@
 {
     IEMOP_MNEMONIC(fist_m32i, "fist m32i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10255 +10258 @@
 {
     IEMOP_MNEMONIC(fistp_m32i, "fistp m32i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10291 +10294 @@
     IEMOP_MNEMONIC(fld_m80r, "fld m80r");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -10322 +10325 @@
 {
     IEMOP_MNEMONIC(fstp_m80r, "fstp m80r");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10357 +10360 @@
 {
     IEMOP_MNEMONIC(fcmovnb_st0_stN, "fcmovnb st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -10383 +10386 @@
 {
     IEMOP_MNEMONIC(fcmovne_st0_stN, "fcmovne st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -10409 +10412 @@
 {
     IEMOP_MNEMONIC(fcmovnbe_st0_stN, "fcmovnbe st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -10435 +10438 @@
 {
     IEMOP_MNEMONIC(fcmovnnu_st0_stN, "fcmovnnu st0,stN");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,      pr80ValueN);
@@ -10461 +10464 @@
 {
     IEMOP_MNEMONIC(fneni, "fneni (8087/ign)");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10473 +10476 @@
 {
     IEMOP_MNEMONIC(fndisi, "fndisi (8087/ign)");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10485 +10488 @@
 {
     IEMOP_MNEMONIC(fnclex, "fnclex");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10508 +10511 @@
 {
     IEMOP_MNEMONIC(fnsetpm, "fnsetpm (80287/ign)");   /* set protected mode on fpu. */
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10521 +10524 @@
     IEMOP_MNEMONIC(frstpm, "frstpm (80287XL/ign)"); /* reset pm, back to real mode. */
 #if 0 /* #UDs on newer CPUs */
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -10615 +10618 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -10695 +10698 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_ST0_m64r, uint8_t, bRm, PFNIEMAIMPLFPUR64, pfnImpl)
 {
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -10743 +10746 @@
     IEMOP_MNEMONIC(fcom_st0_m64r, "fcom st0,m64r");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10776 +10779 @@
     IEMOP_MNEMONIC(fcomp_st0_m64r, "fcomp st0,m64r");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10882 +10885 @@
     IEMOP_MNEMONIC(fld_m64r, "fld m64r");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,          FpuRes);
@@ -10912 +10915 @@
 {
     IEMOP_MNEMONIC(fisttp_m64i, "fisttp m64i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10947 +10950 @@
 {
     IEMOP_MNEMONIC(fst_m64r, "fst m64r");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -10984 +10987 @@
 {
     IEMOP_MNEMONIC(fstp_m64r, "fstp m64r");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -11019 +11022 @@
 {
     IEMOP_MNEMONIC(frstor, "frstor m94/108byte");
-    IEM_MC_BEGIN(3, 0, 0);
+    IEM_MC_BEGIN(3, 0, 0, 0);
     IEM_MC_ARG_CONST(IEMMODE,           enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize,  0);
     IEM_MC_ARG(uint8_t,                 iEffSeg,                                    1);
@@ -11037 +11040 @@
 {
     IEMOP_MNEMONIC(fnsave, "fnsave m94/108byte");
-    IEM_MC_BEGIN(3, 0, 0);
+    IEM_MC_BEGIN(3, 0, 0, 0);
     IEM_MC_ARG_CONST(IEMMODE,           enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize,  0);
     IEM_MC_ARG(uint8_t,                 iEffSeg,                                    1);
@@ -11055 +11058 @@
     IEMOP_MNEMONIC(fnstsw_m16, "fnstsw m16");
 
-    IEM_MC_BEGIN(0, 2, 0);
+    IEM_MC_BEGIN(0, 2, 0, 0);
     IEM_MC_LOCAL(uint16_t, u16Tmp);
     IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst);
@@ -11081 +11084 @@
     /* Note! C0, C1, C2 and C3 are documented as undefined, we leave the
              unmodified. */
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
@@ -11100 +11103 @@
 {
     IEMOP_MNEMONIC(fst_st0_stN, "fst st0,stN");
-    IEM_MC_BEGIN(0, 2, 0);
+    IEM_MC_BEGIN(0, 2, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(PCRTFLOAT80U,          pr80Value);
@@ -11241 +11244 @@
 FNIEMOP_DEF_2(iemOpHlpFpu_st0_m16i, uint8_t, bRm, PFNIEMAIMPLFPUI16, pfnAImpl)
 {
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
@@ -11290 +11293 @@
     IEMOP_MNEMONIC(ficom_st0_m16i, "ficom st0,m16i");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,                  u16Fsw);
@@ -11323 +11326 @@
     IEMOP_MNEMONIC(ficomp_st0_m16i, "ficomp st0,m16i");
 
-    IEM_MC_BEGIN(3, 3, 0);
+    IEM_MC_BEGIN(3, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(uint16_t,                  u16Fsw);
@@ -11430 +11433 @@
 {
     IEMOP_MNEMONIC(ffreep_stN, "ffreep stN");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
 
@@ -11450 +11453 @@
 {
     IEMOP_MNEMONIC(fnstsw_ax, "fnstsw ax");
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_LOCAL(uint16_t, u16Tmp);
@@ -11487 +11490 @@
     IEMOP_MNEMONIC(fild_m16i, "fild m16i");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
@@ -11518 +11521 @@
 {
     IEMOP_MNEMONIC(fisttp_m16i, "fisttp m16i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -11553 +11556 @@
 {
     IEMOP_MNEMONIC(fist_m16i, "fist m16i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -11588 +11591 @@
 {
     IEMOP_MNEMONIC(fistp_m16i, "fistp m16i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -11624 +11627 @@
     IEMOP_MNEMONIC(fbld_m80d, "fbld m80d");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
@@ -11656 +11659 @@
     IEMOP_MNEMONIC(fild_m64i, "fild m64i");
 
-    IEM_MC_BEGIN(2, 3, 0);
+    IEM_MC_BEGIN(2, 3, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     IEM_MC_LOCAL(IEMFPURESULT,              FpuRes);
@@ -11687 +11690 @@
 {
     IEMOP_MNEMONIC(fbstp_m80d, "fbstp m80d");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -11722 +11725 @@
 {
     IEMOP_MNEMONIC(fistp_m64i, "fistp m64i");
-    IEM_MC_BEGIN(3, 2, 0);
+    IEM_MC_BEGIN(3, 2, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,               GCPtrEffDst);
     IEM_MC_LOCAL(uint16_t,              u16Fsw);
@@ -11807 +11810 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
@@ -11819 +11822 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
@@ -11831 +11834 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
@@ -11859 +11862 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
@@ -11871 +11874 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
@@ -11883 +11886 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
@@ -11921 +11924 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT);
+                IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0);
@@ -11929 +11932 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0);
@@ -11937 +11940 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0);
@@ -11951 +11954 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
@@ -11963 +11966 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
@@ -11975 +11978 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
@@ -12003 +12006 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_CX_IS_NZ() {
@@ -12014 +12017 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_ECX_IS_NZ() {
@@ -12025 +12028 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_IF_RCX_IS_NZ() {
@@ -12128 +12131 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 0, 0);
+            IEM_MC_BEGIN(0, 0, 0, 0);
             int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -12137 +12140 @@
         case IEMMODE_64BIT:
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
             int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -12180 +12183 @@
     IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX();
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
@@ -12315 +12318 @@
 {
     IEMOP_MNEMONIC(cmc, "cmc");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_FLIP_EFL_BIT(X86_EFL_CF);
@@ -12330 +12333 @@
     { \
         /* register access */ \
-        IEM_MC_BEGIN(2, 0, 0); \
+        IEM_MC_BEGIN(2, 0, 0, 0); \
         IEMOP_HLP_DONE_DECODING(); \
         IEM_MC_ARG(uint8_t *,   pu8Dst, 0); \
@@ -12345 +12348 @@
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \
         { \
-            IEM_MC_BEGIN(2, 2, 0); \
+            IEM_MC_BEGIN(2, 2, 0, 0); \
             IEM_MC_ARG(uint8_t *,       pu8Dst,          0); \
             IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12364 +12367 @@
         else \
         { \
-            IEM_MC_BEGIN(2, 2, 0); \
+            IEM_MC_BEGIN(2, 2, 0, 0); \
             IEM_MC_ARG(uint8_t *,       pu8Dst,          0); \
             IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12397 +12400 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(2, 0, 0); \
+                IEM_MC_BEGIN(2, 0, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,  pu16Dst, 0); \
@@ -12409 +12412 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,  pu32Dst, 0); \
@@ -12422 +12425 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,  pu64Dst, 0); \
@@ -12446 +12449 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(2, 3, 0); \
+                    IEM_MC_BEGIN(2, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *,      pu16Dst,         0); \
                     IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12465 +12468 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(2, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(2, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,      pu32Dst,         0); \
                     IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12484 +12487 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(2, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(2, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,      pu64Dst,         0); \
                     IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12513 +12516 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(2, 3, 0); \
+                    IEM_MC_BEGIN(2, 3, 0, 0); \
                     IEM_MC_ARG(uint16_t *,      pu16Dst,         0); \
                     IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12532 +12535 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(2, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(2, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,      pu32Dst,         0); \
                     IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12551 +12554 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(2, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(2, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,      pu64Dst,         0); \
                     IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 1); \
@@ -12590 +12593 @@
         /* register access */
         uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
-        IEM_MC_BEGIN(3, 0, 0);
+        IEM_MC_BEGIN(3, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint8_t *,       pu8Dst,             0);
@@ -12604 +12607 @@
     {
         /* memory access. */
-        IEM_MC_BEGIN(3, 3, 0);
+        IEM_MC_BEGIN(3, 3, 0, 0);
         IEM_MC_ARG(uint8_t const *, pu8Dst,             0);
         IEM_MC_ARG(uint8_t,         u8Src,              1);
@@ -12633 +12636 @@
     {
         /* register access */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint16_t *,      pu16AX,     0);
@@ -12655 +12658 @@
     {
         /* memory access. */
-        IEM_MC_BEGIN(3, 2, 0);
+        IEM_MC_BEGIN(3, 2, 0, 0);
         IEM_MC_ARG(uint16_t *,      pu16AX,     0);
         IEM_MC_ARG(uint8_t,         u8Value,    1);
@@ -12690 +12693 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 1, 0);
+                IEM_MC_BEGIN(4, 1, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16AX,     0);
@@ -12713 +12716 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32AX,     0);
@@ -12738 +12741 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64AX,     0);
@@ -12769 +12772 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 2, 0);
+                IEM_MC_BEGIN(4, 2, 0, 0);
                 IEM_MC_ARG(uint16_t *,      pu16AX,     0);
                 IEM_MC_ARG(uint16_t *,      pu16DX,     1);
@@ -12794 +12797 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,      pu32AX,     0);
                 IEM_MC_ARG(uint32_t *,      pu32DX,     1);
@@ -12821 +12824 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,      pu64AX,     0);
                 IEM_MC_ARG(uint64_t *,      pu64DX,     1);
@@ -12918 +12921 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, 0);
+                IEM_MC_BEGIN(3, 0, 0, 0);
                 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -12932 +12935 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -12947 +12950 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -12969 +12972 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 3, 0);
+                IEM_MC_BEGIN(3, 3, 0, 0);
                 IEM_MC_ARG(uint16_t const *, pu16Dst,           0);
                 IEM_MC_ARG(uint16_t,         u16Src,            1);
@@ -12991 +12994 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t const *, pu32Dst,           0);
                 IEM_MC_ARG(uint32_t,         u32Src,            1);
@@ -13013 +13016 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t const *, pu64Dst,           0);
                 IEM_MC_ARG(uint64_t,         u64Src,            1);
@@ -13097 +13100 @@
 {
     IEMOP_MNEMONIC(clc, "clc");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_CLEAR_EFL_BIT(X86_EFL_CF);
@@ -13111 +13114 @@
 {
     IEMOP_MNEMONIC(stc, "stc");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_SET_EFL_BIT(X86_EFL_CF);
@@ -13134 +13137 @@
     IEMOP_MNEMONIC(sti, "sti");
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-    IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_CHECK_IRQ_AFTER | IEM_CIMPL_F_VMEXIT, iemCImpl_sti);
+    IEM_MC_DEFER_TO_CIMPL_0_RET(  IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_CHECK_IRQ_AFTER
+                                | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_INHIBIT_SHADOW, iemCImpl_sti);
 }
 
@@ -13144 +13148 @@
 {
     IEMOP_MNEMONIC(cld, "cld");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_CLEAR_EFL_BIT(X86_EFL_DF);
@@ -13158 +13162 @@
 {
     IEMOP_MNEMONIC(std, "std");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_SET_EFL_BIT(X86_EFL_DF);
@@ -13238 +13242 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(1, 0, 0);
+                IEM_MC_BEGIN(1, 0, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t, u16Target, 0);
@@ -13247 +13251 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t, u32Target, 0);
@@ -13256 +13260 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t, u64Target, 0);
@@ -13273 +13277 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(1, 1, 0);
+                IEM_MC_BEGIN(1, 1, 0, 0);
                 IEM_MC_ARG(uint16_t,  u16Target, 0);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -13284 +13288 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t,  u32Target, 0);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -13295 +13299 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(1, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(1, 1, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t,  u64Target, 0);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -13328 +13332 @@
     { \
         case IEMMODE_16BIT: \
-            IEM_MC_BEGIN(3, 1, 0); \
+            IEM_MC_BEGIN(3, 1, 0, 0); \
             IEM_MC_ARG(uint16_t,        u16Sel,                         0); \
             IEM_MC_ARG(uint16_t,        offSeg,                         1); \
@@ -13344 +13348 @@
         \
         case IEMMODE_32BIT: \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0); \
             IEM_MC_ARG(uint16_t,        u16Sel,                         0); \
             IEM_MC_ARG(uint32_t,        offSeg,                         1); \
@@ -13361 +13365 @@
         case IEMMODE_64BIT: \
             Assert(!IEM_IS_GUEST_CPU_AMD(pVCpu)); \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
             IEM_MC_ARG(uint16_t,        u16Sel,                         0); \
             IEM_MC_ARG(uint64_t,        offSeg,                         1); \
@@ -13405 +13409 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, 0);
+                IEM_MC_BEGIN(0, 1, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Target);
@@ -13414 +13418 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Target);
@@ -13423 +13427 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Target);
@@ -13440 +13444 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, 0);
+                IEM_MC_BEGIN(0, 2, 0, 0);
                 IEM_MC_LOCAL(uint16_t, u16Target);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -13451 +13455 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Target);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -13462 +13466 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Target);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -13506 +13510 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEM_MC_LOCAL(uint16_t,  u16Src);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -13518 +13522 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386 | IEM_MC_F_NOT_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,  u32Src);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -13530 +13534 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint64_t,  u64Src);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

@@ -1371 +1371 @@
     def __init__(self, oInstr): # type: (InstructionTest, Instruction)
         self.oInstr         = oInstr    # type: InstructionTest
-        self.aoInputs       = []        # type: list(TestInOut)
-        self.aoOutputs      = []        # type: list(TestInOut)
-        self.aoSelectors    = []        # type: list(TestSelector)
+        self.aoInputs       = []        # type: List[TestInOut]
+        self.aoOutputs      = []        # type: List[TestInOut]
+        self.aoSelectors    = []        # type: List[TestSelector]
 
     def toString(self, fRepr = False):
@@ -1433 +1433 @@
         self.sMnemonic      = None;
         self.sBrief         = None;
-        self.asDescSections = []        # type: list(str)
-        self.aoMaps         = []        # type: list(InstructionMap)
-        self.aoOperands     = []        # type: list(Operand)
+        self.asDescSections = []        # type: List[str]
+        self.aoMaps         = []        # type: List[InstructionMap]
+        self.aoOperands     = []        # type: List[Operand]
         self.sPrefix        = None;     ##< Single prefix: None, 'none', 0x66, 0xf3, 0xf2
         self.sOpcode        = None      # type: str
@@ -1449 +1449 @@
         self.asCpuIds       = [];       ##< The CPUID feature bit names for this instruction. If multiple, assume AND.
         self.asReqFeatures  = [];       ##< Which features are required to be enabled to run this instruction.
-        self.aoTests        = []        # type: list(InstructionTest)
+        self.aoTests        = []        # type: List[InstructionTest]
         self.sMinCpu        = None;     ##< Indicates the minimum CPU required for the instruction. Not set when oCpuExpr is.
         self.oCpuExpr       = None;     ##< Some CPU restriction expression...
@@ -1664 +1664 @@
 
 ## All the instructions.
-g_aoAllInstructions = []            # type: list(Instruction)
+g_aoAllInstructions = []            # type: List[Instruction]
 
 ## All the instructions indexed by statistics name (opstat).
-g_dAllInstructionsByStat = {}       # type: dict(Instruction)
+g_dAllInstructionsByStat = {}       # type: Dict[Instruction]
 
 ## All the instructions indexed by function name (opfunction).
-g_dAllInstructionsByFunction = {}   # type: dict(list(Instruction))
+g_dAllInstructionsByFunction = {}   # type: Dict[List[Instruction]]
 
 ## Instructions tagged by oponlytest
-g_aoOnlyTestInstructions = []       # type: list(Instruction)
+g_aoOnlyTestInstructions = []       # type: List[Instruction]
 
 ## Instruction maps.
@@ -1759 +1759 @@
         self.iBeginLine   = iBeginLine;             ##< The start line.
         self.iEndLine     = -1;                     ##< The line the function (probably) ends on.
-        self.asLines      = [] # type: list(str)    ##< The raw lines the function is made up of.
+        self.asLines      = [] # type: List[str]    ##< The raw lines the function is made up of.
 
     def complete(self, iEndLine, asLines):
@@ -1949 +1949 @@
     'IEM_MC_F_64BIT':               ('IEM_MC_F_NOT_286_OR_OLDER',),
     'IEM_MC_F_NOT_64BIT':           (),
+};
+## IEM_MC_F_XXX values.
+g_kdCImplFlags = {
+    'IEM_CIMPL_F_BRANCH_DIRECT':        (),
+    'IEM_CIMPL_F_BRANCH_INDIRECT':      (),
+    'IEM_CIMPL_F_BRANCH_RELATIVE':      (),
+    'IEM_CIMPL_F_BRANCH_CONDITIONAL':   (),
+    'IEM_CIMPL_F_BRANCH_FAR':           (),
+    'IEM_CIMPL_F_BRANCH_ANY':           ('IEM_CIMPL_F_BRANCH_DIRECT', 'IEM_CIMPL_F_BRANCH_INDIRECT',
+                                         'IEM_CIMPL_F_BRANCH_RELATIVE',),
+    'IEM_CIMPL_F_MODE':                 (),
+    'IEM_CIMPL_F_RFLAGS':               (),
+    'IEM_CIMPL_F_INHIBIT_SHADOW':       (),
+    'IEM_CIMPL_F_STATUS_FLAGS':         (),
+    'IEM_CIMPL_F_CHECK_IRQ_AFTER':      (),
+    'IEM_CIMPL_F_CHECK_IRQ_BEFORE':     (),
+    'IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER': ('IEM_CIMPL_F_CHECK_IRQ_BEFORE', 'IEM_CIMPL_F_CHECK_IRQ_AFTER',),
+    'IEM_CIMPL_F_VMEXIT':               (),
+    'IEM_CIMPL_F_FPU':                  (),
+    'IEM_CIMPL_F_REP':                  (),
+    'IEM_CIMPL_F_IO':                   (),
+    'IEM_CIMPL_F_END_TB':               (),
+    'IEM_CIMPL_F_XCPT':                 ('IEM_CIMPL_F_BRANCH_INDIRECT', 'IEM_CIMPL_F_BRANCH_FAR',
+                                         'IEM_CIMPL_F_MODE', 'IEM_CIMPL_F_RFLAGS', 'IEM_CIMPL_F_VMEXIT', ),
 };
 class McBlock(object):
@@ -1976 +2000 @@
         self.cchIndent    = cchIndent if cchIndent else offBeginLine;
         ##< The raw lines the block is made up of.
-        self.asLines      = []              # type: list(str)
+        self.asLines      = []              # type: List[str]
         ## IEM_MC_BEGIN: Argument count.
         self.cArgs        = -1;
@@ -1982 +2006 @@
         self.cLocals      = -1;
         ## IEM_MC_BEGIN: IEM_MC_F_XXX dictionary
-        self.dMcFlags     = {}              # type: dict(str)
+        self.dsMcFlags    = {}              # type: Dict[str, bool]
+        ## IEM_MC_[DEFER_TO|CALL]_CIMPL_XXX: IEM_CIMPL_F_XXX dictionary
+        self.dsCImplFlags = {}              # type: Dict[str, bool]
         ## Decoded statements in the block.
-        self.aoStmts      = []              # type: list(McStmt)
+        self.aoStmts      = []              # type: List[McStmt]
 
     def complete(self, iEndLine, offEndLine, offAfterEnd, asLines):
@@ -2029 +2055 @@
     def parseMcBegin(oSelf, sName, asParams):
         """ IEM_MC_BEGIN """
-        oSelf.checkStmtParamCount(sName, asParams, 3);
-        if oSelf.cArgs != -1  or  oSelf.cLocals != -1  or  oSelf.dMcFlags:
+        oSelf.checkStmtParamCount(sName, asParams, 4);
+        if oSelf.cArgs != -1  or  oSelf.cLocals != -1  or  oSelf.dsMcFlags:
             oSelf.raiseStmtError(sName, 'Used more than once!');
         oSelf.cArgs   = int(asParams[0]);
         oSelf.cLocals = int(asParams[1]);
+
         if asParams[2] != '0':
             for sFlag in asParams[2].split('|'):
                 sFlag = sFlag.strip();
-                if sFlag in g_kdMcFlags:
-                    oSelf.dMcFlags[sFlag] = True;
-                    for sFlag2 in g_kdMcFlags[sFlag]:
-                        oSelf.dMcFlags[sFlag2] = True;
-                else:
+                if sFlag not in g_kdMcFlags:
                     oSelf.raiseStmtError(sName, 'Unknown flag: %s' % (sFlag, ));
+                oSelf.dsMcFlags[sFlag] = True;
+                for sFlag2 in g_kdMcFlags[sFlag]:
+                    oSelf.dsMcFlags[sFlag2] = True;
+
+        if asParams[3] != '0':
+            oSelf.parseCImplFlags(sName, asParams[3]);
 
         return McBlock.parseMcGeneric(oSelf, sName, asParams);
@@ -2129 +2158 @@
         return McStmtCall(sName, asParams, 0);
 
+    def parseCImplFlags(self, sName, sFlags):
+        """
+        Helper for parseMcCallCImpl and parseMcDeferToCImpl to validate and
+        merge a bunch of IEM_CIMPL_F_XXX value into dsCImplFlags.
+        """
+        if sFlags != '0':
+            sFlags = self.stripComments(sFlags);
+            #print('debug: %s: %s' % (self.oFunction.sName,' | '.join(''.join(sFlags.split()).split('|')),));
+            for sFlag in sFlags.split('|'):
+                sFlag = sFlag.strip();
+                #print('debug:   %s' % sFlag)
+                if sFlag not in g_kdCImplFlags:
+                    self.raiseStmtError(sName, 'Unknown flag: %s' % (sFlag, ));
+                self.dsCImplFlags[sFlag] = True;
+                for sFlag2 in g_kdCImplFlags[sFlag]:
+                    self.dsCImplFlags[sFlag2] = True;
+        return None;
+
     @staticmethod
     def parseMcCallCImpl(oSelf, sName, asParams):
@@ -2134 +2181 @@
         cArgs = int(sName[-1]);
         oSelf.checkStmtParamCount(sName, asParams, 2 + cArgs);
+        oSelf.parseCImplFlags(sName, asParams[0]);
+        return McStmtCall(sName, asParams, 1);
+
+    @staticmethod
+    def parseMcDeferToCImpl(oSelf, sName, asParams):
+        """ IEM_MC_DEFER_TO_CIMPL_[0|1|2|3]_RET """
+        #print('debug: %s, %s,...' % (sName, asParams[0],));
+        cArgs = int(sName[-5]);
+        oSelf.checkStmtParamCount(sName, asParams, 2 + cArgs);
+        oSelf.parseCImplFlags(sName, asParams[0]);
         return McStmtCall(sName, asParams, 1);
 
@@ -2601 +2658 @@
 ## IEM_MC_XXX -> parser + info dictionary.
 #
-# The info is currently a single boolean entry indicating whether the
-# statement modifies state and must not be used before IEMOP_HL_DONE_*.
+# The info columns:
+#   - col 0: boolean entry indicating whether the statement modifies state and
+#            must not be used before IEMOP_HL_DONE_*.
+#   - col 1: boolean entry indicating native recompiler support.
 #
 # The raw table was generated via the following command
@@ -2608 +2667 @@
 #       | sort | uniq | gawk "{printf """    %%-60s (%%s,        True)\n""", $1, $2}"
 g_dMcStmtParsers = {
-    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ADD_GREG_U16':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADD_GREG_U16_TO_LOCAL':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ADD_GREG_U32':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADD_GREG_U32_TO_LOCAL':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ADD_GREG_U64':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADD_GREG_U64_TO_LOCAL':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ADD_GREG_U8':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADD_GREG_U8_TO_LOCAL':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_ADVANCE_RIP_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_AND_2LOCS_U32':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_ARG_U16':                                        (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_ARG_U32':                                        (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_ARG_U64':                                        (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_GREG_U16':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_AND_GREG_U32':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_AND_GREG_U64':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_AND_GREG_U8':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_AND_LOCAL_U16':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_LOCAL_U32':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_LOCAL_U64':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_AND_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ARG':                                                (McBlock.parseMcArg,               False),
-    'IEM_MC_ARG_CONST':                                          (McBlock.parseMcArgConst,          False),
-    'IEM_MC_ARG_LOCAL_EFLAGS':                                   (McBlock.parseMcArgLocalEFlags,    False),
-    'IEM_MC_ARG_LOCAL_REF':                                      (McBlock.parseMcArgLocalRef,       False),
-    'IEM_MC_ASSIGN':                                             (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ASSIGN_TO_SMALLER':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ASSIGN_U8_SX_U64':                                   (McBlock.parseMcGeneric,           False),
-    'IEM_MC_ASSIGN_U32_SX_U64':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_BEGIN':                                              (McBlock.parseMcBegin,             False),
-    'IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX':                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_BSWAP_LOCAL_U16':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_BSWAP_LOCAL_U32':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_BSWAP_LOCAL_U64':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_CALC_RM_EFF_ADDR':                                   (McBlock.parseMcGeneric,           False),
-    'IEM_MC_CALL_AIMPL_3':                                       (McBlock.parseMcCallAImpl,         True),
-    'IEM_MC_CALL_AIMPL_4':                                       (McBlock.parseMcCallAImpl,         True),
-    'IEM_MC_CALL_AVX_AIMPL_2':                                   (McBlock.parseMcCallAvxAImpl,      True),
-    'IEM_MC_CALL_AVX_AIMPL_3':                                   (McBlock.parseMcCallAvxAImpl,      True),
-    'IEM_MC_CALL_CIMPL_0':                                       (McBlock.parseMcCallCImpl,         True),
-    'IEM_MC_CALL_CIMPL_1':                                       (McBlock.parseMcCallCImpl,         True),
-    'IEM_MC_CALL_CIMPL_2':                                       (McBlock.parseMcCallCImpl,         True),
-    'IEM_MC_CALL_CIMPL_3':                                       (McBlock.parseMcCallCImpl,         True),
-    'IEM_MC_CALL_CIMPL_4':                                       (McBlock.parseMcCallCImpl,         True),
-    'IEM_MC_CALL_CIMPL_5':                                       (McBlock.parseMcCallCImpl,         True),
-    'IEM_MC_CALL_FPU_AIMPL_1':                                   (McBlock.parseMcCallFpuAImpl,      True),
-    'IEM_MC_CALL_FPU_AIMPL_2':                                   (McBlock.parseMcCallFpuAImpl,      True),
-    'IEM_MC_CALL_FPU_AIMPL_3':                                   (McBlock.parseMcCallFpuAImpl,      True),
-    'IEM_MC_CALL_MMX_AIMPL_2':                                   (McBlock.parseMcCallMmxAImpl,      True),
-    'IEM_MC_CALL_MMX_AIMPL_3':                                   (McBlock.parseMcCallMmxAImpl,      True),
-    'IEM_MC_CALL_SSE_AIMPL_2':                                   (McBlock.parseMcCallSseAImpl,      True),
-    'IEM_MC_CALL_SSE_AIMPL_3':                                   (McBlock.parseMcCallSseAImpl,      True),
-    'IEM_MC_CALL_VOID_AIMPL_0':                                  (McBlock.parseMcCallVoidAImpl,     True),
-    'IEM_MC_CALL_VOID_AIMPL_1':                                  (McBlock.parseMcCallVoidAImpl,     True),
-    'IEM_MC_CALL_VOID_AIMPL_2':                                  (McBlock.parseMcCallVoidAImpl,     True),
-    'IEM_MC_CALL_VOID_AIMPL_3':                                  (McBlock.parseMcCallVoidAImpl,     True),
-    'IEM_MC_CALL_VOID_AIMPL_4':                                  (McBlock.parseMcCallVoidAImpl,     True),
-    'IEM_MC_CLEAR_EFL_BIT':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_CLEAR_FSW_EX':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_CLEAR_HIGH_GREG_U64':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_CLEAR_XREG_U32_MASK':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_CLEAR_YREG_128_UP':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_COMMIT_EFLAGS':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_COPY_XREG_U128':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_COPY_YREG_U128_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_COPY_YREG_U256_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_COPY_YREG_U64_ZX_VLMAX':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_DEFER_TO_CIMPL_0_RET':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_DEFER_TO_CIMPL_1_RET':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_DEFER_TO_CIMPL_2_RET':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_DEFER_TO_CIMPL_3_RET':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_END':                                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_EFLAGS':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_EFLAGS_U8':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_FCW':                                          (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_FSW':                                          (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U16':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U16_SX_U32':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U16_SX_U64':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U16_ZX_U32':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U16_ZX_U64':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U32':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U32_SX_U64':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U32_ZX_U64':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U64':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U64_ZX_U64':                              (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8_SX_U16':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8_SX_U32':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8_SX_U64':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8_ZX_U16':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8_ZX_U32':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_GREG_U8_ZX_U64':                               (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_MEM_D80':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_I16':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_I32':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_I64':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_R32':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_R64':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_R80':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_S32_SX_U64':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U128':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U128_NO_AC':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U16':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U16_DISP':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U16_SX_U32':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U16_SX_U64':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U16_ZX_U32':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U16_ZX_U64':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U256':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U256_ALIGN_AVX':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U256_NO_AC':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U32':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U32_DISP':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U32_SX_U64':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U32_ZX_U64':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U64':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U64_ALIGN_U128':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U64_DISP':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8_SX_U16':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8_SX_U32':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8_SX_U64':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8_ZX_U16':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8_ZX_U32':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_U8_ZX_U64':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_XMM':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_XMM_ALIGN_SSE':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_XMM_NO_AC':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_XMM_U32':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_XMM_U64':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_YMM':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_YMM_ALIGN_AVX':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM_YMM_NO_AC':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM16_U8':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MEM32_U8':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FETCH_MREG_U32':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_MREG_U64':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_SREG_BASE_U32':                                (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_SREG_BASE_U64':                                (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_SREG_U16':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_SREG_ZX_U32':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_SREG_ZX_U64':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_XREG_U128':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_XREG_U16':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_XREG_U32':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_XREG_U64':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_XREG_U8':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_XREG_XMM':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_YREG_2ND_U64':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_YREG_U128':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_YREG_U256':                                    (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_YREG_U32':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FETCH_YREG_U64':                                     (McBlock.parseMcGeneric,           False),
-    'IEM_MC_FLIP_EFL_BIT':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_FROM_MMX_MODE':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_DEC_TOP':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_FREE':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_INC_TOP':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_PUSH_OVERFLOW':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP':                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO':                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_UNDERFLOW':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP':                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP':                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP':                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_FPU_TO_MMX_MODE':                                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_IF_CX_IS_NZ':                                        (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET':                    (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET':                        (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_ECX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET':                   (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET':                       (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_ANY_BITS_SET':                                (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_BIT_NOT_SET':                                 (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ':                     (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_BIT_SET':                                     (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE':                          (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_BITS_EQ':                                     (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_BITS_NE':                                     (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_EFL_NO_BITS_SET':                                 (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_FCW_IM':                                          (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_FPUREG_IS_EMPTY':                                 (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_FPUREG_NOT_EMPTY':                                (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80':                        (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_GREG_BIT_SET':                                    (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_LOCAL_IS_Z':                                      (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_MXCSR_XCPT_PENDING':                              (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_RCX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET':                   (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET':                       (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80':                   (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST':             (McBlock.parseMcGenericCond,       True),
-    'IEM_MC_IMPLICIT_AVX_AIMPL_ARGS':                            (McBlock.parseMcGeneric,           False),
-    'IEM_MC_INT_CLEAR_ZMM_256_UP':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_LOCAL':                                              (McBlock.parseMcLocal,             False),
-    'IEM_MC_LOCAL_CONST':                                        (McBlock.parseMcLocalConst,        False),
-    'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE':                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_FPU_XCPT':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0':                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE':              (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_COMMIT_AND_UNMAP':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_COMMIT_AND_UNMAP_RW':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_COMMIT_AND_UNMAP_RO':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_COMMIT_AND_UNMAP_WO':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE':                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP':                                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_EX':                                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U8_RW':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U8_RO':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U8_WO':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U16_RW':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U16_RO':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U16_WO':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U32_RW':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U32_RO':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U32_WO':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U64_RW':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U64_RO':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MEM_MAP_U64_WO':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX':                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX':                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX':                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX':                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MODIFIED_MREG':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_MODIFIED_MREG_BY_REF':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_OR_2LOCS_U32':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_OR_GREG_U16':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_OR_GREG_U32':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_OR_GREG_U64':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_OR_GREG_U8':                                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_OR_LOCAL_U16':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_OR_LOCAL_U32':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_OR_LOCAL_U8':                                        (McBlock.parseMcGeneric,           False),
-    'IEM_MC_POP_U16':                                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_POP_U32':                                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_POP_U64':                                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PREPARE_AVX_USAGE':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_PREPARE_FPU_USAGE':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_PREPARE_SSE_USAGE':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_PUSH_FPU_RESULT':                                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PUSH_FPU_RESULT_MEM_OP':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PUSH_FPU_RESULT_TWO':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PUSH_U16':                                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PUSH_U32':                                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PUSH_U32_SREG':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_PUSH_U64':                                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_RAISE_DIVIDE_ERROR':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED':                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_REF_EFLAGS':                                         (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_FPUREG':                                         (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_I32':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_I32_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_I64':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_I64_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U16':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U16_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U32':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U64':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U8':                                        (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_GREG_U8_CONST':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_LOCAL':                                          (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_MREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_MREG_U64':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_MREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_MXCSR':                                          (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_R32_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_R64_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_U128':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_U128_CONST':                                (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_XREG_XMM_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_YREG_U128':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_YREG_U128_CONST':                                (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REF_YREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False),
-    'IEM_MC_REL_JMP_S16_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_REL_JMP_S32_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_REL_JMP_S8_AND_FINISH':                              (McBlock.parseMcGeneric,           True),
-    'IEM_MC_RETURN_ON_FAILURE':                                  (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SAR_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SAR_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SAR_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SET_EFL_BIT':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SET_FPU_RESULT':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SET_RIP_U16_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SET_RIP_U32_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SET_RIP_U64_AND_FINISH':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SHL_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SHL_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SHL_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SHR_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False),
-    'IEM_MC_SSE_UPDATE_MXCSR':                                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_FPU_RESULT':                                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_FPU_RESULT_MEM_OP':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_FPU_RESULT_THEN_POP':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP':              (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_FPUREG_R80_SRC_REF':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_I64':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U16':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U16_CONST':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U32':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U32_CONST':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U64':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U64_CONST':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U8':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_GREG_U8_CONST':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_I16_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_I32_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_I64_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_I8_CONST_BY_REF':                          (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_INDEF_D80_BY_REF':                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF':                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF':                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF':                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U128':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U16':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U16_CONST':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U256':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U256_ALIGN_AVX':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U32':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U32_CONST':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U64':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U64_CONST':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U8':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MEM_U8_CONST':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MREG_U32_ZX_U64':                              (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_MREG_U64':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_SREG_BASE_U32':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_SREG_BASE_U64':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_SSE_RESULT':                                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_HI_U64':                                  (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_R32':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_R64':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U128':                                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U16':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U32':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U32_U128':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U32_ZX_U128':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U64':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U64_ZX_U128':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_U8':                                      (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_XMM':                                     (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_XMM_U32':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_XREG_XMM_U64':                                 (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_YREG_U128':                                    (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_YREG_U128_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_YREG_U256_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_YREG_U32_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_STORE_YREG_U64_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SUB_GREG_U16':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SUB_GREG_U32':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SUB_GREG_U64':                                       (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SUB_GREG_U8':                                        (McBlock.parseMcGeneric,           True),
-    'IEM_MC_SUB_LOCAL_U16':                                      (McBlock.parseMcGeneric,           False),
-    'IEM_MC_UPDATE_FPU_OPCODE_IP':                               (McBlock.parseMcGeneric,           True),
-    'IEM_MC_UPDATE_FSW':                                         (McBlock.parseMcGeneric,           True),
-    'IEM_MC_UPDATE_FSW_CONST':                                   (McBlock.parseMcGeneric,           True),
-    'IEM_MC_UPDATE_FSW_THEN_POP':                                (McBlock.parseMcGeneric,           True),
-    'IEM_MC_UPDATE_FSW_THEN_POP_POP':                            (McBlock.parseMcGeneric,           True),
-    'IEM_MC_UPDATE_FSW_WITH_MEM_OP':                             (McBlock.parseMcGeneric,           True),
-    'IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP':                    (McBlock.parseMcGeneric,           True),
+    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE':                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ':                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ADD_GREG_U16':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADD_GREG_U16_TO_LOCAL':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ADD_GREG_U32':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADD_GREG_U32_TO_LOCAL':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ADD_GREG_U64':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADD_GREG_U64_TO_LOCAL':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ADD_GREG_U8':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADD_GREG_U8_TO_LOCAL':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_ADVANCE_RIP_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  True,  ),
+    'IEM_MC_AND_2LOCS_U32':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_ARG_U16':                                        (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_ARG_U32':                                        (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_ARG_U64':                                        (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_GREG_U16':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_AND_GREG_U32':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_AND_GREG_U64':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_AND_GREG_U8':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_AND_LOCAL_U16':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_LOCAL_U32':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_LOCAL_U64':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_AND_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ARG':                                                (McBlock.parseMcArg,               False, False, ),
+    'IEM_MC_ARG_CONST':                                          (McBlock.parseMcArgConst,          False, False, ),
+    'IEM_MC_ARG_LOCAL_EFLAGS':                                   (McBlock.parseMcArgLocalEFlags,    False, False, ),
+    'IEM_MC_ARG_LOCAL_REF':                                      (McBlock.parseMcArgLocalRef,       False, False, ),
+    'IEM_MC_ASSIGN':                                             (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ASSIGN_TO_SMALLER':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ASSIGN_U8_SX_U64':                                   (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_ASSIGN_U32_SX_U64':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_BEGIN':                                              (McBlock.parseMcBegin,             False, True,  ),
+    'IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX':                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_BSWAP_LOCAL_U16':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_BSWAP_LOCAL_U32':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_BSWAP_LOCAL_U64':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR':                                   (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_CALL_AIMPL_3':                                       (McBlock.parseMcCallAImpl,         True,  False, ),
+    'IEM_MC_CALL_AIMPL_4':                                       (McBlock.parseMcCallAImpl,         True,  False, ),
+    'IEM_MC_CALL_AVX_AIMPL_2':                                   (McBlock.parseMcCallAvxAImpl,      True,  False, ),
+    'IEM_MC_CALL_AVX_AIMPL_3':                                   (McBlock.parseMcCallAvxAImpl,      True,  False, ),
+    'IEM_MC_CALL_CIMPL_0':                                       (McBlock.parseMcCallCImpl,         True,  False, ),
+    'IEM_MC_CALL_CIMPL_1':                                       (McBlock.parseMcCallCImpl,         True,  False, ),
+    'IEM_MC_CALL_CIMPL_2':                                       (McBlock.parseMcCallCImpl,         True,  False, ),
+    'IEM_MC_CALL_CIMPL_3':                                       (McBlock.parseMcCallCImpl,         True,  False, ),
+    'IEM_MC_CALL_CIMPL_4':                                       (McBlock.parseMcCallCImpl,         True,  False, ),
+    'IEM_MC_CALL_CIMPL_5':                                       (McBlock.parseMcCallCImpl,         True,  False, ),
+    'IEM_MC_CALL_FPU_AIMPL_1':                                   (McBlock.parseMcCallFpuAImpl,      True,  False, ),
+    'IEM_MC_CALL_FPU_AIMPL_2':                                   (McBlock.parseMcCallFpuAImpl,      True,  False, ),
+    'IEM_MC_CALL_FPU_AIMPL_3':                                   (McBlock.parseMcCallFpuAImpl,      True,  False, ),
+    'IEM_MC_CALL_MMX_AIMPL_2':                                   (McBlock.parseMcCallMmxAImpl,      True,  False, ),
+    'IEM_MC_CALL_MMX_AIMPL_3':                                   (McBlock.parseMcCallMmxAImpl,      True,  False, ),
+    'IEM_MC_CALL_SSE_AIMPL_2':                                   (McBlock.parseMcCallSseAImpl,      True,  False, ),
+    'IEM_MC_CALL_SSE_AIMPL_3':                                   (McBlock.parseMcCallSseAImpl,      True,  False, ),
+    'IEM_MC_CALL_VOID_AIMPL_0':                                  (McBlock.parseMcCallVoidAImpl,     True,  False, ),
+    'IEM_MC_CALL_VOID_AIMPL_1':                                  (McBlock.parseMcCallVoidAImpl,     True,  False, ),
+    'IEM_MC_CALL_VOID_AIMPL_2':                                  (McBlock.parseMcCallVoidAImpl,     True,  False, ),
+    'IEM_MC_CALL_VOID_AIMPL_3':                                  (McBlock.parseMcCallVoidAImpl,     True,  False, ),
+    'IEM_MC_CALL_VOID_AIMPL_4':                                  (McBlock.parseMcCallVoidAImpl,     True,  False, ),
+    'IEM_MC_CLEAR_EFL_BIT':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_CLEAR_FSW_EX':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_CLEAR_HIGH_GREG_U64':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_CLEAR_XREG_U32_MASK':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_CLEAR_YREG_128_UP':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_COMMIT_EFLAGS':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_COPY_XREG_U128':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_COPY_YREG_U128_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_COPY_YREG_U256_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_COPY_YREG_U64_ZX_VLMAX':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_DEFER_TO_CIMPL_0_RET':                               (McBlock.parseMcDeferToCImpl,      False, False, ),
+    'IEM_MC_DEFER_TO_CIMPL_1_RET':                               (McBlock.parseMcDeferToCImpl,      False, False, ),
+    'IEM_MC_DEFER_TO_CIMPL_2_RET':                               (McBlock.parseMcDeferToCImpl,      False, False, ),
+    'IEM_MC_DEFER_TO_CIMPL_3_RET':                               (McBlock.parseMcDeferToCImpl,      False, False, ),
+    'IEM_MC_END':                                                (McBlock.parseMcGeneric,           True,  True,  ),
+    'IEM_MC_FETCH_EFLAGS':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_EFLAGS_U8':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_FCW':                                          (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_FSW':                                          (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U16':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U16_SX_U32':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U16_SX_U64':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U16_ZX_U32':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U16_ZX_U64':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U32':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U32_SX_U64':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U32_ZX_U64':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U64':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U64_ZX_U64':                              (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8_SX_U16':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8_SX_U32':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8_SX_U64':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8_ZX_U16':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8_ZX_U32':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_GREG_U8_ZX_U64':                               (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_MEM_D80':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_I16':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_I32':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_I64':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_R32':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_R64':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_R80':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_S32_SX_U64':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U128':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U128_NO_AC':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U16':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U16_DISP':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U16_SX_U32':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U16_SX_U64':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U16_ZX_U32':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U16_ZX_U64':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U256':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U256_ALIGN_AVX':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U256_NO_AC':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U32':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U32_DISP':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U32_SX_U64':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U32_ZX_U64':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U64':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U64_ALIGN_U128':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U64_DISP':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8_SX_U16':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8_SX_U32':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8_SX_U64':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8_ZX_U16':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8_ZX_U32':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_U8_ZX_U64':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_XMM':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_XMM_ALIGN_SSE':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_XMM_NO_AC':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_XMM_U32':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_XMM_U64':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_YMM':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_YMM_ALIGN_AVX':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM_YMM_NO_AC':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM16_U8':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MEM32_U8':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FETCH_MREG_U32':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_MREG_U64':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_SREG_BASE_U32':                                (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_SREG_BASE_U64':                                (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_SREG_U16':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_SREG_ZX_U32':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_SREG_ZX_U64':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_XREG_U128':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_XREG_U16':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_XREG_U32':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_XREG_U64':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_XREG_U8':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_XREG_XMM':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_YREG_2ND_U64':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_YREG_U128':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_YREG_U256':                                    (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_YREG_U32':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FETCH_YREG_U64':                                     (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_FLIP_EFL_BIT':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_FROM_MMX_MODE':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_DEC_TOP':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_FREE':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_INC_TOP':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_PUSH_OVERFLOW':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP':                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO':                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_UNDERFLOW':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP':                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP':                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP':                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_FPU_TO_MMX_MODE':                                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_IF_CX_IS_NZ':                                        (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET':                    (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET':                        (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_ECX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET':                   (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET':                       (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_ANY_BITS_SET':                                (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_BIT_NOT_SET':                                 (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ':                     (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_BIT_SET':                                     (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE':                          (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_BITS_EQ':                                     (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_BITS_NE':                                     (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_EFL_NO_BITS_SET':                                 (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_FCW_IM':                                          (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_FPUREG_IS_EMPTY':                                 (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_FPUREG_NOT_EMPTY':                                (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80':                        (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_GREG_BIT_SET':                                    (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_LOCAL_IS_Z':                                      (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_MXCSR_XCPT_PENDING':                              (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_RCX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET':                   (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET':                       (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80':                   (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST':             (McBlock.parseMcGenericCond,       True,  False, ),
+    'IEM_MC_IMPLICIT_AVX_AIMPL_ARGS':                            (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_INT_CLEAR_ZMM_256_UP':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_LOCAL':                                              (McBlock.parseMcLocal,             False, False, ),
+    'IEM_MC_LOCAL_CONST':                                        (McBlock.parseMcLocalConst,        False, False, ),
+    'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE':                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_FPU_XCPT':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0':                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT':                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE':              (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP_RW':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP_RO':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP_WO':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE':                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP':                                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_EX':                                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U8_RW':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U8_RO':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U8_WO':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U16_RW':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U16_RO':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U16_WO':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U32_RW':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U32_RO':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U32_WO':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U64_RW':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U64_RO':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MEM_MAP_U64_WO':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX':                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX':                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX':                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX':                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX':                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MODIFIED_MREG':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_MODIFIED_MREG_BY_REF':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_OR_2LOCS_U32':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_OR_GREG_U16':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_OR_GREG_U32':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_OR_GREG_U64':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_OR_GREG_U8':                                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_OR_LOCAL_U16':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_OR_LOCAL_U32':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_OR_LOCAL_U8':                                        (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_POP_U16':                                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_POP_U32':                                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_POP_U64':                                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PREPARE_AVX_USAGE':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_PREPARE_FPU_USAGE':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_PREPARE_SSE_USAGE':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_PUSH_FPU_RESULT':                                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PUSH_FPU_RESULT_MEM_OP':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PUSH_FPU_RESULT_TWO':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PUSH_U16':                                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PUSH_U32':                                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PUSH_U32_SREG':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_PUSH_U64':                                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_RAISE_DIVIDE_ERROR':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED':                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_REF_EFLAGS':                                         (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_FPUREG':                                         (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_I32':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_I32_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_I64':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_I64_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U16':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U16_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U32':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U64':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U8':                                        (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_GREG_U8_CONST':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_LOCAL':                                          (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_MREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_MREG_U64':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_MREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_MXCSR':                                          (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_R32_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_R64_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_U128':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_U128_CONST':                                (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_U32_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_XREG_XMM_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_YREG_U128':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_YREG_U128_CONST':                                (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REF_YREG_U64_CONST':                                 (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_REL_JMP_S32_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_REL_JMP_S8_AND_FINISH':                              (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_RETURN_ON_FAILURE':                                  (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SAR_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SAR_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SAR_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SET_EFL_BIT':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SET_FPU_RESULT':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SET_RIP_U16_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SET_RIP_U32_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SET_RIP_U64_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SHL_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SHL_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SHL_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SHR_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_SSE_UPDATE_MXCSR':                                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_FPU_RESULT':                                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_FPU_RESULT_MEM_OP':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_FPU_RESULT_THEN_POP':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP':              (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_FPUREG_R80_SRC_REF':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_I64':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U16':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U16_CONST':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U32':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U32_CONST':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U64':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U64_CONST':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U8':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_GREG_U8_CONST':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_I16_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_I32_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_I64_CONST_BY_REF':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_I8_CONST_BY_REF':                          (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_INDEF_D80_BY_REF':                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF':                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF':                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF':                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U128':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U16':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U16_CONST':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U256':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U256_ALIGN_AVX':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U32':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U32_CONST':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U64':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U64_CONST':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U8':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MEM_U8_CONST':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MREG_U32_ZX_U64':                              (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_MREG_U64':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_SREG_BASE_U32':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_SREG_BASE_U64':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_SSE_RESULT':                                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_HI_U64':                                  (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_R32':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_R64':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U128':                                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U16':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U32':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U32_U128':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U32_ZX_U128':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U64':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U64_ZX_U128':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_U8':                                      (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_XMM':                                     (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_XMM_U32':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_XREG_XMM_U64':                                 (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_YREG_U128':                                    (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_YREG_U128_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_YREG_U256_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_YREG_U32_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_STORE_YREG_U64_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SUB_GREG_U16':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SUB_GREG_U32':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SUB_GREG_U64':                                       (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SUB_GREG_U8':                                        (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_SUB_LOCAL_U16':                                      (McBlock.parseMcGeneric,           False, False, ),
+    'IEM_MC_UPDATE_FPU_OPCODE_IP':                               (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_UPDATE_FSW':                                         (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_UPDATE_FSW_CONST':                                   (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_UPDATE_FSW_THEN_POP':                                (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_UPDATE_FSW_THEN_POP_POP':                            (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_UPDATE_FSW_WITH_MEM_OP':                             (McBlock.parseMcGeneric,           True,  False, ),
+    'IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP':                    (McBlock.parseMcGeneric,           True,  False, ),
 };
 
 ## List of microcode blocks.
-g_aoMcBlocks = [] # type: list(McBlock)
+g_aoMcBlocks = [] # type: List[McBlock]
 
 
@@ -3077 +3136 @@
         self.sComment       = '';
         self.iCommentLine   = 0;
-        self.aoCurInstrs    = []    # type: list(Instruction)
+        self.aoCurInstrs    = []    # type: List[Instruction]
         self.oCurFunction   = None  # type: DecoderFunction
         self.iMcBlockInFunc = 0;
         self.oCurMcBlock    = None  # type: McBlock
-        self.dMacros        = {}    # type: Dict[str,SimpleParser.Macro]
+        self.dMacros        = {}    # type: Dict[str, SimpleParser.Macro]
         self.oReMacros      = None  # type: re      ##< Regular expression matching invocations of anything in self.dMacros.
         if oInheritMacrosFrom:
@@ -4874 +4933 @@
                             % (sStmt, len(asArgs), cParams + 3,));
 
-        oMcBlock.aoStmts = [McStmtCall(asArgs[0], asArgs[1:], 1),];
+        oMcBlock.aoStmts = [ McBlock.parseMcDeferToCImpl(oMcBlock, asArgs[0], asArgs[1:]), ];
 
         # These MCs are not typically part of macro expansions, but let's get

trunk/src/VBox/VMM/VMMAll/IEMAllInstThree0f38.cpp.h

@@ -49 +49 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -70 +70 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -111 +111 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -128 +128 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -167 +167 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -184 +184 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -226 +226 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -243 +243 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -282 +282 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -299 +299 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -342 +342 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -359 +359 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -402 +402 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -419 +419 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -690 +690 @@
          * Register, register. \
          */ \
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
         IEM_MC_ARG(PRTUINT128U,  puDst,  0); \
@@ -712 +712 @@
          * Register, memory. \
          */ \
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER); \
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0); \
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc); \
         IEM_MC_LOCAL(RTUINT128U,                uSrc); \
@@ -785 +785 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_ARG(PCRTUINT128U,                puSrc1,  0);
@@ -804 +804 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PCRTUINT128U,                puSrc1,        0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc2);
@@ -906 +906 @@
          * Register, register. \
          */ \
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0); \
@@ -926 +926 @@
          * Register, memory. \
          */ \
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER); \
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0); \
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc); \
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0); \
@@ -1039 +1039 @@
     {
         /* Register, memory. */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1317 +1317 @@
         if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint8_t,  iEffSeg,         0);
             IEM_MC_ARG(RTGCPTR,  GCPtrInveptDesc, 1);
@@ -1333 +1333 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint8_t,  iEffSeg,         0);
             IEM_MC_ARG(RTGCPTR,  GCPtrInveptDesc, 1);
@@ -1368 +1368 @@
         if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint8_t,  iEffSeg,          0);
             IEM_MC_ARG(RTGCPTR,  GCPtrInvvpidDesc, 1);
@@ -1384 +1384 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint8_t,  iEffSeg,          0);
             IEM_MC_ARG(RTGCPTR,  GCPtrInvvpidDesc, 1);
@@ -1417 +1417 @@
         if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint8_t,  iEffSeg,          0);
             IEM_MC_ARG(RTGCPTR,  GCPtrInvpcidDesc, 1);
@@ -1430 +1430 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint8_t,  iEffSeg,          0);
             IEM_MC_ARG(RTGCPTR,  GCPtrInvpcidDesc, 1);
@@ -1577 +1577 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
         IEM_MC_ARG(PRTUINT128U,                 puDst, 0);
@@ -1597 +1597 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1742 +1742 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
                 IEM_MC_LOCAL(uint16_t,  uSrc);
                 IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -1758 +1758 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t,  uSrc);
                 IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -1774 +1774 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t,  uSrc);
                 IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -1816 +1816 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint32_t *,          puDst, 0);
@@ -1832 +1832 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint32_t *,          puDst, 0);
         IEM_MC_ARG(uint8_t,             uSrc,  1);
@@ -1867 +1867 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -1880 +1880 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -1893 +1893 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -1935 +1935 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
@@ -1949 +1949 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
@@ -1963 +1963 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
@@ -1987 +1987 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER);
+                IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
                 IEM_MC_ARG(uint16_t,            uSrc,  1);
@@ -2006 +2006 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
                 IEM_MC_ARG(uint32_t,            uSrc,  1);
@@ -2025 +2025 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(2, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(2, 1, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint32_t *,          puDst, 0);
                 IEM_MC_ARG(uint64_t,            uSrc,  1);
@@ -2081 +2081 @@
             if (IEM_IS_MODRM_REG_MODE(bRm)) \
             { \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
@@ -2096 +2096 @@
             else \
             { \
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1); \
@@ -2116 +2116 @@
             if (IEM_IS_MODRM_REG_MODE(bRm)) \
             { \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
@@ -2131 +2131 @@
             else \
             { \
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,                1); \

trunk/src/VBox/VMM/VMMAll/IEMAllInstThree0f3a.cpp.h

@@ -52 +52 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
@@ -70 +70 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -111 +111 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
@@ -129 +129 @@
          * XMM, [mem128], imm8.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -171 +171 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
@@ -196 +196 @@
          * XMM, [mem128], imm8.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -243 +243 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
@@ -261 +261 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -323 +323 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
@@ -348 +348 @@
          * XMM32, [mem32].
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -388 +388 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
@@ -413 +413 @@
          * XMM64, [mem64], imm8.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -481 +481 @@
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -502 +502 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,                0);
         IEM_MC_ARG(uint64_t,                    uSrc,                1);
@@ -553 +553 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(uint8_t,   uValue);
@@ -568 +568 @@
          * [mem8], XMM.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint8_t,   uValue);
         IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -597 +597 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(uint16_t,  uValue);
@@ -612 +612 @@
          * [mem16], XMM.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint16_t,  uValue);
         IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -648 +648 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
             IEM_MC_LOCAL(uint64_t,  uSrc);
@@ -663 +663 @@
              * [mem64], XMM.
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint64_t,  uSrc);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -695 +695 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
             IEM_MC_LOCAL(uint32_t,  uSrc);
@@ -710 +710 @@
              * [mem32], XMM.
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,  uSrc);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -739 +739 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(uint32_t,  uSrc);
@@ -754 +754 @@
          * [mem32], XMM.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t,  uSrc);
         IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -792 +792 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(uint8_t,   uSrc);
@@ -807 +807 @@
          * XMM, [mem8].
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint8_t,   uSrc);
         IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -835 +835 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(0, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
         IEM_MC_LOCAL(uint32_t,  uSrc);
@@ -859 +859 @@
          * XMM, [mem32].
          */
-        IEM_MC_BEGIN(0, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t,  uSrc);
         IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -899 +899 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
             IEM_MC_LOCAL(uint64_t,  uSrc);
@@ -914 +914 @@
              * XMM, [mem64].
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint64_t,  uSrc);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -946 +946 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
             IEM_MC_LOCAL(uint32_t,  uSrc);
@@ -961 +961 @@
              * XMM, [mem32].
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,  uSrc);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
@@ -1055 +1055 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
@@ -1076 +1076 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1147 +1147 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
             IEM_MC_ARG(PRTUINT128U,                puDst,             0);
@@ -1174 +1174 @@
              * Register, memory.
              */
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint32_t *,                  pu32Ecx,             0);
             IEM_MC_ARG(uint32_t *,                  pEFlags,             1);
@@ -1211 +1211 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
             IEM_MC_ARG(PRTUINT128U,                puDst,             0);
@@ -1238 +1238 @@
              * Register, memory.
              */
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint32_t *,                  pu32Ecx,             0);
             IEM_MC_ARG(uint32_t *,                  pEFlags,             1);
@@ -1283 +1283 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
             IEM_MC_ARG(uint32_t *,                 pu32Ecx,             0);
@@ -1311 +1311 @@
              * Register, memory.
              */
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint32_t *,                  pu32Ecx,             0);
             IEM_MC_ARG(uint32_t *,                  pEFlags,             1);
@@ -1348 +1348 @@
              */
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
             IEM_MC_ARG(uint32_t *,                 pu32Ecx,             0);
@@ -1376 +1376 @@
              * Register, memory.
              */
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint32_t *,                  pu32Ecx,             0);
             IEM_MC_ARG(uint32_t *,                  pEFlags,             1);
@@ -1420 +1420 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
         IEM_MC_ARG(PRTUINT128U,                puDst,             0);
@@ -1445 +1445 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint32_t *,                  pu32Ecx,             0);
         IEM_MC_ARG(uint32_t *,                  pEFlags,             1);
@@ -1485 +1485 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
         IEM_MC_ARG(uint32_t *,                 pu32Ecx,             0);
@@ -1511 +1511 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint32_t *,                  pu32Ecx,             0);
         IEM_MC_ARG(uint32_t *,                  pEFlags,             1);
@@ -1582 +1582 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
@@ -1603 +1603 @@
          * XMM, [mem128], imm8.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,               0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);

trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h

@@ -50 +50 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -71 +71 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -112 +112 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -133 +133 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -172 +172 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -193 +193 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -235 +235 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -256 +256 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -295 +295 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint64_t *,          pDst, 0);
@@ -316 +316 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -357 +357 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
@@ -374 +374 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 pDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -412 +412 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
@@ -429 +429 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 pDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -470 +470 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(PRTUINT128U,          pDst, 0);
@@ -487 +487 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 pDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -523 +523 @@
          * MMX, MMX.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
@@ -544 +544 @@
          * MMX, [mem32].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  puDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -585 +585 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
@@ -602 +602 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,             puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
@@ -645 +645 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
@@ -662 +662 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,             puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
@@ -705 +705 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
@@ -726 +726 @@
          * MMX, [mem64].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,                  puDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -767 +767 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
@@ -784 +784 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -827 +827 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
@@ -849 +849 @@
          * XMM128, [mem128].
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_LOCAL(X86XMMREG,             uSrc2);
@@ -891 +891 @@
          * XMM128, XMM32.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
@@ -913 +913 @@
          * XMM128, [mem32].
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_LOCAL(RTFLOAT32U,            r32Src2);
@@ -955 +955 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
@@ -977 +977 @@
          * XMM128, [mem128].
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_LOCAL(X86XMMREG,             uSrc2);
@@ -1019 +1019 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
@@ -1041 +1041 @@
          * XMM, [mem64].
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_LOCAL(RTFLOAT64U,            r64Src2);
@@ -1083 +1083 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(PRTUINT128U,             puDst, 0);
@@ -1100 +1100 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1143 +1143 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
@@ -1165 +1165 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
         IEM_MC_LOCAL(X86XMMREG,             uSrc2);
@@ -1204 +1204 @@
 
     /* Ignore operand size here, memory refs are always 16-bit. */
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286, 0);
     IEM_MC_ARG(uint16_t, iEffSeg,               0);
     IEM_MC_ARG(RTGCPTR,  GCPtrEffDst,           1);
@@ -1230 +1230 @@
 
     /* Ignore operand size here, memory refs are always 16-bit. */
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286, 0);
     IEM_MC_ARG(uint16_t, iEffSeg,               0);
     IEM_MC_ARG(RTGCPTR,  GCPtrEffDst,           1);
@@ -1250 +1250 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_286, 0);
         IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
         IEM_MC_ARG(uint16_t, u16Sel, 0);
@@ -1259 +1259 @@
     else
     {
-        IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_286, 0);
         IEM_MC_ARG(uint16_t, u16Sel, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -1281 +1281 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_286, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint16_t, u16Sel, 0);
@@ -1290 +1290 @@
     else
     {
-        IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_286, 0);
         IEM_MC_ARG(uint16_t, u16Sel, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
@@ -1311 +1311 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286, 0);
         IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
         IEM_MC_ARG(uint16_t,    u16Sel,            0);
@@ -1321 +1321 @@
     else
     {
-        IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_286, 0);
         IEM_MC_ARG(uint16_t,    u16Sel,            0);
         IEM_MC_ARG_CONST(bool,  fWriteArg, fWrite, 1);
@@ -1379 +1379 @@
     IEMOP_HLP_MIN_286();
     IEMOP_HLP_64BIT_OP_SIZE();
-    IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_286);
+    IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_286, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                    0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEffSrc,                                1);
@@ -1471 +1471 @@
     IEMOP_HLP_MIN_286();
     IEMOP_HLP_64BIT_OP_SIZE();
-    IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_286);
+    IEM_MC_BEGIN(2, 1, IEM_MC_F_MIN_286, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                    0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEffSrc,                                1);
@@ -1505 +1505 @@
     IEMOP_MNEMONIC(lgdt, "lgdt");
     IEMOP_HLP_64BIT_OP_SIZE();
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                    0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEffSrc,                                1);
@@ -1558 +1558 @@
     IEMOP_MNEMONIC(lidt, "lidt");
     IEMMODE enmEffOpSize = IEM_IS_64BIT_CODE(pVCpu) ? IEMMODE_64BIT : pVCpu->iem.s.enmEffOpSize;
-    IEM_MC_BEGIN(3, 1, 0);
+    IEM_MC_BEGIN(3, 1, 0, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                            0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEffSrc,                        1);
@@ -1690 +1690 @@
 
     /* Ignore operand size here, memory refs are always 16-bit. */
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286, 0);
     IEM_MC_ARG(uint16_t, iEffSeg,               0);
     IEM_MC_ARG(RTGCPTR,  GCPtrEffDst,           1);
@@ -1710 +1710 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint16_t, u16Tmp,                         0);
@@ -1720 +1720 @@
     else
     {
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_286, 0);
         IEM_MC_ARG(uint16_t, u16Tmp,      0);
         IEM_MC_ARG(RTGCPTR,  GCPtrEffDst, 1);
@@ -1737 +1737 @@
     IEMOP_MNEMONIC(invlpg, "invlpg");
     IEMOP_HLP_MIN_486();
-    IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_386);
+    IEM_MC_BEGIN(1, 1, IEM_MC_F_MIN_386, 0);
     IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 0);
     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -1862 +1862 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, 0);
+                IEM_MC_BEGIN(3, 0, 0, 0);
                 IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
                 IEM_MC_ARG(uint16_t *,  pu16Dst,           0);
@@ -1877 +1877 @@
             case IEMMODE_32BIT:
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
                 IEM_MC_ARG(uint64_t *,  pu64Dst,           0);
@@ -1898 +1898 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 1, 0);
+                IEM_MC_BEGIN(3, 1, 0, 0);
                 IEM_MC_ARG(uint16_t *,  pu16Dst,           0);
                 IEM_MC_ARG(uint16_t,    u16Sel,            1);
@@ -1916 +1916 @@
             case IEMMODE_32BIT:
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint64_t *,  pu64Dst,           0);
                 IEM_MC_ARG(uint16_t,    u16Sel,            1);
@@ -2044 +2044 @@
     }
 
-    IEM_MC_BEGIN(0, 1, 0);
+    IEM_MC_BEGIN(0, 1, 0, 0);
     IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc);
     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
@@ -2060 +2060 @@
     IEMOP_MNEMONIC(femms, "femms");
 
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -2109 +2109 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -2123 +2123 @@
          * XMM128, [mem128].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2160 +2160 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -2174 +2174 @@
          * XMM128, [mem128].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2210 +2210 @@
          * XMM32, XMM32.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
@@ -2227 +2227 @@
          * XMM128, [mem32].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2263 +2263 @@
          * XMM64, XMM64.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -2280 +2280 @@
          * XMM128, [mem64].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2316 +2316 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -2330 +2330 @@
          * [mem128], XMM128.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2366 +2366 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -2380 +2380 @@
          * [mem128], XMM128.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2416 +2416 @@
          * XMM32, XMM32.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
@@ -2433 +2433 @@
          * [mem32], XMM32.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2469 +2469 @@
          * XMM64, XMM64.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -2486 +2486 @@
          * [mem64], XMM64.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2521 +2521 @@
         IEMOP_MNEMONIC2(RM_REG, MOVHLPS, movhlps, Vq_WO, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -2549 +2549 @@
         IEMOP_MNEMONIC2(RM_MEM, MOVLPS, movlps, Vq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2584 +2584 @@
         IEMOP_MNEMONIC2(RM_MEM, MOVLPD, movlpd, Vq_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2633 +2633 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -2654 +2654 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2693 +2693 @@
          * XMM128, XMM64.
          */
-        IEM_MC_BEGIN(1, 0, 0);
+        IEM_MC_BEGIN(1, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
         IEM_MC_ARG(uint64_t,                    uSrc, 0);
@@ -2712 +2712 @@
          * XMM128, [mem64].
          */
-        IEM_MC_BEGIN(1, 1, 0);
+        IEM_MC_BEGIN(1, 1, 0, 0);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
         IEM_MC_ARG(uint64_t,                    uSrc, 0);
@@ -2748 +2748 @@
         IEMOP_MNEMONIC2(MR_MEM, MOVLPS, movlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2796 +2796 @@
         IEMOP_MNEMONIC2(MR_MEM, MOVLPD, movlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2941 +2941 @@
         IEMOP_MNEMONIC2(RM_REG, MOVLHPS, movlhps, VqHi_WO, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -2969 +2969 @@
         IEMOP_MNEMONIC2(RM_MEM, MOVHPS, movhps, VqHi_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3004 +3004 @@
         IEMOP_MNEMONIC2(RM_MEM, MOVHPD, movhpd, VqHi_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3053 +3053 @@
          * XMM128, XMM128.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -3074 +3074 @@
          * XMM128, [mem128].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3123 +3123 @@
         IEMOP_MNEMONIC2(MR_MEM, MOVHPS, movhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3171 +3171 @@
         IEMOP_MNEMONIC2(MR_MEM, MOVHPD, movhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
 
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3243 +3243 @@
         }
 
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
@@ -3264 +3264 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3271 +3271 @@
     else
     {
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
@@ -3425 +3425 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -3439 +3439 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3474 +3474 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -3488 +3488 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3526 +3526 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -3540 +3540 @@
          * Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3575 +3575 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -3589 +3589 @@
          * Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -3620 +3620 @@
          * XMM, MMX
          */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
@@ -3650 +3650 @@
          * XMM, [mem64]
          */
-        IEM_MC_BEGIN(3, 2, 0);
+        IEM_MC_BEGIN(3, 2, 0, 0);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(X86XMMREG,             Dst);
@@ -3690 +3690 @@
          * XMM, MMX
          */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
@@ -3719 +3719 @@
          * XMM, [mem64]
          */
-        IEM_MC_BEGIN(3, 3, 0);
+        IEM_MC_BEGIN(3, 3, 0, 0);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(X86XMMREG,             Dst);
@@ -3760 +3760 @@
         {
             /* XMM, greg64 */
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,    fMxcsr);
             IEM_MC_LOCAL(RTFLOAT32U,  r32Dst);
@@ -3786 +3786 @@
         {
             /* XMM, [mem64] */
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,   fMxcsr);
@@ -3818 +3818 @@
         {
             /* greg, XMM */
-            IEM_MC_BEGIN(3, 2, 0);
+            IEM_MC_BEGIN(3, 2, 0, 0);
             IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT32U, r32Dst);
@@ -3844 +3844 @@
         {
             /* greg, [mem32] */
-            IEM_MC_BEGIN(3, 4, 0);
+            IEM_MC_BEGIN(3, 4, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,   fMxcsr);
@@ -3885 +3885 @@
         {
             /* XMM, greg64 */
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,    fMxcsr);
             IEM_MC_LOCAL(RTFLOAT64U,  r64Dst);
@@ -3911 +3911 @@
         {
             /* XMM, [mem64] */
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,   fMxcsr);
@@ -3943 +3943 @@
         {
             /* XMM, greg32 */
-            IEM_MC_BEGIN(3, 2, 0);
+            IEM_MC_BEGIN(3, 2, 0, 0);
             IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT64U, r64Dst);
@@ -3969 +3969 @@
         {
             /* XMM, [mem32] */
-            IEM_MC_BEGIN(3, 4, 0);
+            IEM_MC_BEGIN(3, 4, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,   fMxcsr);
@@ -4018 +4018 @@
          * memory, register.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -4057 +4057 @@
          * memory, register.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc); /** @todo optimize this one day... */
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -4090 +4090 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
@@ -4118 +4118 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, 0);
+        IEM_MC_BEGIN(3, 2, 0, 0);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4157 +4157 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
@@ -4185 +4185 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 3, 0);
+        IEM_MC_BEGIN(3, 3, 0, 0);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4227 +4227 @@
         {
             /* greg64, XMM */
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
@@ -4253 +4253 @@
         {
             /* greg64, [mem64] */
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4285 +4285 @@
         {
             /* greg, XMM */
-            IEM_MC_BEGIN(3, 2, 0);
+            IEM_MC_BEGIN(3, 2, 0, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
@@ -4311 +4311 @@
         {
             /* greg, [mem] */
-            IEM_MC_BEGIN(3, 4, 0);
+            IEM_MC_BEGIN(3, 4, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4352 +4352 @@
         {
             /* greg64, XMM */
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
@@ -4378 +4378 @@
         {
             /* greg64, [mem64] */
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4410 +4410 @@
         {
             /* greg, XMM */
-            IEM_MC_BEGIN(3, 2, 0);
+            IEM_MC_BEGIN(3, 2, 0, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
@@ -4436 +4436 @@
         {
             /* greg32, [mem32] */
-            IEM_MC_BEGIN(3, 4, 0);
+            IEM_MC_BEGIN(3, 4, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4476 +4476 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
@@ -4505 +4505 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, 0);
+        IEM_MC_BEGIN(3, 2, 0, 0);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4544 +4544 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 1, 0);
+        IEM_MC_BEGIN(3, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
@@ -4573 +4573 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 3, 0);
+        IEM_MC_BEGIN(3, 3, 0, 0);
         IEM_MC_ARG(uint32_t *,              pfMxcsr,            0);
         IEM_MC_LOCAL(uint64_t,              u64Dst);
@@ -4615 +4615 @@
         {
             /* greg64, XMM */
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
@@ -4641 +4641 @@
         {
             /* greg64, [mem64] */
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4673 +4673 @@
         {
             /* greg, XMM */
-            IEM_MC_BEGIN(3, 2, 0);
+            IEM_MC_BEGIN(3, 2, 0, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
@@ -4699 +4699 @@
         {
             /* greg, [mem] */
-            IEM_MC_BEGIN(3, 4, 0);
+            IEM_MC_BEGIN(3, 4, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4740 +4740 @@
         {
             /* greg64, XMM */
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
@@ -4766 +4766 @@
         {
             /* greg64, [mem64] */
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4798 +4798 @@
         {
             /* greg32, XMM */
-            IEM_MC_BEGIN(3, 2, 0);
+            IEM_MC_BEGIN(3, 2, 0, 0);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
@@ -4824 +4824 @@
         {
             /* greg32, [mem64] */
-            IEM_MC_BEGIN(3, 4, 0);
+            IEM_MC_BEGIN(3, 4, 0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t,  fMxcsr);
@@ -4864 +4864 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, 0);
+        IEM_MC_BEGIN(4, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -4892 +4892 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, 0);
+        IEM_MC_BEGIN(4, 3, 0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -4933 +4933 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, 0);
+        IEM_MC_BEGIN(4, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -4961 +4961 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, 0);
+        IEM_MC_BEGIN(4, 3, 0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -5006 +5006 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, 0);
+        IEM_MC_BEGIN(4, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -5034 +5034 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, 0);
+        IEM_MC_BEGIN(4, 3, 0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -5075 +5075 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, 0);
+        IEM_MC_BEGIN(4, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -5103 +5103 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, 0);
+        IEM_MC_BEGIN(4, 3, 0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -5238 +5238 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(0, 1, 0); \
+                IEM_MC_BEGIN(0, 1, 0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_LOCAL(uint16_t, u16Tmp); \
@@ -5250 +5250 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_LOCAL(uint32_t, u32Tmp); \
@@ -5264 +5264 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_LOCAL(uint64_t, u64Tmp); \
@@ -5283 +5283 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(0, 2, 0); \
+                IEM_MC_BEGIN(0, 2, 0, 0); \
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc); \
                 IEM_MC_LOCAL(uint16_t, u16Tmp); \
@@ -5297 +5297 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0); \
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc); \
                 IEM_MC_LOCAL(uint32_t, u32Tmp); \
@@ -5313 +5313 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0); \
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc); \
                 IEM_MC_LOCAL(uint64_t, u64Tmp); \
@@ -5471 +5471 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 1, 0);
+        IEM_MC_BEGIN(2, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint8_t,           u8Dst);
@@ -5500 +5500 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 1, 0);
+        IEM_MC_BEGIN(2, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint8_t,           u8Dst);
@@ -6203 +6203 @@
         {
             /* MMX, greg64 */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6220 +6220 @@
         {
             /* MMX, [mem64] */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6255 +6255 @@
         {
             /* MMX, greg32 */
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -6272 +6272 @@
         {
             /* MMX, [mem32] */
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -6310 +6310 @@
         {
             /* XMM, greg64 */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6326 +6326 @@
         {
             /* XMM, [mem64] */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6360 +6360 @@
         {
             /* XMM, greg32 */
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -6376 +6376 @@
         {
             /* XMM, [mem32] */
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -6415 +6415 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
         IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -6434 +6434 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t, u64Tmp);
         IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc);
@@ -6470 +6470 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 
@@ -6486 +6486 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -6521 +6521 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -6535 +6535 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -6562 +6562 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 0, 0);
+        IEM_MC_BEGIN(3, 0, 0, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
@@ -6585 +6585 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, 0);
+        IEM_MC_BEGIN(3, 2, 0, 0);
         IEM_MC_ARG(uint64_t *,                  pDst,       0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -6628 +6628 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 0, 0);
+        IEM_MC_BEGIN(3, 0, 0, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -6647 +6647 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, 0);
+        IEM_MC_BEGIN(3, 2, 0, 0);
         IEM_MC_ARG(PRTUINT128U,                 puDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -6713 +6713 @@
          * Register, immediate.
          */
-        IEM_MC_BEGIN(2, 0, 0);
+        IEM_MC_BEGIN(2, 0, 0, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
@@ -6759 +6759 @@
          * Register, immediate.
          */
-        IEM_MC_BEGIN(2, 0, 0);
+        IEM_MC_BEGIN(2, 0, 0, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -7074 +7074 @@
 {
     IEMOP_MNEMONIC(emms, "emms");
-    IEM_MC_BEGIN(0, 0, 0);
+    IEM_MC_BEGIN(0, 0, 0, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
@@ -7105 +7105 @@
         if (enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint64_t *, pu64Dst, 0);
@@ -7116 +7116 @@
         else
         {
-            IEM_MC_BEGIN(2, 0, 0);
+            IEM_MC_BEGIN(2, 0, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint64_t *, pu64Dst, 0);
@@ -7133 +7133 @@
         if (enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint8_t,       iEffSeg,                                          0);
             IEM_MC_ARG(RTGCPTR,       GCPtrVal,                                         1);
@@ -7147 +7147 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, 0);
+            IEM_MC_BEGIN(3, 0, 0, 0);
             IEM_MC_ARG(uint8_t,       iEffSeg,                                          0);
             IEM_MC_ARG(RTGCPTR,       GCPtrVal,                                         1);
@@ -7187 +7187 @@
         if (enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint64_t, u64Val, 0);
@@ -7198 +7198 @@
         else
         {
-            IEM_MC_BEGIN(2, 0, 0);
+            IEM_MC_BEGIN(2, 0, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES();
             IEM_MC_ARG(uint32_t, u32Val, 0);
@@ -7215 +7215 @@
         if (enmEffOpSize == IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint8_t,       iEffSeg,                                          0);
             IEM_MC_ARG(RTGCPTR,       GCPtrVal,                                         1);
@@ -7229 +7229 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, 0);
+            IEM_MC_BEGIN(3, 0, 0, 0);
             IEM_MC_ARG(uint8_t,       iEffSeg,                                          0);
             IEM_MC_ARG(RTGCPTR,       GCPtrVal,                                         1);
@@ -7324 +7324 @@
         {
             /* greg64, MMX */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -7341 +7341 @@
         {
             /* [mem64], MMX */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -7376 +7376 @@
         {
             /* greg32, MMX */
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -7393 +7393 @@
         {
             /* [mem32], MMX */
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -7432 +7432 @@
         {
             /* greg64, XMM */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -7448 +7448 @@
         {
             /* [mem64], XMM */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -7482 +7482 @@
         {
             /* greg32, XMM */
-            IEM_MC_BEGIN(0, 1, 0);
+            IEM_MC_BEGIN(0, 1, 0, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -7498 +7498 @@
         {
             /* [mem32], XMM */
-            IEM_MC_BEGIN(0, 2, 0);
+            IEM_MC_BEGIN(0, 2, 0, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -7534 +7534 @@
          * XMM128, XMM64.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -7552 +7552 @@
          * XMM128, [mem64].
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -7584 +7584 @@
         /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
         /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
-        IEM_MC_BEGIN(0, 1, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fMmx);
         IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -7602 +7602 @@
          * [mem64], MMX.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(uint64_t, u64Tmp);
         IEM_MC_LOCAL(RTGCPTR,  GCPtrEffSrc);
@@ -7630 +7630 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -7644 +7644 @@
          * [mem128], XMM.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -7671 +7671 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(0, 0, 0);
+        IEM_MC_BEGIN(0, 0, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -7685 +7685 @@
          * [mem128], XMM.
          */
-        IEM_MC_BEGIN(0, 2, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -7714 +7714 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7726 +7726 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7747 +7747 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7759 +7759 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7780 +7780 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7792 +7792 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7813 +7813 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7825 +7825 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7846 +7846 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7858 +7858 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7879 +7879 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7891 +7891 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7912 +7912 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7924 +7924 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7945 +7945 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7957 +7957 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7978 +7978 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -7990 +7990 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8011 +8011 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8023 +8023 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8044 +8044 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8056 +8056 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8077 +8077 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8089 +8089 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8110 +8110 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8122 +8122 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8143 +8143 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8155 +8155 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8176 +8176 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8188 +8188 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8209 +8209 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8221 +8221 @@
     else
     {
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -8247 +8247 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
@@ -8260 +8260 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8288 +8288 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
@@ -8301 +8301 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8329 +8329 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
@@ -8342 +8342 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8370 +8370 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
@@ -8383 +8383 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8411 +8411 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
@@ -8424 +8424 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8452 +8452 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
@@ -8465 +8465 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8493 +8493 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
@@ -8506 +8506 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8534 +8534 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
@@ -8547 +8547 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8575 +8575 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
@@ -8588 +8588 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8616 +8616 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
@@ -8629 +8629 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8657 +8657 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
@@ -8670 +8670 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8698 +8698 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
@@ -8711 +8711 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8739 +8739 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
@@ -8752 +8752 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8780 +8780 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
@@ -8793 +8793 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8821 +8821 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
@@ -8834 +8834 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8862 +8862 @@
     {
         /* register target */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_MIN_386, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
@@ -8875 +8875 @@
     {
         /* memory target */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
@@ -8935 +8935 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
@@ -8952 +8952 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
@@ -8970 +8970 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
@@ -8998 +8998 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint16_t *,              pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,                u16Src,                 1); \
@@ -9026 +9026 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,              pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,                u32Src,                 1); \
@@ -9054 +9054 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 5, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 5, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,              pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,                u64Src,                 1); \
@@ -9092 +9092 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint16_t *,              pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,                u16Src,                 1); \
@@ -9120 +9120 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,              pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,                u32Src,                 1); \
@@ -9148 +9148 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,              pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,                u64Src,                 1); \
@@ -9192 +9192 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t const *, pu16Dst,               0); \
@@ -9209 +9209 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t const *, pu32Dst,               0); \
@@ -9226 +9226 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t const *, pu64Dst,               0); \
@@ -9254 +9254 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint16_t const *,        pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,                u16Src,                 1); \
@@ -9282 +9282 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t const *,        pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,                u32Src,                 1); \
@@ -9310 +9310 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t const *,        pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,                u64Src,                 1); \
@@ -9373 +9373 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
@@ -9390 +9390 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
@@ -9408 +9408 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
@@ -9432 +9432 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint16_t *,              pu16Dst,                0);
                 IEM_MC_ARG(uint16_t,                u16Src,                 1);
@@ -9456 +9456 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,              pu32Dst,                0);
                 IEM_MC_ARG(uint32_t,                u32Src,                 1);
@@ -9480 +9480 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,              pu64Dst,                0);
                 IEM_MC_ARG(uint64_t,                u64Src,                 1);
@@ -9522 +9522 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
@@ -9540 +9540 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
@@ -9559 +9559 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
@@ -9584 +9584 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint16_t *,              pu16Dst,                0);
                 IEM_MC_ARG(uint16_t,                u16Src,                 1);
@@ -9607 +9607 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *,              pu32Dst,                0);
                 IEM_MC_ARG(uint32_t,                u32Src,                 1);
@@ -9630 +9630 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,              pu64Dst,                0);
                 IEM_MC_ARG(uint64_t,                u64Src,                 1);
@@ -9745 +9745 @@
         IEMOP_RAISE_INVALID_OPCODE_RET();
 
-    IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_PENTIUM_II);
+    IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_PENTIUM_II, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9765 +9765 @@
         IEMOP_RAISE_INVALID_OPCODE_RET();
 
-    IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_PENTIUM_II);
+    IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_PENTIUM_II, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9803 +9803 @@
         IEMOP_RAISE_INVALID_OPCODE_RET();
 
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_PENTIUM_II);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_PENTIUM_II, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9839 +9839 @@
         IEMOP_RAISE_INVALID_OPCODE_RET();
 
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_PENTIUM_II);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_PENTIUM_II, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9865 +9865 @@
         IEMOP_RAISE_INVALID_OPCODE_RET();
 
-    IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_CORE);
+    IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_CORE, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9892 +9892 @@
         IEMOP_RAISE_INVALID_OPCODE_RET();
 
-    IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_CORE);
+    IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_CORE, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9921 +9921 @@
         return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
 
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9945 +9945 @@
         return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
 
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -9961 +9961 @@
     RT_NOREF_PV(bRm);
     IEMOP_MNEMONIC(lfence, "lfence");
-    IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 #ifdef RT_ARCH_ARM64
@@ -9981 +9981 @@
     RT_NOREF_PV(bRm);
     IEMOP_MNEMONIC(mfence, "mfence");
-    IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 #ifdef RT_ARCH_ARM64
@@ -10001 +10001 @@
     RT_NOREF_PV(bRm);
     IEMOP_MNEMONIC(sfence, "sfence");
-    IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 #ifdef RT_ARCH_ARM64
@@ -10022 +10022 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10033 +10033 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10051 +10051 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10062 +10062 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10080 +10080 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10092 +10092 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10110 +10110 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10122 +10122 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
@@ -10203 +10203 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_486);
+        IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_486, 0);
         IEMOP_HLP_DONE_DECODING();
         IEM_MC_ARG(uint8_t *,       pu8Dst,                 0);
@@ -10224 +10224 @@
     else
     {
-        IEM_MC_BEGIN(4, 4, IEM_MC_F_MIN_486);
+        IEM_MC_BEGIN(4, 4, IEM_MC_F_MIN_486, 0);
         IEM_MC_ARG(uint8_t *,       pu8Dst,                 0);
         IEM_MC_ARG(uint8_t *,       pu8Al,                  1);
@@ -10265 +10265 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_486, 0);
                 IEMOP_HLP_DONE_DECODING();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
@@ -10286 +10286 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_486, 0);
                 IEMOP_HLP_DONE_DECODING();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
@@ -10313 +10313 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
@@ -10353 +10353 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(4, 4, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(4, 4, IEM_MC_F_MIN_486, 0);
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
                 IEM_MC_ARG(uint16_t *,      pu16Ax,                 1);
@@ -10382 +10382 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(4, 4, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(4, 4, IEM_MC_F_MIN_486, 0);
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
                 IEM_MC_ARG(uint32_t *,      pu32Eax,                 1);
@@ -10415 +10415 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(4, 4, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(4, 4, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
                 IEM_MC_ARG(uint64_t *,      pu64Rax,                1);
@@ -10523 +10523 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
@@ -10533 +10533 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
@@ -10543 +10543 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
@@ -10563 +10563 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -10575 +10575 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -10587 +10587 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -10622 +10622 @@
         if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
@@ -10632 +10632 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
@@ -10648 +10648 @@
         if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
             IEM_MC_LOCAL(uint32_t, u32Value);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -10660 +10660 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -10728 +10728 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                    0); \
@@ -10743 +10743 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                    0); \
@@ -10759 +10759 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                    0); \
@@ -10785 +10785 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint16_t *,              pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,                u16Src,                 1); \
@@ -10807 +10807 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,              pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,                u32Src,                 1); \
@@ -10829 +10829 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,              pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,                u64Src,                 1); \
@@ -10861 +10861 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint16_t *,              pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,                u16Src,                 1); \
@@ -10883 +10883 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t *,              pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,                u32Src,                 1); \
@@ -10905 +10905 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t *,              pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,                u64Src,                 1); \
@@ -10944 +10944 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t const *, pu16Dst,                   0); \
@@ -10959 +10959 @@
             \
             case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint32_t const *, pu32Dst,                   0); \
@@ -10974 +10974 @@
             \
             case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint64_t const *, pu64Dst,                   0); \
@@ -11000 +11000 @@
             { \
                 case IEMMODE_16BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint16_t const *,        pu16Dst,                0); \
                     IEM_MC_ARG(uint16_t,                u16Src,                 1); \
@@ -11022 +11022 @@
                 \
                 case IEMMODE_32BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \
                     IEM_MC_ARG(uint32_t const *,        pu32Dst,                0); \
                     IEM_MC_ARG(uint32_t,                u32Src,                 1); \
@@ -11044 +11044 @@
                 \
                 case IEMMODE_64BIT: \
-                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT); \
+                    IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \
                     IEM_MC_ARG(uint64_t const *,        pu64Dst,                0); \
                     IEM_MC_ARG(uint64_t,                u64Src,                 1); \
@@ -11164 +11164 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
@@ -11180 +11180 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
@@ -11198 +11198 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
@@ -11224 +11224 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
                 IEM_MC_ARG(uint16_t,   u16Src,  1);
@@ -11242 +11242 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0);
                 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
                 IEM_MC_ARG(uint32_t,   u32Src,  1);
@@ -11263 +11263 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
                 IEM_MC_ARG(uint64_t,   u64Src,  1);
@@ -11377 +11377 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint16_t, u16Value);
@@ -11387 +11387 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint32_t, u32Value);
@@ -11397 +11397 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_LOCAL(uint64_t, u64Value);
@@ -11417 +11417 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint16_t, u16Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -11429 +11429 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -11441 +11441 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -11476 +11476 @@
         if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_MIN_386, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint32_t, u32Value);
@@ -11486 +11486 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_LOCAL(uint64_t, u64Value);
@@ -11502 +11502 @@
         if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
             IEM_MC_LOCAL(uint32_t, u32Value);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -11514 +11514 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(uint64_t, u64Value);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -11540 +11540 @@
     if (IEM_IS_MODRM_REG_MODE(bRm))
     {
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_486);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_486, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_ARG(uint8_t *,  pu8Dst,  0);
@@ -11559 +11559 @@
          * We're accessing memory.
          */
-        IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_486);
+        IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_486, 0);
         IEM_MC_ARG(uint8_t *,   pu8Dst,          0);
         IEM_MC_ARG(uint8_t *,   pu8Reg,          1);
@@ -11602 +11602 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_486, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *, pu16Dst,  0);
@@ -11618 +11618 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_486, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *, pu32Dst,  0);
@@ -11636 +11636 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *, pu64Dst,  0);
@@ -11662 +11662 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_486, 0);
                 IEM_MC_ARG(uint16_t *,  pu16Dst,         0);
                 IEM_MC_ARG(uint16_t *,  pu16Reg,         1);
@@ -11689 +11689 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_486);
+                IEM_MC_BEGIN(3, 4, IEM_MC_F_MIN_486, 0);
                 IEM_MC_ARG(uint32_t *,  pu32Dst,         0);
                 IEM_MC_ARG(uint32_t *,  pu32Reg,         1);
@@ -11716 +11716 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(3, 4, IEM_MC_F_64BIT, 0);
                 IEM_MC_ARG(uint64_t *,  pu64Dst,         0);
                 IEM_MC_ARG(uint64_t *,  pu64Reg,         1);
@@ -11759 +11759 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
@@ -11788 +11788 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11830 +11830 @@
          * XMM, XMM.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -11859 +11859 @@
          * XMM, [mem128].
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11901 +11901 @@
          * XMM32, XMM32.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -11930 +11930 @@
          * XMM32, [mem32].
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -11972 +11972 @@
          * XMM64, XMM64.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -12001 +12001 @@
          * XMM64, [mem64].
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(IEMMEDIAF2XMMSRC,              Src);
         IEM_MC_LOCAL(X86XMMREG,                     Dst);
@@ -12045 +12045 @@
         {
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_MIN_386, 0);
                 IEM_MC_LOCAL(uint32_t, u32Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -12059 +12059 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
                 IEM_MC_LOCAL(uint64_t, u64Value);
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
@@ -12099 +12099 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
@@ -12120 +12120 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(uint64_t *,    pu64Dst,               0);
         IEM_MC_ARG(uint16_t,      u16Src,                1);
@@ -12153 +12153 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -12172 +12172 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,   puDst,                 0);
         IEM_MC_ARG(uint16_t,      u16Src,                1);
@@ -12207 +12207 @@
          * Greg32, MMX, imm8.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
@@ -12239 +12239 @@
          * Greg32, XMM, imm8.
          */
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -12274 +12274 @@
          * XMM, XMM, imm8.
          */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
@@ -12293 +12293 @@
          * XMM, [mem128], imm8.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 pDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -12326 +12326 @@
          * XMM, XMM, imm8.
          */
-        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
@@ -12345 +12345 @@
          * XMM, [mem128], imm8.
          */
-        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_ARG(PRTUINT128U,                 pDst,       0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -12377 +12377 @@
     IEMOP_MNEMONIC(cmpxchg8b, "cmpxchg8b Mq");
 
-    IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint64_t *, pu64MemDst,     0);
     IEM_MC_ARG(PRTUINT64U, pu64EaxEdx,     1);
@@ -12424 +12424 @@
     if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fCmpXchg16b)
     {
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0);
         IEM_MC_ARG(PRTUINT128U, pu128MemDst,     0);
         IEM_MC_ARG(PRTUINT128U, pu128RaxRdx,     1);
@@ -12522 +12522 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
@@ -12537 +12537 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
@@ -12553 +12553 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
@@ -12582 +12582 @@
     IEMOP_HLP_IN_VMX_OPERATION("vmptrld", kVmxVDiag_Vmptrld);
     IEMOP_HLP_VMX_INSTR("vmptrld", kVmxVDiag_Vmptrld);
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t, iEffSeg,     0);
     IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
@@ -12602 +12602 @@
     IEMOP_HLP_IN_VMX_OPERATION("vmclear", kVmxVDiag_Vmclear);
     IEMOP_HLP_VMX_INSTR("vmclear", kVmxVDiag_Vmclear);
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t, iEffSeg,     0);
     IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
@@ -12621 +12621 @@
     IEMOP_MNEMONIC(vmxon, "vmxon");
     IEMOP_HLP_VMX_INSTR("vmxon", kVmxVDiag_Vmxon);
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t, iEffSeg,     0);
     IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
@@ -12641 +12641 @@
     IEMOP_HLP_IN_VMX_OPERATION("vmptrst", kVmxVDiag_Vmptrst);
     IEMOP_HLP_VMX_INSTR("vmptrst", kVmxVDiag_Vmptrst);
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t, iEffSeg,     0);
     IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
@@ -12666 +12666 @@
         {
             case IEMMODE_16BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint16_t *,      pu16Dst,                0);
@@ -12681 +12681 @@
 
             case IEMMODE_32BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint32_t *,      pu32Dst,                0);
@@ -12697 +12697 @@
 
             case IEMMODE_64BIT:
-                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT);
+                IEM_MC_BEGIN(2, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_ARG(uint64_t *,      pu64Dst,                0);
@@ -12775 +12775 @@
     {
         case IEMMODE_16BIT:
-            IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_486);
+            IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_486, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ARG(uint32_t *,  pu32Dst, 0);
@@ -12785 +12785 @@
 
         case IEMMODE_32BIT:
-            IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_486);
+            IEM_MC_BEGIN(1, 0, IEM_MC_F_MIN_486, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ARG(uint32_t *,  pu32Dst, 0);
@@ -12796 +12796 @@
 
         case IEMMODE_64BIT:
-            IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
             IEM_MC_ARG(uint64_t *,  pu64Dst, 0);
@@ -13021 +13021 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -13039 +13039 @@
          * Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -13075 +13075 @@
          */
         IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZx_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -13127 +13127 @@
          */
         IEMOP_MNEMONIC2(RM_REG, MOVDQ2Q, movdq2q, Pq_WO, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -13166 +13166 @@
         /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
         IEMOP_MNEMONIC2(RM_REG, PMOVMSKB, pmovmskb, Gd, Nq, DISOPTYPE_X86_MMX | DISOPTYPE_HARMLESS, 0);
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(fSse, fAmdMmxExts);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
@@ -13195 +13195 @@
         /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
         IEMOP_MNEMONIC2(RM_REG, PMOVMSKB, pmovmskb, Gd, Ux, DISOPTYPE_X86_SSE | DISOPTYPE_HARMLESS, 0);
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_ARG(uint64_t *,              puDst, 0);
@@ -13524 +13524 @@
     {
         /* Register, memory. */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -13571 +13571 @@
     {
         /* Register, memory. */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -13782 +13782 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);

trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h

@@ -51 +51 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -71 +71 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
@@ -95 +95 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -120 +120 @@
         else
         {
-            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc2);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -165 +165 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -184 +184 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
@@ -207 +207 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(3, 4, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -231 +231 @@
         else
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc2);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -307 +307 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -323 +323 @@
         else
         {
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
@@ -344 +344 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(2, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -365 +365 @@
         else
         {
-            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -432 +432 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -450 +450 @@
          * 128-bit: Register, Memory
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -470 +470 @@
          * 256-bit: Register, Memory
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -507 +507 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -525 +525 @@
          * 128-bit: Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -545 +545 @@
          * 256-bit: Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -583 +583 @@
          */
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -608 +608 @@
          */
         IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -646 +646 @@
          */
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
 
@@ -672 +672 @@
          */
         IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -709 +709 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -727 +727 @@
          * 128-bit: Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -747 +747 @@
          * 256-bit: Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -784 +784 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -802 +802 @@
          * 128-bit: Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -822 +822 @@
          * 256-bit: Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -859 +859 @@
          */
         IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
 
@@ -885 +885 @@
          */
         IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -923 +923 @@
          */
         IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
 
@@ -949 +949 @@
          */
         IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -986 +986 @@
          */
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
 
@@ -1016 +1016 @@
         IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1055 +1055 @@
         IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1112 +1112 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1131 +1131 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
@@ -1152 +1152 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1173 +1173 @@
         else
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1217 +1217 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_ARG(uint64_t,                    uSrc, 0);
@@ -1234 +1234 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
@@ -1255 +1255 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(1, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(1, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_ARG(uint64_t,                    uSrc, 0);
@@ -1274 +1274 @@
         else
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1313 +1313 @@
         IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1360 +1360 @@
     {
         IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1452 +1452 @@
         IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
 
@@ -1478 +1478 @@
         IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1513 +1513 @@
         IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1566 +1566 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(RTUINT128U,                  uSrc);
@@ -1585 +1585 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
@@ -1606 +1606 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1627 +1627 @@
         else
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1667 +1667 @@
         IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1713 +1713 @@
         IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
 
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1786 +1786 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -1807 +1807 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1824 +1824 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
@@ -1863 +1863 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -1884 +1884 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1901 +1901 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
@@ -1959 +1959 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -1980 +1980 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -1997 +1997 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
@@ -2035 +2035 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -2056 +2056 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -2073 +2073 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
@@ -2144 +2144 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2161 +2161 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2205 +2205 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2222 +2222 @@
         else
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -2289 +2289 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -2318 +2318 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2360 +2360 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -2389 +2389 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2434 +2434 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -2463 +2463 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2505 +2505 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
@@ -2534 +2534 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
         IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
@@ -2615 +2615 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_LOCAL(uint8_t,           u8Dst);
@@ -2631 +2631 @@
         else
         {
-            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(uint8_t,               u8Dst);
@@ -2666 +2666 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_LOCAL(uint8_t,           u8Dst);
@@ -2682 +2682 @@
         else
         {
-            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(uint8_t,               u8Dst);
@@ -3024 +3024 @@
 //         * Register, register.
 //         */
-//        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+//        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
 //        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
 //        IEM_MC_ARG(PRTUINT128U,          pDst, 0);
@@ -3041 +3041 @@
 //         * Register, memory.
 //         */
-//        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+//        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
 //        IEM_MC_ARG(PRTUINT128U,                 pDst,       0);
 //        IEM_MC_LOCAL(RTUINT128U,                uSrc);
@@ -3174 +3174 @@
         {
             /* XMM, greg64 */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -3190 +3190 @@
         {
             /* XMM, [mem64] */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -3224 +3224 @@
         {
             /* XMM, greg32 */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -3240 +3240 @@
         {
             /* XMM, [mem32] */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -3283 +3283 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -3302 +3302 @@
          * Register, memory128.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -3322 +3322 @@
          * Register, memory256.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U, u256Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -3358 +3358 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -3377 +3377 @@
          * Register, memory128.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -3397 +3397 @@
          * Register, memory256.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U, u256Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -3436 +3436 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -3453 +3453 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,             puDst,                 0);
@@ -3475 +3475 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc);
@@ -3498 +3498 @@
         else
         {
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,            uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -3735 +3735 @@
          */
         IEMOP_MNEMONIC(vzeroupper, "vzeroupper");
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
 
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
@@ -3771 +3771 @@
          */
         IEMOP_MNEMONIC(vzeroall, "vzeroall");
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t,  uZero);
 
@@ -3866 +3866 @@
         {
             /* greg64, XMM */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -3882 +3882 @@
         {
             /* [mem64], XMM */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint64_t, u64Tmp);
@@ -3916 +3916 @@
         {
             /* greg32, XMM */
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -3932 +3932 @@
         {
             /* [mem32], XMM */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
             IEM_MC_LOCAL(uint32_t, u32Tmp);
@@ -3969 +3969 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
 
@@ -3985 +3985 @@
          * Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -4026 +4026 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -4045 +4045 @@
          * Register, memory128.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -4065 +4065 @@
          * Register, memory256.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U, u256Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -4102 +4102 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
 
@@ -4121 +4121 @@
          * Register, memory128.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -4141 +4141 @@
          * Register, memory256.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U, u256Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -4235 +4235 @@
 //{
 //    IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
-//    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+//    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
 //    IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
 //    IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -4289 +4289 @@
 {
     IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
-    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+    IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
     IEM_MC_ARG(uint8_t,         iEffSeg,                                 0);
     IEM_MC_ARG(RTGCPTR,         GCPtrEff,                                1);
@@ -4402 +4402 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
@@ -4425 +4425 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTGCPTR,     GCPtrEffSrc);
         IEM_MC_ARG(PRTUINT128U,   puDst,                 0);
@@ -4468 +4468 @@
          */
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
-        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
         IEM_MC_LOCAL(uint16_t,              u16Dst);
@@ -4503 +4503 @@
         { \
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
             IEM_MC_LOCAL(RTUINT256U,            uDst); \
@@ -4525 +4525 @@
         { \
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
             IEM_MC_ARG(PRTUINT128U,          puDst,                 0); \
@@ -4550 +4550 @@
         if (pVCpu->iem.s.uVexLength) \
         { \
-            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_LOCAL(RTUINT256U,            uDst); \
             IEM_MC_LOCAL(RTUINT256U,            uSrc1); \
@@ -4574 +4574 @@
         else \
         { \
-            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_LOCAL(RTUINT128U,                uSrc2); \
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc); \
@@ -4708 +4708 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
 
@@ -4724 +4724 @@
          * Memory, register.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -4758 +4758 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_ARG(uint64_t *,              puDst, 0);
@@ -4774 +4774 @@
         else
         {
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
             IEM_MC_ARG(uint64_t *,              puDst, 0);
@@ -5020 +5020 @@
              * 128-bit: Memory, register.
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -5040 +5040 @@
              * 256-bit: Memory, register.
              */
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -5218 +5218 @@
          * Register, memory128.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U, u128Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
@@ -5238 +5238 @@
          * Register, memory256.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U, u256Tmp);
         IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);

trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h

@@ -221 +221 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -240 +240 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PCRTUINT128U,            puSrc1,  0);
@@ -262 +262 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
             IEM_MC_LOCAL(RTUINT256U,            uSrc2);
@@ -286 +286 @@
         else
         {
-            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,            uSrc2);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -325 +325 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint32_t,              uSrc);
@@ -340 +340 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint32_t,              uSrc);
@@ -360 +360 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -377 +377 @@
         else
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -411 +411 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint64_t,              uSrc);
@@ -426 +426 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
             IEM_MC_LOCAL(uint64_t,              uSrc);
@@ -444 +444 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint64_t,              uSrc);
         IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -482 +482 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
         IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -551 +551 @@
         if (pVCpu->iem.s.uVexLength) \
         { \
-            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
             IEM_MC_LOCAL(RTUINT256U,            uDst); \
@@ -568 +568 @@
         else \
         { \
-            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
             IEM_MC_ARG(PRTUINT128U,          puDst,  0); \
@@ -591 +591 @@
         if (pVCpu->iem.s.uVexLength) \
         { \
-            IEM_MC_BEGIN(2, 3, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(2, 3, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_LOCAL(RTUINT256U,            uDst); \
             IEM_MC_LOCAL(RTUINT128U,            uSrc); \
@@ -611 +611 @@
         else \
         { \
-            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc); \
             IEM_MC_ARG(PRTUINT128U,                 puDst,       0); \
@@ -728 +728 @@
             IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
                               DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -759 +759 @@
             IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
                               DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,                uSrc);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -968 +968 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
         IEM_MC_ARG(PRTUINT128U,          puDst,  0);
@@ -987 +987 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1050 +1050 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,              uSrc);
 
@@ -1065 +1065 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,              uSrc);
 
@@ -1085 +1085 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1102 +1102 @@
         else
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint32_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1133 +1133 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint64_t,              uSrc);
 
@@ -1148 +1148 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint64_t,              uSrc);
 
@@ -1168 +1168 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint64_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1185 +1185 @@
         else
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint64_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1221 +1221 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
         IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1284 +1284 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint8_t,               uSrc);
 
@@ -1299 +1299 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint8_t,               uSrc);
 
@@ -1319 +1319 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint8_t,               uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1336 +1336 @@
         else
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint8_t,               uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1367 +1367 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint16_t,              uSrc);
 
@@ -1382 +1382 @@
         else
         {
-            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint16_t,              uSrc);
 
@@ -1402 +1402 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint16_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1419 +1419 @@
         else
         {
-            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(uint16_t,              uSrc);
             IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -1645 +1645 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
             IEM_MC_ARG(uint64_t *,          pDst,    0);
@@ -1662 +1662 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
             IEM_MC_ARG(uint32_t *,          pDst,    0);
@@ -1686 +1686 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint64_t *,          pDst,    0);
             IEM_MC_ARG(uint64_t,            uSrc1,   1);
@@ -1705 +1705 @@
         else
         {
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint32_t *,          pDst,    0);
             IEM_MC_ARG(uint32_t,            uSrc1,   1);
@@ -1746 +1746 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
@@ -1761 +1761 @@
         else \
         { \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
@@ -1783 +1783 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc,    1); \
@@ -1800 +1800 @@
         else \
         { \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc,    1); \
@@ -1897 +1897 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
@@ -1915 +1915 @@
         else \
         { \
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
@@ -1940 +1940 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc1,   1); \
@@ -1960 +1960 @@
         else \
         { \
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc1,   1); \
@@ -1993 +1993 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
@@ -2008 +2008 @@
         else \
         { \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
@@ -2030 +2030 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc1,   1); \
@@ -2047 +2047 @@
         else \
         { \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc1,   1); \
@@ -2085 +2085 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
@@ -2101 +2101 @@
         else \
         { \
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
@@ -2124 +2124 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
         { \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
             IEM_MC_ARG(uint64_t *,          pDst,    0); \
             IEM_MC_ARG(uint64_t,            uSrc1,   1); \
@@ -2142 +2142 @@
         else \
         { \
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER); \
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
             IEM_MC_ARG(uint32_t *,          pDst,    0); \
             IEM_MC_ARG(uint32_t,            uSrc1,   1); \
@@ -2196 +2196 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
             IEM_MC_ARG(uint64_t *,          pDst1,   0);
@@ -2213 +2213 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
             IEM_MC_ARG(uint32_t *,          pDst1,   0);
@@ -2238 +2238 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint64_t *,          pDst1,   0);
             IEM_MC_ARG(uint64_t *,          pDst2,   1);
@@ -2257 +2257 @@
         else
         {
-            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint32_t *,          pDst1,   0);
             IEM_MC_ARG(uint32_t *,          pDst2,   1);

trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h

@@ -53 +53 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
@@ -74 +74 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
@@ -99 +99 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -125 +125 @@
         else
         {
-            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc2);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -172 +172 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -192 +192 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
@@ -216 +216 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -242 +242 @@
         else
         {
-            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc2);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -293 +293 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
@@ -318 +318 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U,                uDst);
         IEM_MC_LOCAL(RTUINT256U,                uSrc1);
@@ -424 +424 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
@@ -444 +444 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
         IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -516 +516 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
@@ -536 +536 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,            uSrc);
         IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
@@ -595 +595 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
@@ -618 +618 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT128U,                uSrc2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -659 +659 @@
          * Register, register.
          */
-        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
         uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
         IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
@@ -684 +684 @@
          * Register, memory.
          */
-        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+        IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(RTUINT256U,                uDst);
         IEM_MC_LOCAL(RTUINT256U,                uSrc1);
@@ -737 +737 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -759 +759 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
@@ -784 +784 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -814 +814 @@
         else
         {
-            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc2);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -881 +881 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
@@ -903 +903 @@
         else
         {
-            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
             IEM_MC_ARG(PRTUINT128U,          puDst,  0);
@@ -928 +928 @@
         if (pVCpu->iem.s.uVexLength)
         {
-            IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT256U,            uDst);
             IEM_MC_LOCAL(RTUINT256U,            uSrc1);
@@ -958 +958 @@
         else
         {
-            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTUINT128U,                uSrc2);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
@@ -1131 +1131 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
             IEM_MC_ARG(uint64_t *,          pDst,    0);
@@ -1144 +1144 @@
         else
         {
-            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
             IEM_MC_ARG(uint32_t *,          pDst,    0);
@@ -1164 +1164 @@
         if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
         {
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT);
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0);
             IEM_MC_ARG(uint64_t *,          pDst,    0);
             IEM_MC_ARG(uint64_t,            uSrc1,   1);
@@ -1180 +1180 @@
         else
         {
-            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER);
+            IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_ARG(uint32_t *,          pDst,    0);
             IEM_MC_ARG(uint32_t,            uSrc1,   1);

trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py

@@ -44 +44 @@
 
 
+## Supplememnts g_dMcStmtParsers.
+g_dMcStmtThreaded = {
+    'IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED':                      (None, True,  True,  ),
+    'IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED':                      (None, True,  True,  ),
+    'IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED':                      (None, True,  True,  ),
+    'IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED':                      (None, True,  True,  ),
+
+    'IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16':               (None, True,  False, ),
+    'IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32':               (None, True,  False, ), # True ),
+    'IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64':               (None, True,  False, ),
+
+    'IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS':    (None, True,  False, ),
+    'IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS':    (None, True,  False,  ),
+    'IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS':    (None, True,  False, ),
+
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_ADDR32':                (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_PRE386':                (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16':                       (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_ADDR16':                (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_FLAT':                  (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32':                       (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32':                (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS':                  (None, False, False, ),
+    'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64':                       (None, False, False, ),
+
+    'IEM_MC_CALL_CIMPL_1_THREADED':                              (None, True,  False, ),
+    'IEM_MC_CALL_CIMPL_2_THREADED':                              (None, True,  False, ),
+    'IEM_MC_CALL_CIMPL_3_THREADED':                              (None, True,  False, ),
+    'IEM_MC_CALL_CIMPL_4_THREADED':                              (None, True,  False, ),
+    'IEM_MC_CALL_CIMPL_5_THREADED':                              (None, True,  False, ),
+
+    'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16':                (None, True,  False, ),
+    'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32':                (None, True,  False, ),
+    'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64':                (None, True,  False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16':               (None, True,  False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32':               (None, True,  False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64':               (None, True,  False, ),
+    'IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32':               (None, True,  False, ),
+    'IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64':               (None, True,  False, ),
+
+    'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16_WITH_FLAGS':     (None, True,  False, ),
+    'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_WITH_FLAGS':     (None, True,  False, ),
+    'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_WITH_FLAGS':     (None, True,  False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS':    (None, True,  False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS':    (None, True,  False, ),
+    'IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS':    (None, True,  False, ),
+    'IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS':    (None, True,  False, ),
+    'IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS':    (None, True,  False, ),
+
+    'IEM_MC_STORE_GREG_U8_THREADED':                             (None, True,  False, ),
+    'IEM_MC_STORE_GREG_U8_CONST_THREADED':                       (None, True,  False, ),
+    'IEM_MC_FETCH_GREG_U8_THREADED':                             (None, False, False, ),
+    'IEM_MC_FETCH_GREG_U8_SX_U16_THREADED':                      (None, False, False, ),
+    'IEM_MC_FETCH_GREG_U8_SX_U32_THREADED':                      (None, False, False, ),
+    'IEM_MC_FETCH_GREG_U8_SX_U64_THREADED':                      (None, False, False, ),
+    'IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED':                      (None, False, False, ),
+    'IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED':                      (None, False, False, ),
+    'IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED':                      (None, False, False, ),
+    'IEM_MC_REF_GREG_U8_THREADED':                               (None, True,  False, ),
+
+    # Flat Mem:
+    'IEM_MC_FETCH_MEM16_FLAT_U8':                                (None, True,  False, ),
+    'IEM_MC_FETCH_MEM32_FLAT_U8':                                (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_D80':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_I16':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_I32':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_I64':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_R32':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_R64':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_R80':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U128_ALIGN_SSE':                      (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U128_NO_AC':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U128':                                (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U16_DISP':                            (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U16_SX_U32':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U16_SX_U64':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U16':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U256_ALIGN_AVX':                      (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U256_NO_AC':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U256':                                (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U32_DISP':                            (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U32_SX_U64':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U32':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64':                          (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U64':                                 (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8_SX_U16':                           (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8_SX_U32':                           (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8_SX_U64':                           (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8':                                  (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16':                           (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32':                           (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64':                           (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE':                       (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_XMM_U32':                             (None, True,  False, ),
+    'IEM_MC_FETCH_MEM_FLAT_XMM_U64':                             (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_EX':                                    (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP':                                       (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U16_RO':                                (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U16_RW':                                (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U32_RO':                                (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U32_RW':                                (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U64_RO':                                (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U64_RW':                                (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U8_RO':                                 (None, True,  False, ),
+    'IEM_MC_MEM_FLAT_MAP_U8_RW':                                 (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE':                      (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U128':                                (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U16':                                 (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX':                      (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U256':                                (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U32':                                 (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U64':                                 (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U8_CONST':                            (None, True,  False, ),
+    'IEM_MC_STORE_MEM_FLAT_U8':                                  (None, True,  False, ),
+
+    # Flat Stack:
+    'IEM_MC_FLAT64_PUSH_U16':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U64':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U16':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U64':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_POP_U16':                                     (None, True,  False, ),
+    'IEM_MC_FLAT64_POP_U64':                                     (None, True,  False, ),
+    'IEM_MC_FLAT64_POP_U16':                                     (None, True,  False, ),
+    'IEM_MC_FLAT64_POP_U64':                                     (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U16':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U64':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U16':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U64':                                    (None, True,  False, ),
+    'IEM_MC_FLAT32_PUSH_U16':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U16':                                    (None, True,  False, ),
+    'IEM_MC_FLAT32_PUSH_U32':                                    (None, True,  False, ),
+    'IEM_MC_FLAT64_PUSH_U64':                                    (None, True,  False, ),
+};
+
 class NativeRecompFunctionVariation(object):
     """
@@ -70 +206 @@
         aoStmts = self.oVariation.aoStmtsForThreadedFunction # type: list(McStmt)
         return iai.McStmt.renderCodeForList(aoStmts, cchIndent);
+
+    @staticmethod
+    def checkStatements(aoStmts, sHostArch):
+        """
+        Checks that all the given statements are supported by the native recompiler.
+        """
+        _ = sHostArch;
+        for oStmt in aoStmts:   # type: McStmt
+            if not oStmt.isCppStmt():
+                aInfo = iai.g_dMcStmtParsers.get(oStmt.sName);
+                if not aInfo:
+                    aInfo = g_dMcStmtThreaded.get(oStmt.sName);
+                    if not aInfo:
+                        raise Exception('Unknown statement: %s' % (oStmt.sName, ));
+                if aInfo[2] is False:
+                    return False;
+                if aInfo[2] is not True:
+                    if isinstance(aInfo[2], str):
+                        if aInfo[2] != sHostArch:
+                            return False;
+                    elif sHostArch not in aInfo[2]:
+                        return False;
+            #elif not self.fDecode:
+
+            if isinstance(oStmt, iai.McStmtCond):
+                if not NativeRecompFunctionVariation.checkStatements(oStmt.aoIfBranch, sHostArch):
+                    return False;
+                if not NativeRecompFunctionVariation.checkStatements(oStmt.aoElseBranch, sHostArch):
+                    return False;
+        return True;
 
 
@@ -87 +253 @@
     #
     aoStmts = oVariation.aoStmtsForThreadedFunction # type: list(McStmt)
+    if NativeRecompFunctionVariation.checkStatements(aoStmts, sHostArch):
+        return NativeRecompFunctionVariation(oVariation, sHostArch);
 
     # The simplest case are the IEM_MC_DEFER_TO_CIMPL_*_RET_THREADED ones, just pass them thru:
-    if (    len(aoStmts) == 1
-        and aoStmts[0].sName.startswith('IEM_MC_DEFER_TO_CIMPL_')
-        and aoStmts[0].sName.endswith('_RET_THREADED')):
-        return NativeRecompFunctionVariation(oVariation, sHostArch);
+    #if (    len(aoStmts) == 1
+    #    and aoStmts[0].sName.startswith('IEM_MC_DEFER_TO_CIMPL_')
+    #    and aoStmts[0].sName.endswith('_RET_THREADED')):
+    #    return NativeRecompFunctionVariation(oVariation, sHostArch);
+
+
+    # g_dMcStmtParsers
+
 
     return None;

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

@@ -48 +48 @@
 #define IEM_WITH_OPAQUE_DECODER_STATE
 #define VMCPU_INCL_CPUM_GST_CTX
+#define VMM_INCLUDED_SRC_include_IEMMc_h /* block IEMMc.h inclusion. */
 #include <VBox/vmm/iem.h>
 #include <VBox/vmm/cpum.h>
@@ -1126 +1127 @@
  * Called before starting a new recompile job.
  */
-static PIEMRECOMPILERSTATE iemNativeReInit(PIEMRECOMPILERSTATE pReNative)
+static PIEMRECOMPILERSTATE iemNativeReInit(PIEMRECOMPILERSTATE pReNative, PCIEMTB pTb)
 {
     pReNative->cLabels   = 0;
     pReNative->cFixups   = 0;
+    pReNative->pTbOrg    = pTb;
     return pReNative;
 }
@@ -1142 +1144 @@
  * @param   pVCpu   The cross context virtual CPU structure of the calling
  *                  thread.
+ * @param   pTb     The TB that's about to be recompiled.
  * @thread  EMT(pVCpu)
  */
-static PIEMRECOMPILERSTATE iemNativeInit(PVMCPUCC pVCpu)
+static PIEMRECOMPILERSTATE iemNativeInit(PVMCPUCC pVCpu, PCIEMTB pTb)
 {
     VMCPU_ASSERT_EMT(pVCpu);
@@ -1172 +1175 @@
          */
         pVCpu->iem.s.pNativeRecompilerStateR3 = pReNative;
-        return iemNativeReInit(pReNative);
+        return iemNativeReInit(pReNative, pTb);
     }
 
@@ -1906 +1909 @@
 
 
+#if 0
+/** Same as iemRegFinishClearingRF. */
+DECLINLINE(uint32_t) iemNativeEmitFinishClearingRF(PIEMRECOMPILERSTATE pReNative, uint32_t off)
+{
+    RT_NOREF(pReNative, off);
+#if 0
+    uint32_t const fFlags = pReNative->pTbOrg->fFlags;
+    if (fFlags & IEMTB_F_INHIBIT_SHADOW)
+    {
+    }
+    IEMTB_F_IEM_F_MASK
+
+    //
+        if (RT_LIKELY(!(  pVCpu->cpum.GstCtx.eflags.uBoth
+                        & (X86_EFL_TF | X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK)) ))
+            return VINF_SUCCESS;
+        return iemFinishInstructionWithFlagsSet(pVCpu);
+#else
+    return UINT32_MAX;
+#endif
+}
+
+
+/** Same as iemRegAddToEip32AndFinishingClearingRF. */
+DECLINLINE(uint32_t) iemNativeEmitAddToEip32AndFinishingClearingRF(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr)
+{
+    /* Increment RIP. */
+    pVCpu->cpum.GstCtx.rip = (uint32_t)(pVCpu->cpum.GstCtx.eip + cbInstr);
+
+    /* Consider flags. */
+    return iemNativeEmitFinishClearingRF(pReNative, off);
+}
+#endif
+
 /*
  * MC definitions for the native recompiler.
@@ -1921 +1958 @@
 #define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2) \
     return iemNativeEmitCImplCall3(pReNative, off, pCallEntry->idxInstr, (uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1, a2)
+
+
+#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fFlags)      {
+
+#define IEM_MC_END()                                    } AssertFailedReturn(UINT32_MAX /* shouldn't be reached! */)
+
+#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr) \
+    return iemNativeEmitAddToIp16AndFinishingClearingRF(pReNative, off, a_cbInstr)
+
+#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr) \
+    return iemNativeEmitAddToEip32AndFinishingClearingRF(pReNative, off, a_cbInstr)
+
+#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr) \
+    return iemNativeEmitAddToRip64AndFinishingClearingRF(pReNative, off, a_cbInstr)
+
 
 /*
@@ -1965 +2017 @@
     PIEMRECOMPILERSTATE pReNative = pVCpu->iem.s.pNativeRecompilerStateR3;
     if (RT_LIKELY(pReNative))
-        iemNativeReInit(pReNative);
+        iemNativeReInit(pReNative, pTb);
     else
     {
-        pReNative = iemNativeInit(pVCpu);
+        pReNative = iemNativeInit(pVCpu, pTb);
         AssertReturn(pReNative, pTb);
     }

trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp

@@ -80 +80 @@
  *  and only used when we're in 16-bit code on a pre-386 CPU. */
 #define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr) \
-    return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr)
+    return iemRegAddToIp16AndFinishingNoFlags(pVCpu, a_cbInstr)
 
 /** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
  *  and used for 16-bit and 32-bit code on 386 and later CPUs. */
 #define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr) \
-    return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
+    return iemRegAddToEip32AndFinishingNoFlags(pVCpu, a_cbInstr)
 
 /** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
  *  and only used when we're in 64-bit code. */
 #define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr) \
+    return iemRegAddToRip64AndFinishingNoFlags(pVCpu, a_cbInstr)
+
+
+/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
+ *  and only used when we're in 16-bit code on a pre-386 CPU and we need to
+ *  check and clear flags. */
+#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr) \
+    return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr)
+
+/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
+ *  and used for 16-bit and 32-bit code on 386 and later CPUs and we need to
+ *  check and clear flags. */
+#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr) \
+    return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
+
+/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
+ *  and only used when we're in 64-bit code and we need to check and clear
+ *  flags. */
+#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr) \
     return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr)
 
@@ -98 +117 @@
  *  parameter, for use in 16-bit code on a pre-386 CPU. */
 #define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr) \
-    return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8))
+    return iemRegIp16RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8))
 
 /** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
@@ -104 +123 @@
  * later CPUs. */
 #define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize) \
-    return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
+    return iemRegEip32RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
 
 /** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
  * size as extra parameters, for use in 64-bit code. */
 #define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize) \
+    return iemRegRip64RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
+
+
+/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
+ *  parameter, for use in 16-bit code on a pre-386 CPU and we need to check and
+ *  clear flags. */
+#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i8, a_cbInstr) \
+    return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8))
+
+/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
+ * size as extra parameters, for use in 16-bit and 32-bit code on 386 and
+ * later CPUs and we need to check and clear flags. */
+#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize) \
+    return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
+
+/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
+ * size as extra parameters, for use in 64-bit code and we need to check and
+ * clear flags. */
+#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize) \
     return iemRegRip64RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
 
@@ -117 +155 @@
  *  param, for use in 16-bit code on a pre-386 CPU. */
 #define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr) \
-    return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
+    return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
 
 /** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
  *  param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
 #define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr) \
-    return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
+    return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
 
 /** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
  *  param, for use in 64-bit code. */
 #define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr) \
+    return iemRegRip64RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
+
+
+/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
+ *  param, for use in 16-bit code on a pre-386 CPU and we need to check and
+ *  clear flags. */
+#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i16, a_cbInstr) \
+    return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
+
+/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
+ *  param, for use in 16-bit and 32-bit code on 386 and later CPUs and we need
+ *  to check and clear flags. */
+#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i16, a_cbInstr) \
+    return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
+
+/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
+ *  param, for use in 64-bit code and we need to check and clear flags. */
+#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i16, a_cbInstr) \
     return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
 
@@ -141 +197 @@
  *  an extra parameter, for use in 16-bit and 32-bit code on 386+. */
 #define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr) \
-    return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
+    return iemRegEip32RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32))
 
 /** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
  *  an extra parameter, for use in 64-bit code. */
 #define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr) \
+    return iemRegRip64RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32))
+
+
+/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
+ *  an extra parameter - dummy for pre-386 variations not eliminated by the
+ *  python script. */
+#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i32, a_cbInstr) \
+    do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
+
+/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
+ *  an extra parameter, for use in 16-bit and 32-bit code on 386+ and we need
+ *  to check and clear flags. */
+#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i32, a_cbInstr) \
+    return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
+
+/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
+ *  an extra parameter, for use in 64-bit codeand we need to check and clear
+ *  flags. */
+#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i32, a_cbInstr) \
     return iemRegRip64RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
 
@@ -155 +230 @@
     (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
 
-/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, pre-386 16-bit. */
-#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_PRE386(a_GCPtrEff, a_bRm, a_u16Disp) \
-    IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
-
-/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit with address prefix. */
-#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_ADDR16(a_GCPtrEff, a_bRm, a_u16Disp) \
-    IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
-
-
 /** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
 #define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
     (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
-
-/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit flat. */
-#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_FLAT(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
-    (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
-
-/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit with address prefix. */
-#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_ADDR32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
-    (a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
-
 
 /** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */

trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py

@@ -41 +41 @@
 import sys;
 import argparse;
+from typing import Dict, List;
 
 import IEMAllInstPython as iai;
@@ -134 +135 @@
     ksVariation_Default     = '';               ##< No variations - only used by IEM_MC_DEFER_TO_CIMPL_X_RET.
     ksVariation_16          = '_16';            ##< 16-bit mode code (386+).
+    ksVariation_16f         = '_16f';           ##< 16-bit mode code (386+), check+clear eflags.
     ksVariation_16_Addr32   = '_16_Addr32';     ##< 16-bit mode code (386+), address size prefixed to 32-bit addressing.
+    ksVariation_16f_Addr32  = '_16f_Addr32';    ##< 16-bit mode code (386+), address size prefixed to 32-bit addressing, eflags.
     ksVariation_16_Pre386   = '_16_Pre386';     ##< 16-bit mode code, pre-386 CPU target.
+    ksVariation_16f_Pre386  = '_16f_Pre386';    ##< 16-bit mode code, pre-386 CPU target, check+clear eflags.
     ksVariation_32          = '_32';            ##< 32-bit mode code (386+).
+    ksVariation_32f         = '_32f';           ##< 32-bit mode code (386+), check+clear eflags.
     ksVariation_32_Flat     = '_32_Flat';       ##< 32-bit mode code (386+) with CS, DS, E,S and SS flat and 4GB wide.
+    ksVariation_32f_Flat    = '_32f_Flat';      ##< 32-bit mode code (386+) with CS, DS, E,S and SS flat and 4GB wide, eflags.
     ksVariation_32_Addr16   = '_32_Addr16';     ##< 32-bit mode code (386+), address size prefixed to 16-bit addressing.
+    ksVariation_32f_Addr16  = '_32f_Addr16';    ##< 32-bit mode code (386+), address size prefixed to 16-bit addressing, eflags.
     ksVariation_64          = '_64';            ##< 64-bit mode code.
+    ksVariation_64f         = '_64f';           ##< 64-bit mode code, check+clear eflags.
     ksVariation_64_FsGs     = '_64_FsGs';       ##< 64-bit mode code, with memory accesses via FS or GS.
+    ksVariation_64f_FsGs    = '_64f_FsGs';      ##< 64-bit mode code, with memory accesses via FS or GS, check+clear eflags.
     ksVariation_64_Addr32   = '_64_Addr32';     ##< 64-bit mode code, address size prefixed to 32-bit addressing.
+    ksVariation_64f_Addr32  = '_64f_Addr32';    ##< 64-bit mode code, address size prefixed to 32-bit addressing, c+c eflags.
     kasVariations           = (
         ksVariation_Default,
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Addr32,
+        ksVariation_16f_Addr32,
         ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_32_Flat,
+        ksVariation_32f_Flat,
         ksVariation_32_Addr16,
+        ksVariation_32f_Addr16,
         ksVariation_64,
+        ksVariation_64f,
         ksVariation_64_FsGs,
+        ksVariation_64f_FsGs,
         ksVariation_64_Addr32,
+        ksVariation_64f_Addr32,
     );
     kasVariationsWithoutAddress = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_64,
+        ksVariation_64f,
     );
     kasVariationsWithoutAddressNot286 = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_64,
+        ksVariation_64f,
     );
     kasVariationsWithoutAddressNot286Not64 = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_32,
+        ksVariation_32f,
     );
     kasVariationsWithoutAddressNot64 = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
         ksVariation_32,
+        ksVariation_32f,
     );
     kasVariationsWithoutAddressOnly64 = (
         ksVariation_64,
+        ksVariation_64f,
     );
     kasVariationsWithAddress = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Addr32,
+        ksVariation_16f_Addr32,
         ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_32_Flat,
+        ksVariation_32f_Flat,
         ksVariation_32_Addr16,
+        ksVariation_32f_Addr16,
         ksVariation_64,
+        ksVariation_64f,
         ksVariation_64_FsGs,
+        ksVariation_64f_FsGs,
         ksVariation_64_Addr32,
+        ksVariation_64f_Addr32,
     );
     kasVariationsWithAddressNot286 = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Addr32,
+        ksVariation_16f_Addr32,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_32_Flat,
+        ksVariation_32f_Flat,
         ksVariation_32_Addr16,
+        ksVariation_32f_Addr16,
         ksVariation_64,
+        ksVariation_64f,
         ksVariation_64_FsGs,
+        ksVariation_64f_FsGs,
         ksVariation_64_Addr32,
+        ksVariation_64f_Addr32,
     );
     kasVariationsWithAddressNot286Not64 = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Addr32,
+        ksVariation_16f_Addr32,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_32_Flat,
+        ksVariation_32f_Flat,
         ksVariation_32_Addr16,
+        ksVariation_32f_Addr16,
     );
     kasVariationsWithAddressNot64 = (
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Addr32,
+        ksVariation_16f_Addr32,
         ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_32_Flat,
+        ksVariation_32f_Flat,
         ksVariation_32_Addr16,
+        ksVariation_32f_Addr16,
     );
     kasVariationsWithAddressOnly64 = (
         ksVariation_64,
+        ksVariation_64f,
         ksVariation_64_FsGs,
+        ksVariation_64f_FsGs,
         ksVariation_64_Addr32,
+        ksVariation_64f_Addr32,
+    );
+    kasVariationsOnlyPre386 = (
+        ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
     );
     kasVariationsEmitOrder = (
         ksVariation_Default,
         ksVariation_64,
+        ksVariation_64f,
         ksVariation_64_FsGs,
+        ksVariation_64f_FsGs,
         ksVariation_32_Flat,
+        ksVariation_32f_Flat,
         ksVariation_32,
+        ksVariation_32f,
         ksVariation_16,
+        ksVariation_16f,
         ksVariation_16_Addr32,
+        ksVariation_16f_Addr32,
         ksVariation_16_Pre386,
+        ksVariation_16f_Pre386,
         ksVariation_32_Addr16,
+        ksVariation_32f_Addr16,
         ksVariation_64_Addr32,
+        ksVariation_64f_Addr32,
     );
     kdVariationNames = {
         ksVariation_Default:    'defer-to-cimpl',
         ksVariation_16:         '16-bit',
+        ksVariation_16f:        '16-bit w/ eflag checking and clearing',
         ksVariation_16_Addr32:  '16-bit w/ address prefix (Addr32)',
+        ksVariation_16f_Addr32: '16-bit w/ address prefix (Addr32) and eflag checking and clearing',
         ksVariation_16_Pre386:  '16-bit on pre-386 CPU',
+        ksVariation_16f_Pre386: '16-bit on pre-386 CPU w/ eflag checking and clearing',
         ksVariation_32:         '32-bit',
+        ksVariation_32f:        '32-bit w/ eflag checking and clearing',
         ksVariation_32_Flat:    '32-bit flat and wide open CS, SS, DS and ES',
+        ksVariation_32f_Flat:   '32-bit flat and wide open CS, SS, DS and ES w/ eflag checking and clearing',
         ksVariation_32_Addr16:  '32-bit w/ address prefix (Addr16)',
+        ksVariation_32f_Addr16: '32-bit w/ address prefix (Addr16) and eflag checking and clearing',
         ksVariation_64:         '64-bit',
+        ksVariation_64f:        '64-bit w/ eflag checking and clearing',
         ksVariation_64_FsGs:    '64-bit with memory accessed via FS or GS',
+        ksVariation_64f_FsGs:   '64-bit with memory accessed via FS or GS and eflag checking and clearing',
         ksVariation_64_Addr32:  '64-bit w/ address prefix (Addr32)',
-
+        ksVariation_64f_Addr32: '64-bit w/ address prefix (Addr32) and eflag checking and clearing',
+    };
+    kdVariationsWithEflagsCheckingAndClearing = {
+        ksVariation_16f: True,
+        ksVariation_16f_Addr32: True,
+        ksVariation_16f_Pre386: True,
+        ksVariation_32f: True,
+        ksVariation_32f_Flat: True,
+        ksVariation_32f_Addr16: True,
+        ksVariation_64f: True,
+        ksVariation_64f_FsGs: True,
+        ksVariation_64f_Addr32: True,
+    };
+    kdVariationsWithFlatAddress = {
+        ksVariation_32_Flat: True,
+        ksVariation_32f_Flat: True,
+        ksVariation_64: True,
+        ksVariation_64f: True,
+    };
+    kdVariationsWithFlatAddr16 = {
+        ksVariation_16: True,
+        ksVariation_16f: True,
+        ksVariation_16_Pre386: True,
+        ksVariation_16f_Pre386: True,
+        ksVariation_32_Addr16: True,
+        ksVariation_32f_Addr16: True,
+    };
+    kdVariationsWithFlatAddr32No64 = {
+        ksVariation_16_Addr32:  True,
+        ksVariation_16f_Addr32: True,
+        ksVariation_32:         True,
+        ksVariation_32f:        True,
+        ksVariation_32_Flat:    True,
+        ksVariation_32f_Flat:   True,
     };
     ## @}
@@ -251 +368 @@
     ## @note iemThreadedRecompilerMcDeferToCImpl0 duplicates info found here.
     kdCImplFlags = {
-        'IEM_CIMPL_F_MODE':                 False,
-        'IEM_CIMPL_F_BRANCH_DIRECT':        False,
-        'IEM_CIMPL_F_BRANCH_INDIRECT':      False,
-        'IEM_CIMPL_F_BRANCH_RELATIVE':      False,
-        'IEM_CIMPL_F_BRANCH_FAR':           True,
-        'IEM_CIMPL_F_BRANCH_CONDITIONAL':   False,
-        'IEM_CIMPL_F_RFLAGS':               False,
-        'IEM_CIMPL_F_CHECK_IRQ_AFTER':      False,
-        'IEM_CIMPL_F_CHECK_IRQ_BEFORE':     False,
-        'IEM_CIMPL_F_STATUS_FLAGS':         False,
-        'IEM_CIMPL_F_VMEXIT':               False,
-        'IEM_CIMPL_F_FPU':                  False,
-        'IEM_CIMPL_F_REP':                  False,
-        'IEM_CIMPL_F_IO':                   False,
-        'IEM_CIMPL_F_END_TB':               True,
-        'IEM_CIMPL_F_XCPT':                 True,
+        'IEM_CIMPL_F_MODE':                         False,
+        'IEM_CIMPL_F_BRANCH_DIRECT':                False,
+        'IEM_CIMPL_F_BRANCH_INDIRECT':              False,
+        'IEM_CIMPL_F_BRANCH_RELATIVE':              False,
+        'IEM_CIMPL_F_BRANCH_FAR':                   True,
+        'IEM_CIMPL_F_BRANCH_CONDITIONAL':           False,
+        # IEM_CIMPL_F_BRANCH_ANY should only be used for testing, so not included here.
+        'IEM_CIMPL_F_RFLAGS':                       False,
+        'IEM_CIMPL_F_INHIBIT_SHADOW':               False,
+        'IEM_CIMPL_F_CHECK_IRQ_AFTER':              False,
+        'IEM_CIMPL_F_CHECK_IRQ_BEFORE':             False,
+        'IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER':   False, # (ignore)
+        'IEM_CIMPL_F_STATUS_FLAGS':                 False,
+        'IEM_CIMPL_F_VMEXIT':                       False,
+        'IEM_CIMPL_F_FPU':                          False,
+        'IEM_CIMPL_F_REP':                          False,
+        'IEM_CIMPL_F_IO':                           False,
+        'IEM_CIMPL_F_END_TB':                       True,
+        'IEM_CIMPL_F_XCPT':                         True,
     };
 
@@ -275 +395 @@
 
         ## Threaded function parameter references.
-        self.aoParamRefs    = []            # type: list(ThreadedParamRef)
+        self.aoParamRefs    = []            # type: List[ThreadedParamRef]
         ## Unique parameter references.
-        self.dParamRefs     = {}            # type: dict(str,list(ThreadedParamRef))
+        self.dParamRefs     = {}            # type: Dict[str, List[ThreadedParamRef]]
         ## Minimum number of parameters to the threaded function.
         self.cMinParams     = 0;
 
         ## List/tree of statements for the threaded function.
-        self.aoStmtsForThreadedFunction = [] # type: list(McStmt)
-
-        ## Dictionary with any IEM_CIMPL_F_XXX flags associated to the code block.
-        self.dsCImplFlags   = { }           # type: dict(str, bool)
+        self.aoStmtsForThreadedFunction = [] # type: List[McStmt]
 
         ## Function enum number, for verification. Set by generateThreadedFunctionsHeader.
@@ -554 +671 @@
     };
 
+    kdThreadedCalcRmEffAddrMcByVariation = {
+        ksVariation_16:             'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16',
+        ksVariation_16f:            'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16',
+        ksVariation_16_Pre386:      'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16',
+        ksVariation_16f_Pre386:     'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16',
+        ksVariation_32_Addr16:      'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16',
+        ksVariation_32f_Addr16:     'IEM_MC_CALC_RM_EFF_ADDR_THREADED_16',
+        ksVariation_16_Addr32:      'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32',
+        ksVariation_16f_Addr32:     'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32',
+        ksVariation_32:             'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32',
+        ksVariation_32f:            'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32',
+        ksVariation_32_Flat:        'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32',
+        ksVariation_32f_Flat:       'IEM_MC_CALC_RM_EFF_ADDR_THREADED_32',
+        ksVariation_64:             'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64',
+        ksVariation_64f:            'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64',
+        ksVariation_64_FsGs:        'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS',
+        ksVariation_64f_FsGs:       'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS',
+        ksVariation_64_Addr32:      'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32', ## @todo How did this work again...
+        ksVariation_64f_Addr32:     'IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32',
+    };
+
     def analyzeMorphStmtForThreaded(self, aoStmts, iParamRef = 0):
         """
@@ -602 +740 @@
                 # Morph IEM_MC_CALC_RM_EFF_ADDR into IEM_MC_CALC_RM_EFF_ADDR_THREADED ...
                 if oNewStmt.sName == 'IEM_MC_CALC_RM_EFF_ADDR':
-                    assert self.sVariation != self.ksVariation_Default;
-                    oNewStmt.sName = 'IEM_MC_CALC_RM_EFF_ADDR_THREADED' + self.sVariation.upper();
+                    oNewStmt.sName = self.kdThreadedCalcRmEffAddrMcByVariation[self.sVariation];
                     assert len(oNewStmt.asParams) == 3;
 
-                    if self.sVariation in (self.ksVariation_16, self.ksVariation_16_Pre386, self.ksVariation_32_Addr16):
+                    if self.sVariation in self.kdVariationsWithFlatAddr16:
                         oNewStmt.asParams = [
                             oNewStmt.asParams[0], oNewStmt.asParams[1], self.dParamRefs['u16Disp'][0].sNewName,
@@ -615 +752 @@
                             sSibAndMore = '(%s) | ((%s) & 0x0f00)' % (self.dParamRefs['bSib'][0].sNewName, oStmt.asParams[2]);
 
-                        if self.sVariation in (self.ksVariation_32, self.ksVariation_32_Flat, self.ksVariation_16_Addr32):
+                        if self.sVariation in self.kdVariationsWithFlatAddr32No64:
                             oNewStmt.asParams = [
                                 oNewStmt.asParams[0], oNewStmt.asParams[1], sSibAndMore, self.dParamRefs['u32Disp'][0].sNewName,
@@ -624 +761 @@
                                 self.dParamRefs['u32Disp'][0].sNewName, self.dParamRefs['cbInstr'][0].sNewName,
                             ];
-                # ... and IEM_MC_ADVANCE_RIP_AND_FINISH into *_THREADED and maybe *_LM64/_NOT64 ...
+                # ... and IEM_MC_ADVANCE_RIP_AND_FINISH into *_THREADED_PCxx[_WITH_FLAGS] ...
                 elif oNewStmt.sName in ('IEM_MC_ADVANCE_RIP_AND_FINISH', 'IEM_MC_REL_JMP_S8_AND_FINISH',
                                         'IEM_MC_REL_JMP_S16_AND_FINISH', 'IEM_MC_REL_JMP_S32_AND_FINISH'):
                     oNewStmt.asParams.append(self.dParamRefs['cbInstr'][0].sNewName);
                     if (    oNewStmt.sName in ('IEM_MC_REL_JMP_S8_AND_FINISH', )
-                        and self.sVariation != self.ksVariation_16_Pre386):
+                        and self.sVariation not in (self.ksVariation_16_Pre386, self.ksVariation_16f_Pre386,)):
                         oNewStmt.asParams.append(self.dParamRefs['pVCpu->iem.s.enmEffOpSize'][0].sNewName);
                     oNewStmt.sName += '_THREADED';
-                    if self.sVariation in (self.ksVariation_64, self.ksVariation_64_FsGs, self.ksVariation_64_Addr32):
+                    if   self.sVariation in (self.ksVariation_64,  self.ksVariation_64_FsGs,  self.ksVariation_64_Addr32):
                         oNewStmt.sName += '_PC64';
+                    elif self.sVariation in (self.ksVariation_64f, self.ksVariation_64f_FsGs, self.ksVariation_64f_Addr32):
+                        oNewStmt.sName += '_PC64_WITH_FLAGS';
                     elif self.sVariation == self.ksVariation_16_Pre386:
                         oNewStmt.sName += '_PC16';
-                    elif self.sVariation != self.ksVariation_Default:
+                    elif self.sVariation == self.ksVariation_16f_Pre386:
+                        oNewStmt.sName += '_PC16_WITH_FLAGS';
+                    elif self.sVariation not in self.kdVariationsWithEflagsCheckingAndClearing:
+                        assert self.sVariation != self.ksVariation_Default;
                         oNewStmt.sName += '_PC32';
+                    else:
+                        oNewStmt.sName += '_PC32_WITH_FLAGS';
 
                 # ... and IEM_MC_*_GREG_U8 into *_THREADED w/ reworked index taking REX into account
@@ -651 +795 @@
 
                 # ... and in FLAT modes we must morph memory access into FLAT accesses ...
-                elif (    self.sVariation in (self.ksVariation_64, self.ksVariation_32_Flat,)
+                elif (    self.sVariation in self.kdVariationsWithFlatAddress
                       and (   oNewStmt.sName.startswith('IEM_MC_FETCH_MEM')
                            or (oNewStmt.sName.startswith('IEM_MC_STORE_MEM_') and oNewStmt.sName.find('_BY_REF') < 0)
@@ -665 +809 @@
 
                 # ... PUSH and POP also needs flat variants, but these differ a little.
-                elif (    self.sVariation in (self.ksVariation_64, self.ksVariation_32_Flat,)
+                elif (    self.sVariation in self.kdVariationsWithFlatAddress
                       and (   (oNewStmt.sName.startswith('IEM_MC_PUSH') and oNewStmt.sName.find('_FPU') < 0)
                            or oNewStmt.sName.startswith('IEM_MC_POP'))):
-                    oNewStmt.sName = self.kdMemMcToFlatInfoStack[oNewStmt.sName][int(self.sVariation == self.ksVariation_64)];
+                    oNewStmt.sName = self.kdMemMcToFlatInfoStack[oNewStmt.sName][int(self.sVariation in (self.ksVariation_64,
+                                                                                                         self.ksVariation_64f,))];
 
 
@@ -678 +823 @@
 
         return (aoThreadedStmts, iParamRef);
-
-
-    def analyzeCodeOperation(self, aoStmts, fSeenConditional = False):
-        """
-        Analyzes the code looking clues as to additional side-effects.
-
-        Currently this is simply looking for any IEM_IMPL_C_F_XXX flags and
-        collecting these in self.dsCImplFlags.
-        """
-        for oStmt in aoStmts:
-            # Pick up hints from CIMPL calls and deferals.
-            if oStmt.sName.startswith('IEM_MC_CALL_CIMPL_') or oStmt.sName.startswith('IEM_MC_DEFER_TO_CIMPL_'):
-                sFlagsSansComments = iai.McBlock.stripComments(oStmt.asParams[0]);
-                for sFlag in sFlagsSansComments.split('|'):
-                    sFlag = sFlag.strip();
-                    if sFlag != '0':
-                        if sFlag in self.kdCImplFlags:
-                            self.dsCImplFlags[sFlag] = True;
-                        elif sFlag == 'IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER':
-                            self.dsCImplFlags['IEM_CIMPL_F_CHECK_IRQ_BEFORE'] = True;
-                            self.dsCImplFlags['IEM_CIMPL_F_CHECK_IRQ_AFTER']  = True;
-                        else:
-                            self.raiseProblem('Unknown CIMPL flag value: %s' % (sFlag,));
-
-            # Set IEM_IMPL_C_F_BRANCH if we see any branching MCs.
-            elif oStmt.sName.startswith('IEM_MC_SET_RIP'):
-                assert not fSeenConditional;
-                self.dsCImplFlags['IEM_CIMPL_F_BRANCH_INDIRECT'] = True;
-            elif oStmt.sName.startswith('IEM_MC_REL_JMP'):
-                self.dsCImplFlags['IEM_CIMPL_F_BRANCH_RELATIVE'] = True;
-                if fSeenConditional:
-                    self.dsCImplFlags['IEM_CIMPL_F_BRANCH_CONDITIONAL'] = True;
-
-            # Process branches of conditionals recursively.
-            if isinstance(oStmt, iai.McStmtCond):
-                self.analyzeCodeOperation(oStmt.aoIfBranch, True);
-                if oStmt.aoElseBranch:
-                    self.analyzeCodeOperation(oStmt.aoElseBranch, True);
-
-        return True;
 
 
@@ -760 +865 @@
 
         # Organize them by size too for the purpose of optimize them.
-        dBySize = {}        # type: dict(str,str)
+        dBySize = {}        # type: Dict[str, str]
         for sStdRef, aoRefs in self.dParamRefs.items():
             if aoRefs[0].sType[0] != 'P':
@@ -829 +934 @@
 
             if (    oStmt.sName in ('IEM_MC_REL_JMP_S8_AND_FINISH',)
-                and self.sVariation != self.ksVariation_16_Pre386):
+                and self.sVariation not in (self.ksVariation_16_Pre386, self.ksVariation_16f_Pre386,)):
                 self.aoParamRefs.append(ThreadedParamRef('pVCpu->iem.s.enmEffOpSize', 'IEMMODE', oStmt));
 
@@ -837 +942 @@
                 assert oStmt.asParams[1] == 'bRm';
 
-                if self.sVariation in (self.ksVariation_16, self.ksVariation_16_Pre386, self.ksVariation_32_Addr16):
+                if self.sVariation in self.kdVariationsWithFlatAddr16:
                     self.aoParamRefs.append(ThreadedParamRef('bRm',     'uint8_t',  oStmt));
                     self.aoParamRefs.append(ThreadedParamRef('(uint16_t)uEffAddrInfo' ,
                                                              'uint16_t', oStmt, sStdRef = 'u16Disp'));
-                elif self.sVariation in (self.ksVariation_32, self.ksVariation_32_Flat, self.ksVariation_16_Addr32):
+                elif self.sVariation in self.kdVariationsWithFlatAddr32No64:
                     self.aoParamRefs.append(ThreadedParamRef('bRm',     'uint8_t',  oStmt));
                     self.aoParamRefs.append(ThreadedParamRef('(uint8_t)(uEffAddrInfo >> 32)',
@@ -848 +953 @@
                                                              'uint32_t', oStmt, sStdRef = 'u32Disp'));
                 else:
-                    assert self.sVariation in (self.ksVariation_64, self.ksVariation_64_FsGs, self.ksVariation_64_Addr32);
+                    assert self.sVariation in self.kasVariationsWithAddressOnly64;
                     self.aoParamRefs.append(ThreadedParamRef('IEM_GET_MODRM_EX(pVCpu, bRm)',
                                                              'uint8_t',  oStmt, sStdRef = 'bRmEx'));
@@ -866 +971 @@
 
             # If in flat mode variation, ignore the effective segment parameter to memory MCs.
-            if (    self.sVariation in (self.ksVariation_64, self.ksVariation_32_Flat,)
+            if (    self.sVariation in self.kdVariationsWithFlatAddress
                 and oStmt.sName in self.kdMemMcToFlatInfo
                 and self.kdMemMcToFlatInfo[oStmt.sName][0] != -1):
@@ -1042 +1147 @@
         self.analyzeConsolidateThreadedParamRefs();
 
-        # Scan the code for IEM_CIMPL_F_ and other clues.
-        self.analyzeCodeOperation(aoStmts);
-
         # Morph the statement stream for the block into what we'll be using in the threaded function.
         (self.aoStmtsForThreadedFunction, iParamRef) = self.analyzeMorphStmtForThreaded(aoStmts);
@@ -1060 +1162 @@
         """
         aoStmts = [
-            iai.McCppCall('IEM_MC2_BEGIN_EMIT_CALLS', ['1' if 'IEM_CIMPL_F_CHECK_IRQ_BEFORE' in self.dsCImplFlags else '0'],
+            iai.McCppCall('IEM_MC2_BEGIN_EMIT_CALLS',
+                          ['1' if 'IEM_CIMPL_F_CHECK_IRQ_BEFORE' in self.oParent.dsCImplFlags else '0'],
                           cchIndent = cchIndent), # Scope and a hook for various stuff.
         ];
@@ -1085 +1188 @@
         # For CIMPL stuff, we need to consult the associated IEM_CIMPL_F_XXX
         # mask and maybe emit additional checks.
-        if (   'IEM_CIMPL_F_MODE'   in self.dsCImplFlags
-            or 'IEM_CIMPL_F_XCPT'   in self.dsCImplFlags
-            or 'IEM_CIMPL_F_VMEXIT' in self.dsCImplFlags):
+        if (   'IEM_CIMPL_F_MODE'   in self.oParent.dsCImplFlags
+            or 'IEM_CIMPL_F_XCPT'   in self.oParent.dsCImplFlags
+            or 'IEM_CIMPL_F_VMEXIT' in self.oParent.dsCImplFlags):
             aoStmts.append(iai.McCppCall('IEM_MC2_EMIT_CALL_1', ( 'kIemThreadedFunc_BltIn_CheckMode', 'pVCpu->iem.s.fExec', ),
                                          cchIndent = cchIndent));
 
-        sCImplFlags = ' | '.join(self.dsCImplFlags.keys());
+        sCImplFlags = ' | '.join(self.oParent.dsCImplFlags.keys());
         if not sCImplFlags:
             sCImplFlags = '0'
@@ -1101 +1204 @@
         asEndTbFlags      = [];
         asTbBranchedFlags = [];
-        for sFlag in self.dsCImplFlags:
+        for sFlag in self.oParent.dsCImplFlags:
             if self.kdCImplFlags[sFlag] is True:
                 asEndTbFlags.append(sFlag);
@@ -1114 +1217 @@
                                             cchIndent = cchIndent));
 
-        if 'IEM_CIMPL_F_CHECK_IRQ_AFTER' in self.dsCImplFlags:
+        if 'IEM_CIMPL_F_CHECK_IRQ_AFTER' in self.oParent.dsCImplFlags:
             aoStmts.append(iai.McCppGeneric('pVCpu->iem.s.cInstrTillIrqCheck = 0;', cchIndent = cchIndent));
 
@@ -1125 +1228 @@
     """
 
-    def __init__(self, oMcBlock):
-        self.oMcBlock       = oMcBlock      # type: IEMAllInstPython.McBlock
+    def __init__(self, oMcBlock: iai.McBlock) -> None:
+        self.oMcBlock       = oMcBlock      # type: iai.McBlock
+        # The remaining fields are only useful after analyze() has been called:
         ## Variations for this block. There is at least one.
-        self.aoVariations   = []            # type: list(ThreadedFunctionVariation)
+        self.aoVariations   = []            # type: List[ThreadedFunctionVariation]
         ## Variation dictionary containing the same as aoVariations.
-        self.dVariations    = {}            # type: dict(str,ThreadedFunctionVariation)
+        self.dVariations    = {}            # type: Dict[str, ThreadedFunctionVariation]
         ## Dictionary of local variables (IEM_MC_LOCAL[_CONST]) and call arguments (IEM_MC_ARG*).
-        self.dVariables     = {}            # type: dict(str,McStmtVar)
+        self.dVariables     = {}            # type: Dict[str, iai.McStmtVar]
+        ## Dictionary with any IEM_CIMPL_F_XXX flags explicitly advertised in the code block
+        ## and those determined by analyzeCodeOperation().
+        self.dsCImplFlags   = {}            # type: Dict[str, bool]
 
     @staticmethod
@@ -1148 +1255 @@
         print('%s:%s: warning: %s' % (self.oMcBlock.sSrcFile, self.oMcBlock.iBeginLine, sMessage, ));
 
-    def analyzeFindVariablesAndCallArgs(self, aoStmts):
+    def analyzeFindVariablesAndCallArgs(self, aoStmts: List[iai.McStmt]) -> bool:
         """ Scans the statements for MC variables and call arguments. """
         for oStmt in aoStmts:
@@ -1166 +1273 @@
         return True;
 
+    def analyzeCodeOperation(self, aoStmts: List[iai.McStmt], fSeenConditional = False) -> bool:
+        """
+        Analyzes the code looking clues as to additional side-effects.
+
+        Currently this is simply looking for branching and adding the relevant
+        branch flags to dsCImplFlags.  ASSUMES the caller pre-populates the
+        dictionary with a copy of self.oMcBlock.dsCImplFlags.
+        """
+        for oStmt in aoStmts:
+            # Set IEM_IMPL_C_F_BRANCH if we see any branching MCs.
+            if oStmt.sName.startswith('IEM_MC_SET_RIP'):
+                assert not fSeenConditional;
+                self.dsCImplFlags['IEM_CIMPL_F_BRANCH_INDIRECT'] = True;
+            elif oStmt.sName.startswith('IEM_MC_REL_JMP'):
+                self.dsCImplFlags['IEM_CIMPL_F_BRANCH_RELATIVE'] = True;
+                if fSeenConditional:
+                    self.dsCImplFlags['IEM_CIMPL_F_BRANCH_CONDITIONAL'] = True;
+
+            # Process branches of conditionals recursively.
+            if isinstance(oStmt, iai.McStmtCond):
+                self.analyzeCodeOperation(oStmt.aoIfBranch, True);
+                if oStmt.aoElseBranch:
+                    self.analyzeCodeOperation(oStmt.aoElseBranch, True);
+
+        return True;
+
     def analyze(self):
         """
@@ -1184 +1317 @@
         # Scan the statements for local variables and call arguments (self.dVariables).
         self.analyzeFindVariablesAndCallArgs(aoStmts);
+
+        # Scan the code for IEM_CIMPL_F_ and other clues.
+        self.dsCImplFlags = self.oMcBlock.dsCImplFlags.copy();
+        self.analyzeCodeOperation(aoStmts);
 
         # Create variations as needed.
@@ -1191 +1328 @@
                                         'IEM_MC_DEFER_TO_CIMPL_2_RET': True,
                                         'IEM_MC_DEFER_TO_CIMPL_3_RET': True, }):
-            asVariations = [ThreadedFunctionVariation.ksVariation_Default,];
+            asVariations = (ThreadedFunctionVariation.ksVariation_Default,);
 
         elif iai.McStmt.findStmtByNames(aoStmts, {'IEM_MC_CALC_RM_EFF_ADDR' : True,}):
-            if 'IEM_MC_F_64BIT' in self.oMcBlock.dMcFlags:
+            if 'IEM_MC_F_64BIT' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithAddressOnly64;
-            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dMcFlags and 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dMcFlags:
+            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dsMcFlags and 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithAddressNot286Not64;
-            elif 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dMcFlags:
+            elif 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithAddressNot286;
-            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dMcFlags:
+            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithAddressNot64;
-            elif 'IEM_MC_F_ONLY_8086' in self.oMcBlock.dMcFlags:
-                asVariations = [ThreadedFunctionVariation.ksVariation_16_Pre386,];
+            elif 'IEM_MC_F_ONLY_8086' in self.oMcBlock.dsMcFlags:
+                asVariations = ThreadedFunctionVariation.kasVariationsOnlyPre386;
             else:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithAddress;
         else:
-            if 'IEM_MC_F_64BIT' in self.oMcBlock.dMcFlags:
+            if 'IEM_MC_F_64BIT' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithoutAddressOnly64;
-            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dMcFlags and 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dMcFlags:
+            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dsMcFlags and 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithoutAddressNot286Not64;
-            elif 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dMcFlags:
+            elif 'IEM_MC_F_NOT_286_OR_OLDER' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithoutAddressNot286;
-            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dMcFlags:
+            elif 'IEM_MC_F_NOT_64BIT' in self.oMcBlock.dsMcFlags:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithoutAddressNot64;
-            elif 'IEM_MC_F_ONLY_8086' in self.oMcBlock.dMcFlags:
-                asVariations = [ThreadedFunctionVariation.ksVariation_16_Pre386,];
+            elif 'IEM_MC_F_ONLY_8086' in self.oMcBlock.dsMcFlags:
+                asVariations = ThreadedFunctionVariation.kasVariationsOnlyPre386;
             else:
                 asVariations = ThreadedFunctionVariation.kasVariationsWithoutAddress;
+
+        if not iai.McStmt.findStmtByNames(aoStmts,
+                                          { 'IEM_MC_ADVANCE_RIP_AND_FINISH': True,
+                                            'IEM_MC_REL_JMP_S8_AND_FINISH':  True,
+                                            'IEM_MC_REL_JMP_S16_AND_FINISH': True,
+                                            'IEM_MC_REL_JMP_S32_AND_FINISH': True,
+                                           }):
+            asVariations = [sVariation for sVariation in asVariations
+                            if sVariation not in ThreadedFunctionVariation.kdVariationsWithEflagsCheckingAndClearing];
 
         self.aoVariations = [ThreadedFunctionVariation(self, sVar) for sVar in asVariations];
@@ -1230 +1376 @@
 
         return True;
+
+    ## Used by emitThreadedCallStmts.
+    kdVariationsWithNeedForPrefixCheck = {
+        ThreadedFunctionVariation.ksVariation_64_Addr32:  True,
+        ThreadedFunctionVariation.ksVariation_64f_Addr32: True,
+        ThreadedFunctionVariation.ksVariation_64_FsGs:    True,
+        ThreadedFunctionVariation.ksVariation_64f_FsGs:   True,
+        ThreadedFunctionVariation.ksVariation_32_Addr16:  True,
+        ThreadedFunctionVariation.ksVariation_32f_Addr16: True,
+        ThreadedFunctionVariation.ksVariation_32_Flat:    True,
+        ThreadedFunctionVariation.ksVariation_32f_Flat:   True,
+        ThreadedFunctionVariation.ksVariation_16_Addr32:  True,
+        ThreadedFunctionVariation.ksVariation_16f_Addr32: True,
+    };
 
     def emitThreadedCallStmts(self):
@@ -1305 +1465 @@
         fSimple = True;
         sSwitchValue  = '(pVCpu->iem.s.fExec & (IEM_F_MODE_CPUMODE_MASK | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK))';
-        if (   ThrdFnVar.ksVariation_64_Addr32 in dByVari
-            or ThrdFnVar.ksVariation_64_FsGs   in dByVari
-            or ThrdFnVar.ksVariation_32_Addr16 in dByVari
-            or ThrdFnVar.ksVariation_32_Flat   in dByVari
-            or ThrdFnVar.ksVariation_16_Addr32 in dByVari):
+        if dByVari.keys() & self.kdVariationsWithNeedForPrefixCheck.keys():
             sSwitchValue += ' | (pVCpu->iem.s.enmEffAddrMode == (pVCpu->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK) ? 0 : 8)';
             # Accesses via FS and GS and CS goes thru non-FLAT functions. (CS
@@ -1316 +1472 @@
             sSwitchValue += ' | (pVCpu->iem.s.iEffSeg < X86_SREG_FS && pVCpu->iem.s.iEffSeg != X86_SREG_CS ? 0 : 16)';
             fSimple       = False;                                              # threaded functions.
+        if dByVari.keys() & ThreadedFunctionVariation.kdVariationsWithEflagsCheckingAndClearing:
+            sSwitchValue += ' | ((pVCpu->iem.s.fTbPrevInstr & (IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_INHIBIT_SHADOW)) || ' \
+                          + '(pVCpu->iem.s.fExec & IEM_F_PENDING_BRK_MASK) ? 32 : 0)';
 
         #
@@ -1330 +1489 @@
                 Case('IEMMODE_64BIT | 8',   ThrdFnVar.ksVariation_64_Addr32),
             ]);
+            if ThreadedFunctionVariation.ksVariation_64f_Addr32 in dByVari:
+                aoCases.extend([
+                    Case('IEMMODE_64BIT | 32',       ThrdFnVar.ksVariation_64f),
+                    Case('IEMMODE_64BIT | 32 | 16',  ThrdFnVar.ksVariation_64f_FsGs),
+                    Case('IEMMODE_64BIT | 32 | 8 | 16', None), # fall thru
+                    Case('IEMMODE_64BIT | 32 | 8',   ThrdFnVar.ksVariation_64f_Addr32),
+                ]);
         elif ThrdFnVar.ksVariation_64 in dByVari:
             assert fSimple;
             aoCases.append(Case('IEMMODE_64BIT', ThrdFnVar.ksVariation_64));
+            if ThreadedFunctionVariation.ksVariation_64f in dByVari:
+                aoCases.append(Case('IEMMODE_64BIT | 32', ThrdFnVar.ksVariation_64f));
 
         if ThrdFnVar.ksVariation_32_Addr16 in dByVari:
@@ -1339 +1507 @@
                 Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK',         ThrdFnVar.ksVariation_32_Flat),
                 Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 16',    None), # fall thru
-                Case('IEMMODE_32BIT | 16',                                          None), # fall thru
+                Case('IEMMODE_32BIT                                       | 16',    None), # fall thru
                 Case('IEMMODE_32BIT',                                               ThrdFnVar.ksVariation_32),
                 Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 8',     None), # fall thru
@@ -1346 +1514 @@
                 Case('IEMMODE_32BIT                                       | 8',     ThrdFnVar.ksVariation_32_Addr16),
             ]);
+            if ThrdFnVar.ksVariation_32f_Addr16 in dByVari:
+                aoCases.extend([
+                    Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 32',         ThrdFnVar.ksVariation_32f_Flat),
+                    Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 32 | 16',    None), # fall thru
+                    Case('IEMMODE_32BIT                                       | 32 | 16',    None), # fall thru
+                    Case('IEMMODE_32BIT                                       | 32',         ThrdFnVar.ksVariation_32f),
+                    Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 32 | 8',     None), # fall thru
+                    Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 32 | 8 | 16',None), # fall thru
+                    Case('IEMMODE_32BIT                                       | 32 | 8 | 16',None), # fall thru
+                    Case('IEMMODE_32BIT                                       | 32 | 8',     ThrdFnVar.ksVariation_32f_Addr16),
+                ]);
         elif ThrdFnVar.ksVariation_32 in dByVari:
             assert fSimple;
@@ -1352 +1531 @@
                 Case('IEMMODE_32BIT',                                       ThrdFnVar.ksVariation_32),
             ]);
+            if ThrdFnVar.ksVariation_32f in dByVari:
+                aoCases.extend([
+                    Case('IEMMODE_32BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 32', None), # fall thru
+                    Case('IEMMODE_32BIT                                       | 32', ThrdFnVar.ksVariation_32f),
+                ]);
 
         if ThrdFnVar.ksVariation_16_Addr32 in dByVari:
@@ -1361 +1545 @@
                 Case('IEMMODE_16BIT | 8',       ThrdFnVar.ksVariation_16_Addr32),
             ]);
+            if ThrdFnVar.ksVariation_16f_Addr32 in dByVari:
+                aoCases.extend([
+                    Case('IEMMODE_16BIT | 32 | 16',      None), # fall thru
+                    Case('IEMMODE_16BIT | 32',           ThrdFnVar.ksVariation_16f),
+                    Case('IEMMODE_16BIT | 32 | 8 | 16',  None), # fall thru
+                    Case('IEMMODE_16BIT | 32 | 8',       ThrdFnVar.ksVariation_16f_Addr32),
+                ]);
         elif ThrdFnVar.ksVariation_16 in dByVari:
             assert fSimple;
             aoCases.append(Case('IEMMODE_16BIT', ThrdFnVar.ksVariation_16));
+            if ThrdFnVar.ksVariation_16f in dByVari:
+                aoCases.append(Case('IEMMODE_16BIT | 32', ThrdFnVar.ksVariation_16f));
 
         if ThrdFnVar.ksVariation_16_Pre386 in dByVari:
             aoCases.append(Case('IEMMODE_16BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK', ThrdFnVar.ksVariation_16_Pre386));
+        if ThrdFnVar.ksVariation_16f_Pre386 in dByVari:  # should be nested under previous if, but line too long.
+            aoCases.append(Case('IEMMODE_16BIT | IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK | 32', ThrdFnVar.ksVariation_16f_Pre386));
 
         #
@@ -1427 +1622 @@
             aoDecoderStmts.append(oNewStmt);
             #print('oNewStmt %s %s' % (oNewStmt.sName, len(oNewStmt.asParams),));
+            if oNewStmt.sName == 'IEM_MC_BEGIN' and self.dsCImplFlags:
+                oNewStmt.asParams[3] = ' | '.join(sorted(self.dsCImplFlags.keys()));
 
             # If we haven't emitted the threaded function call yet, look for
@@ -1470 +1667 @@
         if len(self.oMcBlock.aoStmts) == 1:
             # IEM_MC_DEFER_TO_CIMPL_X_RET - need to wrap in {} to make it safe to insert into random code.
-            sCode = iai.McStmt.renderCodeForList(self.morphInputCode(self.oMcBlock.aoStmts)[0],
-                                                 cchIndent = cchIndent).replace('\n', ' /* gen */\n', 1);
-            sCode = ' ' * (min(cchIndent, 2) - 2) + '{\n' \
-                  + sCode \
-                  + ' ' * (min(cchIndent, 2) - 2) + '}\n';
+            sCode = ' ' * cchIndent + 'pVCpu->iem.s.fTbCurInstr = ';
+            if self.dsCImplFlags:
+                sCode += ' | '.join(sorted(self.dsCImplFlags.keys())) + ';\n';
+            else:
+                sCode += '0;\n';
+            sCode += iai.McStmt.renderCodeForList(self.morphInputCode(self.oMcBlock.aoStmts)[0],
+                                                  cchIndent = cchIndent).replace('\n', ' /* gen */\n', 1);
+            sIndent = ' ' * (min(cchIndent, 2) - 2);
+            sCode = sIndent + '{\n' + sCode + sIndent + '}\n';
             return sCode;
 
@@ -1492 +1693 @@
 
     def __init__(self):
-        self.aoThreadedFuncs = []       # type: list(ThreadedFunction)
+        self.aoThreadedFuncs = []       # type: List[ThreadedFunction]
         self.oOptions        = None     # type: argparse.Namespace
-        self.aoParsers       = []       # type: list(IEMAllInstPython.SimpleParser)
-        self.aidxFirstFunctions = []    # type: list(int) ##< Runs parallel to aoParser giving the index of the first function.
+        self.aoParsers       = []       # type: List[IEMAllInstPython.SimpleParser]
+        self.aidxFirstFunctions = []    # type: List[int] ##< Runs parallel to aoParser giving the index of the first function.
 
     #
@@ -2070 +2271 @@
                                 or (sModified.find('IEM_MC_DEFER_TO_CIMPL_') > 0 and sModified.strip().startswith('{\n'))
                                 or sModified.startswith('pVCpu->iem.s.fEndTb = true')
+                                or sModified.startswith('pVCpu->iem.s.fTbCurInstr = ')
                                 ), 'sModified="%s"' % (sModified,);
                         oOut.write(sModified);

trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp

@@ -10 +10 @@
  *      - Level 4  (Log4) : Decoding mnemonics w/ EIP. [same as IEM]
  *      - Level 5  (Log5) : Decoding details. [same as IEM]
- *      - Level 6  (Log6) :
+ *      - Level 6  (Log6) : TB opcode range management.
  *      - Level 7  (Log7) : TB obsoletion.
  *      - Level 8  (Log8) : TB compilation.
@@ -1369 +1369 @@
  * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
  * @param   pszFunction The IEM function doing the execution.
- */
-static void iemThreadedLogCurInstr(PVMCPUCC pVCpu, const char *pszFunction) RT_NOEXCEPT
+ * @param   idxInstr    The instruction number in the block.
+ */
+static void iemThreadedLogCurInstr(PVMCPUCC pVCpu, const char *pszFunction, uint32_t idxInstr) RT_NOEXCEPT
 {
 # ifdef IN_RING3
@@ -1382 +1383 @@
 
         PCX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
-        Log2(("**** %s fExec=%x pTb=%p\n"
+        Log2(("**** %s fExec=%x pTb=%p #%u\n"
               " eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
               " eip=%08x esp=%08x ebp=%08x iopl=%d tr=%04x\n"
@@ -1388 +1389 @@
               " fsw=%04x fcw=%04x ftw=%02x mxcsr=%04x/%04x\n"
               " %s\n"
-              , pszFunction, pVCpu->iem.s.fExec, pVCpu->iem.s.pCurTbR3,
+              , pszFunction, pVCpu->iem.s.fExec, pVCpu->iem.s.pCurTbR3, idxInstr,
               pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ebx, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.esi, pVCpu->cpum.GstCtx.edi,
               pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.ebp, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, pVCpu->cpum.GstCtx.tr.Sel,
@@ -1477 +1478 @@
         pVCpu->iem.s.cInstrTillIrqCheck     = !(fExtraFlags & IEMTB_F_INHIBIT_SHADOW) ? 32 : 0;
         pVCpu->iem.s.fTbCurInstrIsSti       = false;
+        /* Force RF clearing and TF checking on first instruction in the block
+           as we don't really know what came before and should assume the worst: */
+        pVCpu->iem.s.fTbPrevInstr           = IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB;
     }
     else
@@ -1484 +1488 @@
         Assert(pVCpu->iem.s.fEndTb          == false);
         Assert(pVCpu->iem.s.fTbCrossedPage  == false);
-    }
+        pVCpu->iem.s.fTbPrevInstr           = pVCpu->iem.s.fTbCurInstr;
+    }
+    pVCpu->iem.s.fTbCurInstr                = 0;
 
 #ifdef DBGFTRACE_ENABLED
@@ -1609 +1615 @@
 bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb)
 {
+    Log6(("%04x:%08RX64: iemThreadedCompileBeginEmitCallsComplications\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
     Assert((pVCpu->iem.s.GCPhysInstrBuf & GUEST_PAGE_OFFSET_MASK) == 0);
 #if 0
@@ -1693 +1700 @@
      *        GDT/LDT entry's base address can be modified independently from
      *        the code. */
-    if (pVCpu->iem.s.fTbBranched != 0)
+    if (pVCpu->iem.s.fTbBranched != IEMBRANCHED_F_NO)
     {
         if (   !pVCpu->iem.s.fTbCrossedPage       /* 1a */
@@ -1746 +1753 @@
                 pTb->aRanges[idxRange].u2Unused    = 0;
                 pTb->cRanges++;
+                Log6(("%04x:%08RX64: new range #%u same page: offPhysPage=%#x offOpcodes=%#x\n",
+                      pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, idxRange, pTb->aRanges[idxRange].offPhysPage,
+                      pTb->aRanges[idxRange].offOpcodes));
             }
             else
@@ -1875 +1885 @@
             pTb->aRanges[idxRange].u2Unused    = 0;
             pTb->cRanges++;
+            Log6(("%04x:%08RX64: new range #%u new page (a) %u/%RGp: offPhysPage=%#x offOpcodes=%#x\n",
+                  pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, idxRange,  pTb->aRanges[idxRange].idxPhysPage, GCPhysNew,
+                  pTb->aRanges[idxRange].offPhysPage, pTb->aRanges[idxRange].offOpcodes));
 
             /* Determin which function we need to load & check. */
@@ -1898 +1911 @@
             pTb->aRanges[idxRange].u2Unused       = 0;
             pTb->cRanges++;
+            Log6(("%04x:%08RX64: new range #%u new page (b) %u/%RGp: offPhysPage=%#x offOpcodes=%#x\n",
+                  pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, idxRange,  pTb->aRanges[idxRange].idxPhysPage, GCPhysNew,
+                  pTb->aRanges[idxRange].offPhysPage, pTb->aRanges[idxRange].offOpcodes));
 
             /* Determin which function we need to load & check. */
@@ -2137 +2153 @@
         /* Process the next instruction. */
 #ifdef LOG_ENABLED
-        iemThreadedLogCurInstr(pVCpu, "CC");
+        iemThreadedLogCurInstr(pVCpu, "CC", pTb->cInstructions);
         uint16_t const uCsLog  = pVCpu->cpum.GstCtx.cs.Sel;
         uint64_t const uRipLog = pVCpu->cpum.GstCtx.rip;
@@ -2251 +2267 @@
         pVCpu->iem.s.cTbExecNative++;
 # ifdef LOG_ENABLED
-        iemThreadedLogCurInstr(pVCpu, "EXn");
+        iemThreadedLogCurInstr(pVCpu, "EXn", 0);
 # endif
         VBOXSTRICTRC const rcStrict = ((PFNIEMTBNATIVE)pTb->Native.paInstructions)(pVCpu);
@@ -2288 +2304 @@
             {
                 uRipPrev = pVCpu->cpum.GstCtx.rip;
-                iemThreadedLogCurInstr(pVCpu, "EXt");
+                iemThreadedLogCurInstr(pVCpu, "EXt", pTb->Thrd.cCalls - cCallsLeft - 1);
             }
             Log9(("%04x:%08RX64: #%d/%d - %d %s\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,

trunk/src/VBox/VMM/VMMAll/IEMAllThrdTables.h

@@ -113 +113 @@
 #define g_apfnVexMap3       g_apfnIemThreadedRecompilerVecMap3
 
+
+/*
+ * Override IEM_MC_BEGIN to take down the IEM_CIMPL_F_XXX flags.
+ */
+#undef IEM_MC_BEGIN
+#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) \
+    { \
+        pVCpu->iem.s.fTbCurInstr = (a_fCImplFlags) /*| ((a_fMcFlags) << 20*/
 
 /*
@@ -300 +308 @@
     Log8(("CImpl0: %04x:%08RX64 LB %#x: %#x %p\n",
           pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IEM_GET_INSTR_LEN(pVCpu), fFlags, pfnCImpl));
+    pVCpu->iem.s.fTbCurInstr = fFlags;
 
     IEM_MC2_BEGIN_EMIT_CALLS(fFlags & IEM_CIMPL_F_CHECK_IRQ_BEFORE);

trunk/src/VBox/VMM/include/IEMInline.h

@@ -2189 +2189 @@
 
 /**
+ * Tail method for a finish function that does't clear flags or raise \#DB.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegFinishNoFlags(PVMCPUCC pVCpu) RT_NOEXCEPT
+{
+    AssertCompile(CPUMCTX_INHIBIT_SHADOW < UINT32_MAX);
+    Assert(!(  pVCpu->cpum.GstCtx.eflags.uBoth
+             & (X86_EFL_TF | X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK)) );
+    RT_NOREF(pVCpu);
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * Updates the RIP to point to the next instruction, but does not need to clear
+ * EFLAGS.RF or CPUMCTX_INHIBIT_SHADOW nor check for debug flags.
+ *
+ * Only called from 64-bit code.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             The number of bytes to add.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToRip64AndFinishingNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
+{
+    pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rip + cbInstr;
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
+ * Updates the EIP to point to the next instruction, but does not need to clear
+ * EFLAGS.RF or CPUMCTX_INHIBIT_SHADOW nor check for debug flags.
+ *
+ * This is never from 64-bit code.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             The number of bytes to add.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToEip32AndFinishingNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
+{
+    pVCpu->cpum.GstCtx.rip = (uint32_t)(pVCpu->cpum.GstCtx.eip + cbInstr);
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
+ * Updates the IP to point to the next instruction, but does not need to clear
+ * EFLAGS.RF or CPUMCTX_INHIBIT_SHADOW nor check for debug flags.
+ *
+ * This is only ever used from 16-bit code on a pre-386 CPU.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             The number of bytes to add.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToIp16AndFinishingNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
+{
+    pVCpu->cpum.GstCtx.rip = (uint16_t)(pVCpu->cpum.GstCtx.ip + cbInstr);
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
  * Adds a 8-bit signed jump offset to RIP from 64-bit code.
  *
@@ -2295 +2358 @@
 
 /**
+ * Adds a 8-bit signed jump offset to RIP from 64-bit code, no checking or
+ * clearing of flags.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ * @param   enmEffOpSize        Effective operand size.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS8AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
+                                                                          IEMMODE enmEffOpSize) RT_NOEXCEPT
+{
+    Assert(IEM_IS_64BIT_CODE(pVCpu));
+    Assert(enmEffOpSize == IEMMODE_64BIT || enmEffOpSize == IEMMODE_16BIT);
+
+    uint64_t uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
+    if (enmEffOpSize == IEMMODE_16BIT)
+        uNewRip &= UINT16_MAX;
+
+    if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
+        pVCpu->cpum.GstCtx.rip = uNewRip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
+ * Adds a 8-bit signed jump offset to EIP, on 386 or later from 16-bit or 32-bit
+ * code (never 64-bit), no checking or clearing of flags.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ * @param   enmEffOpSize        Effective operand size.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS8AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
+                                                                          IEMMODE enmEffOpSize) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+    Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
+
+    uint32_t uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + (int32_t)offNextInstr;
+    if (enmEffOpSize == IEMMODE_16BIT)
+        uNewEip &= UINT16_MAX;
+    if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewEip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
+ * Adds a 8-bit signed jump offset to IP, on a pre-386 CPU, no checking or
+ * clearing of flags.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegIp16RelativeJumpS8AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                         int8_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+
+    uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + (int16_t)offNextInstr;
+    if (RT_LIKELY(uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewIp;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
  * Adds a 16-bit signed jump offset to RIP from 64-bit code.
  *
@@ -2357 +2516 @@
 
 /**
+ * Adds a 16-bit signed jump offset to RIP from 64-bit code, no checking or
+ * clearing of flags.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS16AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                           int16_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(IEM_IS_64BIT_CODE(pVCpu));
+
+    pVCpu->cpum.GstCtx.rip = (uint16_t)(pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
+ * Adds a 16-bit signed jump offset to EIP from 16-bit or 32-bit code,
+ * no checking or clearing of flags.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ *
+ * @note    This is also used by 16-bit code in pre-386 mode, as the code is
+ *          identical.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS16AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                           int16_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+
+    uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr;
+    if (RT_LIKELY(uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewIp;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
  * Adds a 32-bit signed jump offset to RIP from 64-bit code.
  *
@@ -2428 +2643 @@
      */
     return iemRegFinishClearingRF(pVCpu);
+}
+
+
+/**
+ * Adds a 32-bit signed jump offset to RIP from 64-bit code, no checking or
+ * clearing of flags.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * We ASSUME that the effective operand size is 64-bit here, as 16-bit is the
+ * only alternative for relative jumps in 64-bit code and that is already
+ * handled in the decoder stage.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS32AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                           int32_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(IEM_IS_64BIT_CODE(pVCpu));
+
+    uint64_t const uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
+    if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
+        pVCpu->cpum.GstCtx.rip = uNewRip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
+}
+
+
+/**
+ * Adds a 32-bit signed jump offset to RIP from 64-bit code, no checking or
+ * clearing of flags.
+ *
+ * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
+ * segment limit.
+ *
+ * We ASSUME that the effective operand size is 32-bit here, as 16-bit is the
+ * only alternative for relative jumps in 32-bit code and that is already
+ * handled in the decoder stage.
+ *
+ * @returns Strict VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   cbInstr             Instruction size.
+ * @param   offNextInstr        The offset of the next instruction.
+ */
+DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS32AndFinishNoFlags(PVMCPUCC pVCpu, uint8_t cbInstr,
+                                                                           int32_t offNextInstr) RT_NOEXCEPT
+{
+    Assert(!IEM_IS_64BIT_CODE(pVCpu));
+    Assert(pVCpu->cpum.GstCtx.rip <= UINT32_MAX);
+
+    uint32_t const uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + offNextInstr;
+    if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
+        pVCpu->cpum.GstCtx.rip = uNewEip;
+    else
+        return iemRaiseGeneralProtectionFault0(pVCpu);
+
+#ifndef IEM_WITH_CODE_TLB
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#endif
+    return iemRegFinishNoFlags(pVCpu);
 }
 

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -1427 +1427 @@
     /** The virtual sync time at the last timer poll call. */
     uint32_t                msRecompilerPollNow;
+    /** The IEM_CIMPL_F_XXX mask for the current instruction. */
+    uint32_t                fTbCurInstr;
+    /** The IEM_CIMPL_F_XXX mask for the previous instruction. */
+    uint32_t                fTbPrevInstr;
     /** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set.   */
     RTGCPHYS                GCPhysInstrBufPrev;
@@ -1443 +1447 @@
     R3PTRTYPE(struct IEMRECOMPILERSTATE *)  pNativeRecompilerStateR3;
     /** Alignment padding. */
-    uint64_t                auAlignment10[5];
+    uint64_t                auAlignment10[4];
     /** Statistics: Times TB execution was broken off before reaching the end. */
     STAMCOUNTER             StatTbExecBreaks;

trunk/src/VBox/VMM/include/IEMMc.h

@@ -41 +41 @@
  */
 
-#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fFlags)      {
-#define IEM_MC_END()                                    }
+#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) {
+#define IEM_MC_END()                                                }
 
 /** Internal macro. */
@@ -2003 +2003 @@
 /** May change significant portions of RFLAGS. */
 #define IEM_CIMPL_F_RFLAGS              RT_BIT_32(6)
-/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS . */
+/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
 #define IEM_CIMPL_F_STATUS_FLAGS        RT_BIT_32(7)
+/** May trigger interrupt shadowing. */
+#define IEM_CIMPL_F_INHIBIT_SHADOW      RT_BIT_32(8)
 /** May enable interrupts, so recheck IRQ immediately afterwards executing
  *  the instruction. */
-#define IEM_CIMPL_F_CHECK_IRQ_AFTER     RT_BIT_32(8)
+#define IEM_CIMPL_F_CHECK_IRQ_AFTER     RT_BIT_32(9)
 /** May disable interrupts, so recheck IRQ immediately before executing the
  *  instruction. */
-#define IEM_CIMPL_F_CHECK_IRQ_BEFORE    RT_BIT_32(9)
+#define IEM_CIMPL_F_CHECK_IRQ_BEFORE    RT_BIT_32(10)
 /** Convenience: Check for IRQ both before and after an instruction. */
 #define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE | IEM_CIMPL_F_CHECK_IRQ_AFTER)
 /** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
-#define IEM_CIMPL_F_VMEXIT              RT_BIT_32(10)
+#define IEM_CIMPL_F_VMEXIT              RT_BIT_32(11)
 /** May modify FPU state.
  * @todo Not sure if this is useful yet.  */
-#define IEM_CIMPL_F_FPU                 RT_BIT_32(11)
+#define IEM_CIMPL_F_FPU                 RT_BIT_32(12)
 /** REP prefixed instruction which may yield before updating PC.
  * @todo Not sure if this is useful, REP functions now return non-zero
  *       status if they don't update the PC. */
-#define IEM_CIMPL_F_REP                 RT_BIT_32(12)
+#define IEM_CIMPL_F_REP                 RT_BIT_32(13)
 /** I/O instruction.
  * @todo Not sure if this is useful yet.  */
-#define IEM_CIMPL_F_IO                  RT_BIT_32(13)
+#define IEM_CIMPL_F_IO                  RT_BIT_32(14)
 /** Force end of TB after the instruction. */
-#define IEM_CIMPL_F_END_TB              RT_BIT_32(14)
+#define IEM_CIMPL_F_END_TB              RT_BIT_32(15)
 /** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
 #define IEM_CIMPL_F_XCPT \

trunk/src/VBox/VMM/include/IEMN8veRecompiler.h

@@ -257 +257 @@
     /** Buffer used by the recompiler for recording fixups when generating code. */
     PIEMNATIVEFIXUP             paFixups;
+
+    /** The translation block being recompiled. */
+    PCIEMTB                     pTbOrg;
 } IEMRECOMPILERSTATE;
 /** Pointer to a native recompiler state. */

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -558 +558 @@
 
 #define IEM_ARG_CHECK_CALLBACK(a_idx, a_User) int RT_CONCAT(iArgCheck_,a_idx); NOREF(RT_CONCAT(iArgCheck_,a_idx))
-#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fFlags) \
+#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) \
     { \
         const uint8_t  cArgs    = (a_cArgs); NOREF(cArgs); \
         const uint8_t  cLocals  = (a_cLocals); NOREF(cLocals); \
-        const uint32_t fMcBegin = (((a_cArgs) + (a_cLocals)) << 23) + (a_fFlags); \
+        const uint32_t fMcBegin = (((a_cArgs) + (a_cLocals)) << 23) + (a_fMcFlags) + (a_fCImplFlags); \
         IEM_REPEAT(a_cArgs, IEM_ARG_CHECK, 0); \