Changeset 101428 in vbox

Timestamp:

Oct 13, 2023 5:39:12 AM (15 months ago)

Author:

vboxsync

Message:

VMM/HM: Added logging for new SVM features.

Location:

trunk

Files:

• include/VBox/vmm/cpum-x86-amd64.h (modified) (1 diff)
• include/iprt/x86.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp (modified) (1 diff)
• src/VBox/VMM/VMMR3/HM.cpp (modified) (1 diff)

trunk/include/VBox/vmm/cpum-x86-amd64.h

@@ -985 +985 @@
     /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
     uint32_t        fSvmGmet : 1;
+    /** SVM: Supports AVIC in x2APIC mode. */
+    uint32_t        fSvmX2Avic : 1;
     /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
     uint32_t        fSvmSSSCheck : 1;
     /** SVM: Supports SPEC_CTRL virtualization. */
     uint32_t        fSvmSpecCtrl : 1;
+    /** SVM: Supports Read-Only Guest Page Table feature. */
+    uint32_t        fSvmRoGpt : 1;
     /** SVM: Supports HOST_MCE_OVERRIDE. */
     uint32_t        fSvmHostMceOverride : 1;
     /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
     uint32_t        fSvmTlbiCtl : 1;
+     /** SVM: Supports NMI virtualization. */
+    uint32_t        fSvmVNmi : 1;
+    /** SVM: Supports IBS virtualizaiton. */
+    uint32_t        fSvmIbsVirt : 1;
+    /** SVM: Supports Extended LVT AVIC access changes. */
+    uint32_t        fSvmExtLvtAvicAccessChg : 1;
+    /** SVM: Supports Guest VMCB address check. */
+    uint32_t        fSvmNstVirtVmcbAddrChk : 1;
+    /** SVM: Supports Bus Lock Threshold. */
+    uint32_t        fSvmBusLockThreshold : 1;
     /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
-    uint32_t        fSvmPadding0 : 14;
+    uint32_t        fSvmPadding0 : 7;
     /** SVM: Maximum supported ASID. */
     uint32_t        uSvmMaxAsid;

trunk/include/iprt/x86.h

@@ -884 +884 @@
 /** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
 #define X86_CPUID_SVM_FEATURE_EDX_GMET                      RT_BIT(17)
+/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
+ *  mode. */
+#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC                    RT_BIT(18)
 /** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
 #define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK                  RT_BIT(19)
 /** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
 #define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL                 RT_BIT(20)
+/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
+#define X86_CPUID_SVM_FEATURE_EDX_ROGPT                     RT_BIT(21)
 /** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
 #define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE         RT_BIT(23)
 /** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
 #define X86_CPUID_SVM_FEATURE_EDX_TLBICTL                   RT_BIT(24)
+/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
+#define X86_CPUID_SVM_FEATURE_EDX_VNMI                      RT_BIT(25)
+/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
+#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT                  RT_BIT(26)
+/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
+#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG   RT_BIT(27)
+/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
+#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK    RT_BIT(28)
+/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
+#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD        RT_BIT(29)
+
 /** @} */
 

trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp

@@ -1559 +1559 @@
                 pFeatures->fSvmVGif                 = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
                 pFeatures->fSvmGmet                 = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
+                pFeatures->fSvmX2Avic               = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_X2AVIC);
                 pFeatures->fSvmSSSCheck             = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SSSCHECK);
                 pFeatures->fSvmSpecCtrl             = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL);
+                pFeatures->fSvmRoGpt                = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_ROGPT);
                 pFeatures->fSvmHostMceOverride      = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE);
                 pFeatures->fSvmTlbiCtl              = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TLBICTL);
+                pFeatures->fSvmVNmi                 = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VNMI);
+                pFeatures->fSvmIbsVirt              = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT);
+                pFeatures->fSvmExtLvtAvicAccessChg  = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG);
+                pFeatures->fSvmNstVirtVmcbAddrChk   = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK);
+                pFeatures->fSvmBusLockThreshold     = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD);
                 pFeatures->uSvmMaxAsid              = pSvmLeaf->uEbx;
             }

trunk/src/VBox/VMM/VMMR3/HM.cpp

@@ -1901 +1901 @@
     {
 #define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
-        HMSVM_REPORT_FEATURE("NESTED_PAGING",          X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
-        HMSVM_REPORT_FEATURE("LBR_VIRT",               X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
-        HMSVM_REPORT_FEATURE("SVM_LOCK",               X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
-        HMSVM_REPORT_FEATURE("NRIP_SAVE",              X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
-        HMSVM_REPORT_FEATURE("TSC_RATE_MSR",           X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
-        HMSVM_REPORT_FEATURE("VMCB_CLEAN",             X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
-        HMSVM_REPORT_FEATURE("FLUSH_BY_ASID",          X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
-        HMSVM_REPORT_FEATURE("DECODE_ASSISTS",         X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
-        HMSVM_REPORT_FEATURE("PAUSE_FILTER",           X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
-        HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
-        HMSVM_REPORT_FEATURE("AVIC",                   X86_CPUID_SVM_FEATURE_EDX_AVIC),
-        HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD",     X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
-        HMSVM_REPORT_FEATURE("VGIF",                   X86_CPUID_SVM_FEATURE_EDX_VGIF),
-        HMSVM_REPORT_FEATURE("GMET",                   X86_CPUID_SVM_FEATURE_EDX_GMET),
-        HMSVM_REPORT_FEATURE("SSSCHECK",               X86_CPUID_SVM_FEATURE_EDX_SSSCHECK),
-        HMSVM_REPORT_FEATURE("SPEC_CTRL",              X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL),
-        HMSVM_REPORT_FEATURE("HOST_MCE_OVERRIDE",      X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE),
-        HMSVM_REPORT_FEATURE("TLBICTL",                X86_CPUID_SVM_FEATURE_EDX_TLBICTL),
+        HMSVM_REPORT_FEATURE("NESTED_PAGING",           X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
+        HMSVM_REPORT_FEATURE("LBR_VIRT",                X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
+        HMSVM_REPORT_FEATURE("SVM_LOCK",                X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
+        HMSVM_REPORT_FEATURE("NRIP_SAVE",               X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
+        HMSVM_REPORT_FEATURE("TSC_RATE_MSR",            X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
+        HMSVM_REPORT_FEATURE("VMCB_CLEAN",              X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
+        HMSVM_REPORT_FEATURE("FLUSH_BY_ASID",           X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
+        HMSVM_REPORT_FEATURE("DECODE_ASSISTS",          X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
+        HMSVM_REPORT_FEATURE("PAUSE_FILTER",            X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
+        HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD",  X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
+        HMSVM_REPORT_FEATURE("AVIC",                    X86_CPUID_SVM_FEATURE_EDX_AVIC),
+        HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD",      X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
+        HMSVM_REPORT_FEATURE("VGIF",                    X86_CPUID_SVM_FEATURE_EDX_VGIF),
+        HMSVM_REPORT_FEATURE("GMET",                    X86_CPUID_SVM_FEATURE_EDX_GMET),
+        HMSVM_REPORT_FEATURE("X2AVIC",                  X86_CPUID_SVM_FEATURE_EDX_X2AVIC),
+        HMSVM_REPORT_FEATURE("SSSCHECK",                X86_CPUID_SVM_FEATURE_EDX_SSSCHECK),
+        HMSVM_REPORT_FEATURE("SPEC_CTRL",               X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL),
+        HMSVM_REPORT_FEATURE("ROGPT",                   X86_CPUID_SVM_FEATURE_EDX_ROGPT),
+        HMSVM_REPORT_FEATURE("HOST_MCE_OVERRIDE",       X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE),
+        HMSVM_REPORT_FEATURE("TLBICTL",                 X86_CPUID_SVM_FEATURE_EDX_TLBICTL),
+        HMSVM_REPORT_FEATURE("VNMI",                    X86_CPUID_SVM_FEATURE_EDX_VNMI),
+        HMSVM_REPORT_FEATURE("IBS_VIRT",                X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT),
+        HMSVM_REPORT_FEATURE("EXT_LVT_AVIC_ACCESS_CHG", X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG),
+        HMSVM_REPORT_FEATURE("NST_VIRT_VMCB_ADDR_CHK",  X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK),
+        HMSVM_REPORT_FEATURE("BUS_LOCK_THRESHOLD",      X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD),
 #undef HMSVM_REPORT_FEATURE
     };