Changeset 101479 in vbox for trunk/src/VBox/Devices/Bus
- Timestamp:
- Oct 17, 2023 2:38:54 PM (19 months ago)
- svn:sync-xref-src-repo-rev:
- 159551
- Location:
- trunk/src/VBox/Devices/Bus
- Files:
-
- 3 edited
-
DevPciGenericEcam.cpp (modified) (5 diffs)
-
DevPciIch9.cpp (modified) (9 diffs)
-
DevPciInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPciGenericEcam.cpp
r100766 r101479 99 99 100 100 101 /** 102 * @interface_method_impl{PDMPCIBUSREGCC,pfnSetIrqR3} 103 */ 104 static DECLCALLBACK(void) pciGenEcamSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 105 { 106 PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT); 101 static void pciGenEcamSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC, 102 uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 103 { 107 104 PDEVPCIBUS pBus = &pPciRoot->PciBus; 108 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);109 uint8_t uDevFn = pPciDev->uDevFn;110 105 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn); 111 112 LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));113 106 114 107 /* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command … … 164 157 } 165 158 } 159 } 160 161 162 /** 163 * @interface_method_impl{PDMPCIBUSREGCC,pfnSetIrqR3} 164 */ 165 static DECLCALLBACK(void) pciGenEcamSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 166 { 167 LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc)); 168 pciGenEcamSetIrqInternal(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC), 169 pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc); 170 } 171 172 173 static DECLCALLBACK(void) pciGenEcamBridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 174 { 175 /* 176 * The PCI-to-PCI bridge specification defines how the interrupt pins 177 * are routed from the secondary to the primary bus (see chapter 9). 178 * iIrq gives the interrupt pin the pci device asserted. 179 * We change iIrq here according to the spec and call the SetIrq function 180 * of our parent passing the device which asserted the interrupt instead of the device of the bridge. 181 * 182 * See ich9pciBiosInitAllDevicesOnBus for corresponding configuration code. 183 */ 184 PDEVPCIBUS pBus; 185 uint8_t uDevFnBridge; 186 int iIrqPinBridge; 187 PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge); 188 AssertReturnVoid(pDevInsBus); 189 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus)); 190 Assert(pDevInsBus->pReg == &g_DevicePciGenericEcam); /* ASSUMPTION: Same style root bus. Need callback interface to mix types. */ 191 192 /* 193 * For MSI/MSI-X enabled devices the iIrq doesn't denote the pin but rather a vector which is completely 194 * orthogonal to the pin based approach. The vector is not subject to the pin based routing with PCI bridges. 195 */ 196 int iIrqPinVector = iIrqPinBridge; 197 if ( MsiIsEnabled(pPciDev) 198 || MsixIsEnabled(pPciDev)) 199 iIrqPinVector = iIrq; 200 pciGenEcamSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC), 201 uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc); 166 202 } 167 203 … … 428 464 } 429 465 466 467 /** 468 * @interface_method_impl{PDMIBASE,pfnQueryInterface} 469 */ 470 static DECLCALLBACK(void *) pciGenEcamBridgeQueryInterface(PPDMIBASE pInterface, const char *pszIID) 471 { 472 PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase); 473 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase); 474 475 /* HACK ALERT! Special access to the PDMPCIDEV structure of an ich9pcibridge 476 instance (see PDMIICH9BRIDGEPDMPCIDEV_IID for details). */ 477 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIICH9BRIDGEPDMPCIDEV, pDevIns->apPciDevs[0]); 478 return NULL; 479 } 480 481 482 /** 483 * @interface_method_impl{PDMDEVREG,pfnDestruct} 484 */ 485 static DECLCALLBACK(int) pciGenEcamBridgeR3Destruct(PPDMDEVINS pDevIns) 486 { 487 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); 488 if (pBus->papBridgesR3) 489 { 490 PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3); 491 pBus->papBridgesR3 = NULL; 492 } 493 return VINF_SUCCESS; 494 } 495 496 497 /** 498 * @interface_method_impl{PDMDEVREG,pfnConstruct} 499 */ 500 static DECLCALLBACK(int) pciGenEcamBridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 501 { 502 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 503 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 504 505 /* 506 * Validate and read configuration. 507 */ 508 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "ExpressEnabled|ExpressPortType", ""); 509 510 /* check if we're supposed to implement a PCIe bridge. */ 511 bool fExpress; 512 int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false); 513 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ExpressEnabled\""))); 514 515 char szExpressPortType[80]; 516 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ExpressPortType", szExpressPortType, sizeof(szExpressPortType), "RootCmplxIntEp"); 517 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read \"ExpressPortType\" as string"))); 518 519 uint8_t const uExpressPortType = devpciR3BridgeCommonGetExpressPortTypeFromString(szExpressPortType); 520 Log(("PCI/bridge#%u: fR0Enabled=%RTbool fRCEnabled=%RTbool fExpress=%RTbool uExpressPortType=%u (%s)\n", 521 iInstance, pDevIns->fR0Enabled, pDevIns->fRCEnabled, fExpress, uExpressPortType, szExpressPortType)); 522 523 /* 524 * Init data and register the PCI bus. 525 */ 526 pDevIns->IBase.pfnQueryInterface = pciGenEcamBridgeQueryInterface; 527 528 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC); 529 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); 530 531 pBus->enmType = DEVPCIBUSTYPE_ICH9; 532 pBus->fPureBridge = true; 533 pBusCC->pDevInsR3 = pDevIns; 534 pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices)); 535 AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY); 536 537 PDMPCIBUSREGCC PciBusReg; 538 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION; 539 PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice; 540 PciBusReg.pfnRegisterMsiR3 = NULL; 541 PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister; 542 PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses; 543 PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite; 544 PciBusReg.pfnConfigRead = devpciR3CommonConfigRead; 545 PciBusReg.pfnSetIrqR3 = pciGenEcamBridgeSetIrq; 546 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION; 547 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus); 548 if (RT_FAILURE(rc)) 549 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus")); 550 Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */ 551 if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION) 552 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS, 553 N_("PCI helper version mismatch; got %#x expected %#x"), 554 pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION); 555 556 LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus)); 557 558 559 /* Disable default device locking. */ 560 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns)); 561 AssertRCReturn(rc, rc); 562 563 /** @todo r=aeichner This is the same as the ICH9 bridge. */ 564 /* 565 * Fill in PCI configs and add them to the bus. 566 */ 567 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; 568 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); 569 570 PDMPciDevSetVendorId( pPciDev, 0x8086); /* Intel */ 571 if (fExpress) 572 { 573 PDMPciDevSetDeviceId(pPciDev, 0x29e1); /* 82X38/X48 Express Host-Primary PCI Express Bridge. */ 574 PDMPciDevSetRevisionId(pPciDev, 0x01); 575 } 576 else 577 { 578 PDMPciDevSetDeviceId(pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */ 579 PDMPciDevSetRevisionId(pPciDev, 0xf2); 580 } 581 PDMPciDevSetClassSub( pPciDev, 0x04); /* pci2pci */ 582 PDMPciDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */ 583 if (fExpress) 584 PDMPciDevSetClassProg(pPciDev, 0x00); /* Normal decoding. */ 585 else 586 PDMPciDevSetClassProg(pPciDev, 0x01); /* Supports subtractive decoding. */ 587 PDMPciDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */ 588 if (fExpress) 589 { 590 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_SERR); 591 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Has capabilities. */ 592 PDMPciDevSetByte(pPciDev, VBOX_PCI_CACHE_LINE_SIZE, 8); /* 32 bytes */ 593 /* PCI Express */ 594 PDMPciDevSetByte(pPciDev, 0xa0 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */ 595 PDMPciDevSetByte(pPciDev, 0xa0 + 1, 0); /* next */ 596 PDMPciDevSetWord(pPciDev, 0xa0 + 2, 597 /* version */ 0x2 598 | (uExpressPortType << 4)); 599 PDMPciDevSetDWord(pPciDev, 0xa0 + 4, VBOX_PCI_EXP_DEVCAP_RBE); /* Device capabilities. */ 600 PDMPciDevSetWord(pPciDev, 0xa0 + 8, 0x0000); /* Device control. */ 601 PDMPciDevSetWord(pPciDev, 0xa0 + 10, 0x0000); /* Device status. */ 602 PDMPciDevSetDWord(pPciDev, 0xa0 + 12, 603 /* Max Link Speed */ 2 604 | /* Maximum Link Width */ (16 << 4) 605 | /* Active State Power Management (ASPM) Sopport */ (0 << 10) 606 | VBOX_PCI_EXP_LNKCAP_LBNC 607 | /* Port Number */ ((2 + iInstance) << 24)); /* Link capabilities. */ 608 PDMPciDevSetWord(pPciDev, 0xa0 + 16, VBOX_PCI_EXP_LNKCTL_CLOCK); /* Link control. */ 609 PDMPciDevSetWord(pPciDev, 0xa0 + 18, 610 /* Current Link Speed */ 2 611 | /* Negotiated Link Width */ (16 << 4) 612 | VBOX_PCI_EXP_LNKSTA_SL_CLK); /* Link status. */ 613 PDMPciDevSetDWord(pPciDev, 0xa0 + 20, 614 /* Slot Power Limit Value */ (75 << 7) 615 | /* Physical Slot Number */ (0 << 19)); /* Slot capabilities. */ 616 PDMPciDevSetWord(pPciDev, 0xa0 + 24, 0x0000); /* Slot control. */ 617 PDMPciDevSetWord(pPciDev, 0xa0 + 26, 0x0000); /* Slot status. */ 618 PDMPciDevSetWord(pPciDev, 0xa0 + 28, 0x0000); /* Root control. */ 619 PDMPciDevSetWord(pPciDev, 0xa0 + 30, 0x0000); /* Root capabilities. */ 620 PDMPciDevSetDWord(pPciDev, 0xa0 + 32, 0x00000000); /* Root status. */ 621 PDMPciDevSetDWord(pPciDev, 0xa0 + 36, 0x00000000); /* Device capabilities 2. */ 622 PDMPciDevSetWord(pPciDev, 0xa0 + 40, 0x0000); /* Device control 2. */ 623 PDMPciDevSetWord(pPciDev, 0xa0 + 42, 0x0000); /* Device status 2. */ 624 PDMPciDevSetDWord(pPciDev, 0xa0 + 44, 625 /* Supported Link Speeds Vector */ (2 << 1)); /* Link capabilities 2. */ 626 PDMPciDevSetWord(pPciDev, 0xa0 + 48, 627 /* Target Link Speed */ 2); /* Link control 2. */ 628 PDMPciDevSetWord(pPciDev, 0xa0 + 50, 0x0000); /* Link status 2. */ 629 PDMPciDevSetDWord(pPciDev, 0xa0 + 52, 0x00000000); /* Slot capabilities 2. */ 630 PDMPciDevSetWord(pPciDev, 0xa0 + 56, 0x0000); /* Slot control 2. */ 631 PDMPciDevSetWord(pPciDev, 0xa0 + 58, 0x0000); /* Slot status 2. */ 632 PDMPciDevSetCapabilityList(pPciDev, 0xa0); 633 } 634 else 635 { 636 PDMPciDevSetCommand(pPciDev, 0x00); 637 PDMPciDevSetStatus(pPciDev, 0x20); /* 66MHz Capable. */ 638 } 639 PDMPciDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */ 640 641 /* 642 * This device does not generate interrupts. Interrupt delivery from 643 * devices attached to the bus is unaffected. 644 */ 645 PDMPciDevSetInterruptPin (pPciDev, 0x00); 646 647 if (fExpress) 648 { 649 /** @todo r=klaus set up the PCIe config space beyond the old 256 byte 650 * limit, containing additional capability descriptors. */ 651 } 652 653 /* 654 * Register this PCI bridge. The called function will take care on which bus we will get registered. 655 */ 656 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, 657 PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pci-generic-ecam-bridge"); 658 AssertLogRelRCReturn(rc, rc); 659 660 pPciDev->Int.s.pfnBridgeConfigRead = devpciR3BridgeCommonConfigRead; 661 pPciDev->Int.s.pfnBridgeConfigWrite = devpciR3BridgeCommonConfigWrite; 662 663 /* 664 * Register SSM handlers. We use the same saved state version as for the host bridge 665 * to make changes easier. 666 */ 667 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCIGENECAM_SAVED_STATE_VERSION, 668 sizeof(*pBus) + 16*128, 669 "pgm" /* before */, 670 NULL, NULL, NULL, 671 NULL, devpciR3BridgeCommonSaveExec, NULL, 672 NULL, devpciR3BridgeCommonLoadExec, NULL); 673 AssertLogRelRCReturn(rc, rc); 674 675 return VINF_SUCCESS; 676 } 677 430 678 #else /* !IN_RING3 */ 431 679 … … 458 706 AssertLogRelRCReturn(rc, rc); 459 707 } 708 709 return rc; 710 } 711 712 713 /** 714 * @interface_method_impl{PDMDEVREGR0,pfnConstruct} 715 */ 716 static DECLCALLBACK(int) pciGenEcamBridgeRZConstruct(PPDMDEVINS pDevIns) 717 { 718 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 719 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); 720 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC); 721 722 /* Mirror the ring-3 device lock disabling: */ 723 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns)); 724 AssertRCReturn(rc, rc); 725 726 /* Set up the RZ PCI bus callbacks: */ 727 PDMPCIBUSREGCC PciBusReg; 728 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION; 729 PciBusReg.iBus = pBus->iBus; 730 PciBusReg.pfnSetIrq = pciGenEcamBridgeSetIrq; 731 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION; 732 rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp)); 733 AssertRCReturn(rc, rc); 460 734 461 735 return rc; … … 536 810 /* .u32VersionEnd = */ PDM_DEVREG_VERSION 537 811 }; 812 813 /** 814 * The device registration structure 815 * for the PCI-to-PCI bridge. 816 */ 817 const PDMDEVREG g_DevicePciGenericEcamBridge = 818 { 819 /* .u32Version = */ PDM_DEVREG_VERSION, 820 /* .uReserved0 = */ 0, 821 /* .szName = */ "pci-generic-ecam-bridge", 822 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE, 823 /* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI, 824 /* .cMaxInstances = */ ~0U, 825 /* .uSharedVersion = */ 42, 826 /* .cbInstanceShared = */ sizeof(DEVPCIBUS), 827 /* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)), 828 /* .cbInstanceRC = */ 0, 829 /* .cMaxPciDevices = */ 1, 830 /* .cMaxMsixVectors = */ 0, 831 /* .pszDescription = */ "Generic ECAM PCI to PCI bridge", 832 #if defined(IN_RING3) 833 /* .pszRCMod = */ "VBoxDDRC.rc", 834 /* .pszR0Mod = */ "VBoxDDR0.r0", 835 /* .pfnConstruct = */ pciGenEcamBridgeR3Construct, 836 /* .pfnDestruct = */ pciGenEcamBridgeR3Destruct, 837 /* .pfnRelocate = */ NULL, 838 /* .pfnMemSetup = */ NULL, 839 /* .pfnPowerOn = */ NULL, 840 /* .pfnReset = */ NULL, /* Must be NULL, to make sure only bus driver handles reset */ 841 /* .pfnSuspend = */ NULL, 842 /* .pfnResume = */ NULL, 843 /* .pfnAttach = */ NULL, 844 /* .pfnDetach = */ NULL, 845 /* .pfnQueryInterface = */ NULL, 846 /* .pfnInitComplete = */ NULL, 847 /* .pfnPowerOff = */ NULL, 848 /* .pfnSoftReset = */ NULL, 849 /* .pfnReserved0 = */ NULL, 850 /* .pfnReserved1 = */ NULL, 851 /* .pfnReserved2 = */ NULL, 852 /* .pfnReserved3 = */ NULL, 853 /* .pfnReserved4 = */ NULL, 854 /* .pfnReserved5 = */ NULL, 855 /* .pfnReserved6 = */ NULL, 856 /* .pfnReserved7 = */ NULL, 857 #elif defined(IN_RING0) 858 /* .pfnEarlyConstruct = */ NULL, 859 /* .pfnConstruct = */ pciGenEcamBridgeRZConstruct, 860 /* .pfnDestruct = */ NULL, 861 /* .pfnFinalDestruct = */ NULL, 862 /* .pfnRequest = */ NULL, 863 /* .pfnReserved0 = */ NULL, 864 /* .pfnReserved1 = */ NULL, 865 /* .pfnReserved2 = */ NULL, 866 /* .pfnReserved3 = */ NULL, 867 /* .pfnReserved4 = */ NULL, 868 /* .pfnReserved5 = */ NULL, 869 /* .pfnReserved6 = */ NULL, 870 /* .pfnReserved7 = */ NULL, 871 #elif defined(IN_RC) 872 /* .pfnConstruct = */ pciGenEcamBridgeRZConstruct, 873 /* .pfnReserved0 = */ NULL, 874 /* .pfnReserved1 = */ NULL, 875 /* .pfnReserved2 = */ NULL, 876 /* .pfnReserved3 = */ NULL, 877 /* .pfnReserved4 = */ NULL, 878 /* .pfnReserved5 = */ NULL, 879 /* .pfnReserved6 = */ NULL, 880 /* .pfnReserved7 = */ NULL, 881 #else 882 # error "Not in IN_RING3, IN_RING0 or IN_RC!" 883 #endif 884 /* .u32VersionEnd = */ PDM_DEVREG_VERSION 885 }; -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r100897 r101479 1182 1182 1183 1183 1184 static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)1184 DECL_HIDDEN_CALLBACK(int) devpciR3BridgeCommonSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 1185 1185 { 1186 1186 PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); … … 1194 1194 * @callback_method_impl{FNPCIBRIDGECONFIGWRITE} 1195 1195 */ 1196 static DECLCALLBACK(VBOXSTRICTRC) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,1197 uint32_t u32Address, unsigned cb, uint32_t u32Value)1196 DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) devpciR3BridgeCommonConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, 1197 uint32_t u32Address, unsigned cb, uint32_t u32Value) 1198 1198 { 1199 1199 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); … … 1234 1234 * @callback_method_impl{FNPCIBRIDGECONFIGREAD} 1235 1235 */ 1236 static DECLCALLBACK(VBOXSTRICTRC) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,1237 uint32_t u32Address, unsigned cb, uint32_t *pu32Value)1236 DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) devpciR3BridgeCommonConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, 1237 uint32_t u32Address, unsigned cb, uint32_t *pu32Value) 1238 1238 { 1239 1239 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); … … 1778 1778 } 1779 1779 1780 static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)1780 DECL_HIDDEN_CALLBACK(int) devpciR3BridgeCommonLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 1781 1781 { 1782 1782 PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); … … 3551 3551 * @param pszExpressPortType The string identifier for the port/device type. 3552 3552 */ 3553 static uint8_t ich9pcibridgeR3GetExpressPortTypeFromString(const char *pszExpressPortType)3553 DECLHIDDEN(uint8_t) devpciR3BridgeCommonGetExpressPortTypeFromString(const char *pszExpressPortType) 3554 3554 { 3555 3555 if (!RTStrCmp(pszExpressPortType, "EndPtDev")) … … 3674 3674 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read \"ExpressPortType\" as string"))); 3675 3675 3676 uint8_t const uExpressPortType = ich9pcibridgeR3GetExpressPortTypeFromString(szExpressPortType);3676 uint8_t const uExpressPortType = devpciR3BridgeCommonGetExpressPortTypeFromString(szExpressPortType); 3677 3677 Log(("PCI/bridge#%u: fR0Enabled=%RTbool fRCEnabled=%RTbool fExpress=%RTbool uExpressPortType=%u (%s)\n", 3678 3678 iInstance, pDevIns->fR0Enabled, pDevIns->fRCEnabled, fExpress, uExpressPortType, szExpressPortType)); … … 3814 3814 AssertLogRelRCReturn(rc, rc); 3815 3815 3816 pPciDev->Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;3817 pPciDev->Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;3816 pPciDev->Int.s.pfnBridgeConfigRead = devpciR3BridgeCommonConfigRead; 3817 pPciDev->Int.s.pfnBridgeConfigWrite = devpciR3BridgeCommonConfigWrite; 3818 3818 3819 3819 /* … … 3825 3825 "pgm" /* before */, 3826 3826 NULL, NULL, NULL, 3827 NULL, ich9pcibridgeR3SaveExec, NULL,3828 NULL, ich9pcibridgeR3LoadExec, NULL);3827 NULL, devpciR3BridgeCommonSaveExec, NULL, 3828 NULL, devpciR3BridgeCommonLoadExec, NULL); 3829 3829 AssertLogRelRCReturn(rc, rc); 3830 3830 … … 4047 4047 /* .u32VersionEnd = */ PDM_DEVREG_VERSION 4048 4048 }; 4049 -
trunk/src/VBox/Devices/Bus/DevPciInternal.h
r99820 r101479 294 294 DECL_HIDDEN_CALLBACK(int) devpciR3CommonLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass); 295 295 296 DECL_HIDDEN_CALLBACK(int) devpciR3BridgeCommonSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM); 297 DECL_HIDDEN_CALLBACK(int) devpciR3BridgeCommonLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass); 298 299 DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) devpciR3BridgeCommonConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, 300 uint32_t u32Address, unsigned cb, uint32_t u32Value); 301 DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) devpciR3BridgeCommonConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, 302 uint32_t u32Address, unsigned cb, uint32_t *pu32Value); 303 304 DECLHIDDEN(uint8_t) devpciR3BridgeCommonGetExpressPortTypeFromString(const char *pszExpressPortType); 305 296 306 297 307 DECLINLINE(uint8_t) devpciR3GetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
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