Changeset 101549 in vbox for trunk/src/VBox/VMM

Timestamp:

Oct 23, 2023 9:53:09 AM (14 months ago)

Author:

vboxsync

Message:

VMM/Armv8: Allow configuring the program counter reset value, bugref:10528

Location:

trunk/src/VBox/VMM

Files:

• VMMR3/CPUM-armv8.cpp (modified) (2 diffs)
• include/CPUMInternal-armv8.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp

@@ -363 +363 @@
     pVM->cpum.s.GuestInfo.paSysRegRangesR3 = &pVM->cpum.s.GuestInfo.aSysRegRanges[0];
 
+    PCFGMNODE   pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
+
+    /** @cfgm{/CPUM/ResetPcValue, string}
+     * Program counter value after a reset, sets the address of the first isntruction to execute. */
+    int rc = CFGMR3QueryU64Def(pCpumCfg, "ResetPcValue", &pVM->cpum.s.u64ResetPc, 0);
+    AssertLogRelRCReturn(rc, rc);
+
     /*
      * Register saved state data item.
      */
-    int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
-                                   NULL, cpumR3LiveExec, NULL,
-                                   NULL, cpumR3SaveExec, NULL,
-                                   cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
+    rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
+                               NULL, cpumR3LiveExec, NULL,
+                               NULL, cpumR3SaveExec, NULL,
+                               cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
     if (RT_FAILURE(rc))
         return rc;
@@ -467 +474 @@
                     | ARMV8_SPSR_EL2_AARCH64_I
                     | ARMV8_SPSR_EL2_AARCH64_F;
+
+    pCtx->Pc.u64 = pVM->cpum.s.u64ResetPc;
     /** @todo */
 }

trunk/src/VBox/VMM/include/CPUMInternal-armv8.h

@@ -107 +107 @@
     uint8_t                 abPadding0[6];
 
+    /** The reset value of the program counter. */
+    uint64_t                u64ResetPc;
+
     /** Align to 64-byte boundary. */
-    uint8_t                 abPadding1[56];
+    uint8_t                 abPadding1[48];
 
     /** Host CPU feature information.