Changeset 101802 in vbox

Timestamp:

Nov 5, 2023 3:17:44 AM (15 months ago)

Author:

vboxsync

Message:

VMM/IEM: Improved the tstIEMCheckMc to better ensure all promissed arguments are used in IEM_MC_CALL_XXXX macros. bugref:10371

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (10 diffs)
• VMMAll/IEMAllInstVexMap1.cpp.h (modified) (2 diffs)
• testcase/tstIEMCheckMc.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h

@@ -2693 +2693 @@
          * XMM128, XMM64.
          */
-        IEM_MC_BEGIN(1, 0, 0, 0);
+        IEM_MC_BEGIN(0, 1, 0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
-        IEM_MC_ARG(uint64_t,                    uSrc, 0);
+        IEM_MC_LOCAL(uint64_t,                  uSrc);
 
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
@@ -2712 +2712 @@
          * XMM128, [mem64].
          */
-        IEM_MC_BEGIN(1, 1, 0, 0);
+        IEM_MC_BEGIN(0, 2, 0, 0);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
-        IEM_MC_ARG(uint64_t,                    uSrc, 0);
+        IEM_MC_LOCAL(uint64_t,                  uSrc);
 
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
@@ -10022 +10022 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint64_t, u64Dst, 0);
+        IEM_MC_LOCAL(uint64_t, u64Dst);
         IEM_MC_FETCH_SREG_BASE_U64(u64Dst, X86_SREG_FS);
         IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Dst);
@@ -10033 +10033 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint32_t, u32Dst, 0);
+        IEM_MC_LOCAL(uint32_t, u32Dst);
         IEM_MC_FETCH_SREG_BASE_U32(u32Dst, X86_SREG_FS);
         IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Dst);
@@ -10051 +10051 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint64_t, u64Dst, 0);
+        IEM_MC_LOCAL(uint64_t, u64Dst);
         IEM_MC_FETCH_SREG_BASE_U64(u64Dst, X86_SREG_GS);
         IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Dst);
@@ -10062 +10062 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint32_t, u32Dst, 0);
+        IEM_MC_LOCAL(uint32_t, u32Dst);
         IEM_MC_FETCH_SREG_BASE_U32(u32Dst, X86_SREG_GS);
         IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Dst);
@@ -10080 +10080 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint64_t, u64Dst, 0);
+        IEM_MC_LOCAL(uint64_t, u64Dst);
         IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(u64Dst);
@@ -10092 +10092 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint32_t, u32Dst, 0);
+        IEM_MC_LOCAL(uint32_t, u32Dst);
         IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_STORE_SREG_BASE_U64(X86_SREG_FS, u32Dst);
@@ -10110 +10110 @@
     if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_64BIT, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint64_t, u64Dst, 0);
+        IEM_MC_LOCAL(uint64_t, u64Dst);
         IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(u64Dst);
@@ -10122 +10122 @@
     else
     {
-        IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
+        IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fFsGsBase);
         IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT();
-        IEM_MC_ARG(uint32_t, u32Dst, 0);
+        IEM_MC_LOCAL(uint32_t, u32Dst);
         IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_STORE_SREG_BASE_U64(X86_SREG_GS, u32Dst);

trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h

@@ -1217 +1217 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
-            IEM_MC_ARG(uint64_t,                    uSrc, 0);
+            IEM_MC_LOCAL(uint64_t,                  uSrc);
 
             IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
@@ -1255 +1255 @@
         if (pVCpu->iem.s.uVexLength == 0)
         {
-            IEM_MC_BEGIN(1, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
             IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
-            IEM_MC_ARG(uint64_t,                    uSrc, 0);
+            IEM_MC_LOCAL(uint64_t,                  uSrc);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -100 +100 @@
 
 #define CHK_CALL_ARG(a_Name, a_iArg) \
-    do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; } while (0)
+    do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; RT_NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); } while (0)
 
 
@@ -600 +600 @@
 #define IEM_MC_ARG(a_Type, a_Name, a_iArg) (void)fMcBegin; \
     RT_CONCAT(iArgCheck_,a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
-    int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
+    int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); \
     AssertCompile((a_iArg) < cArgs); \
     a_Type a_Name; \
@@ -606 +606 @@
 #define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) (void)fMcBegin; \
     RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
-    int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
+    int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); \
     AssertCompile((a_iArg) < cArgs); \
     a_Type const a_Name = (a_Value); \
@@ -615 +615 @@
 #define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) (void)fMcBegin; \
     RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
-    int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
+    int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); \
     AssertCompile((a_iArg) < cArgs); \
     a_Type const a_Name = &(a_Local); \
@@ -621 +621 @@
 #define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) (void)fMcBegin; \
     RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
-    int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_pName)); \
+    int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); \
     AssertCompile((a_iArg) < cArgs); \
     uint32_t a_Name; \
@@ -999 +999 @@
 #define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
     do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
-#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() do { IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0); (void)fMcBegin; } while (0)
+#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0); do { (void)fMcBegin; } while (0)
 #define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
-    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
+    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(pXState, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
 #define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
-    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
+    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(pXState, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
 #define IEM_MC_CALL_AVX_AIMPL_4(a_pfnAImpl, a1, a2, a3, a4) \
-    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; } while (0)
+    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(pXState, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; } while (0)
 
 #define IEM_MC_IF_EFL_BIT_SET(a_fBit)                                   (void)fMcBegin; if (g_fRandom) {