- Timestamp:
- Nov 8, 2023 3:56:18 PM (16 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 11 edited
-
VMMAll/IEMAllInstOneByte.cpp.h (modified) (99 diffs)
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VMMAll/IEMAllInstPython.py (modified) (4 diffs)
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VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (44 diffs)
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VMMAll/IEMAllN8veRecompiler.cpp (modified) (5 diffs)
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VMMAll/IEMAllThrdFuncs.cpp (modified) (5 diffs)
-
VMMAll/IEMAllThrdPython.py (modified) (3 diffs)
-
VMMAll/IEMAllThrdTables.h (modified) (1 diff)
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include/IEMInternal.h (modified) (8 diffs)
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include/IEMMc.h (modified) (5 diffs)
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include/IEMN8veRecompiler.h (modified) (1 diff)
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testcase/tstIEMCheckMc.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r101958 r101984 835 835 IEMOP_HLP_NO_64BIT(); 836 836 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 837 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize); 837 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, 838 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 839 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_ES) 840 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_ES) 841 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_ES), 842 iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize); 838 843 } 839 844 … … 1004 1009 /** @todo eliminate END_TB here */ 1005 1010 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_END_TB, 1011 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 1012 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_CS), 1006 1013 iemCImpl_pop_Sreg, X86_SREG_CS, pVCpu->iem.s.enmEffOpSize); 1007 1014 } … … 1124 1131 IEMOP_HLP_NO_64BIT(); 1125 1132 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_INHIBIT_SHADOW, 1133 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 1134 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_SS) 1135 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_SS) 1136 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_SS), 1126 1137 iemCImpl_pop_Sreg, X86_SREG_SS, pVCpu->iem.s.enmEffOpSize); 1127 1138 } … … 1229 1240 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1230 1241 IEMOP_HLP_NO_64BIT(); 1231 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, iemCImpl_pop_Sreg, X86_SREG_DS, pVCpu->iem.s.enmEffOpSize); 1242 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE, 1243 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 1244 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_DS) 1245 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_DS) 1246 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_DS), 1247 iemCImpl_pop_Sreg, X86_SREG_DS, pVCpu->iem.s.enmEffOpSize); 1232 1248 } 1233 1249 … … 1357 1373 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1358 1374 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF); 1359 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_daa);1375 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_daa); 1360 1376 } 1361 1377 … … 1467 1483 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1468 1484 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF); 1469 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_das);1485 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_das); 1470 1486 } 1471 1487 … … 1628 1644 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF); 1629 1645 1630 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aaa);1646 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_aaa); 1631 1647 } 1632 1648 … … 1756 1772 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_OF); 1757 1773 1758 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aas);1774 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_aas); 1759 1775 } 1760 1776 … … 2505 2521 IEMOP_HLP_NO_64BIT(); 2506 2522 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT) 2507 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_pusha_16);2523 IEM_MC_DEFER_TO_CIMPL_0_RET(0, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP), iemCImpl_pusha_16); 2508 2524 Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_32BIT); 2509 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_pusha_32);2525 IEM_MC_DEFER_TO_CIMPL_0_RET(0, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP), iemCImpl_pusha_32); 2510 2526 } 2511 2527 … … 2522 2538 IEMOP_HLP_NO_64BIT(); 2523 2539 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT) 2524 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_popa_16); 2540 IEM_MC_DEFER_TO_CIMPL_0_RET(0, 2541 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 2542 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX) 2543 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX) 2544 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBX) 2545 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 2546 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBP) 2547 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 2548 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 2549 iemCImpl_popa_16); 2525 2550 Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_32BIT); 2526 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_popa_32); 2551 IEM_MC_DEFER_TO_CIMPL_0_RET(0, 2552 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 2553 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX) 2554 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX) 2555 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBX) 2556 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 2557 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBP) 2558 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 2559 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 2560 iemCImpl_popa_32); 2527 2561 } 2528 2562 IEMOP_MNEMONIC(mvex, "mvex"); … … 3284 3318 switch (pVCpu->iem.s.enmEffAddrMode) 3285 3319 { 3286 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3287 iemCImpl_rep_ins_op8_addr16, false); 3288 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3289 iemCImpl_rep_ins_op8_addr32, false); 3290 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3291 iemCImpl_rep_ins_op8_addr64, false); 3320 case IEMMODE_16BIT: 3321 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3322 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3323 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3324 iemCImpl_rep_ins_op8_addr16, false); 3325 case IEMMODE_32BIT: 3326 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3327 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3328 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3329 iemCImpl_rep_ins_op8_addr32, false); 3330 case IEMMODE_64BIT: 3331 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3332 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3333 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3334 iemCImpl_rep_ins_op8_addr64, false); 3292 3335 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3293 3336 } … … 3298 3341 switch (pVCpu->iem.s.enmEffAddrMode) 3299 3342 { 3300 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3301 iemCImpl_ins_op8_addr16, false); 3302 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3303 iemCImpl_ins_op8_addr32, false); 3304 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3305 iemCImpl_ins_op8_addr64, false); 3343 case IEMMODE_16BIT: 3344 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3345 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3346 iemCImpl_ins_op8_addr16, false); 3347 case IEMMODE_32BIT: 3348 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3349 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3350 iemCImpl_ins_op8_addr32, false); 3351 case IEMMODE_64BIT: 3352 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3353 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3354 iemCImpl_ins_op8_addr64, false); 3306 3355 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3307 3356 } … … 3327 3376 case IEMMODE_16BIT: 3328 3377 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3378 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3379 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3329 3380 iemCImpl_rep_ins_op16_addr16, false); 3330 3381 case IEMMODE_32BIT: 3331 3382 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3383 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3384 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3332 3385 iemCImpl_rep_ins_op16_addr32, false); 3333 3386 case IEMMODE_64BIT: 3334 3387 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3388 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3389 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3335 3390 iemCImpl_rep_ins_op16_addr64, false); 3336 3391 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3343 3398 case IEMMODE_16BIT: 3344 3399 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3400 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3401 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3345 3402 iemCImpl_rep_ins_op32_addr16, false); 3346 3403 case IEMMODE_32BIT: 3347 3404 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3405 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3406 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3348 3407 iemCImpl_rep_ins_op32_addr32, false); 3349 3408 case IEMMODE_64BIT: 3350 3409 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3410 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 3411 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3351 3412 iemCImpl_rep_ins_op32_addr64, false); 3352 3413 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3364 3425 switch (pVCpu->iem.s.enmEffAddrMode) 3365 3426 { 3366 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3367 iemCImpl_ins_op16_addr16, false); 3368 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3369 iemCImpl_ins_op16_addr32, false); 3370 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3371 iemCImpl_ins_op16_addr64, false); 3427 case IEMMODE_16BIT: 3428 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3429 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3430 iemCImpl_ins_op16_addr16, false); 3431 case IEMMODE_32BIT: 3432 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3433 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3434 iemCImpl_ins_op16_addr32, false); 3435 case IEMMODE_64BIT: 3436 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3437 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3438 iemCImpl_ins_op16_addr64, false); 3372 3439 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3373 3440 } … … 3377 3444 switch (pVCpu->iem.s.enmEffAddrMode) 3378 3445 { 3379 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3380 iemCImpl_ins_op32_addr16, false); 3381 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3382 iemCImpl_ins_op32_addr32, false); 3383 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3384 iemCImpl_ins_op32_addr64, false); 3446 case IEMMODE_16BIT: 3447 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3448 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3449 iemCImpl_ins_op32_addr16, false); 3450 case IEMMODE_32BIT: 3451 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3452 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3453 iemCImpl_ins_op32_addr32, false); 3454 case IEMMODE_64BIT: 3455 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3456 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI), 3457 iemCImpl_ins_op32_addr64, false); 3385 3458 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 3386 3459 } … … 3406 3479 case IEMMODE_16BIT: 3407 3480 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3481 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3482 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3408 3483 iemCImpl_rep_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3409 3484 case IEMMODE_32BIT: 3410 3485 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3486 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3487 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3411 3488 iemCImpl_rep_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3412 3489 case IEMMODE_64BIT: 3413 3490 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3491 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3492 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3414 3493 iemCImpl_rep_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3415 3494 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3423 3502 case IEMMODE_16BIT: 3424 3503 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3504 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3425 3505 iemCImpl_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false); 3426 3506 case IEMMODE_32BIT: 3427 3507 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3508 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3428 3509 iemCImpl_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false); 3429 3510 case IEMMODE_64BIT: 3430 3511 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3512 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3431 3513 iemCImpl_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false); 3432 3514 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3453 3535 case IEMMODE_16BIT: 3454 3536 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3537 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3538 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3455 3539 iemCImpl_rep_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3456 3540 case IEMMODE_32BIT: 3457 3541 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3542 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3543 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3458 3544 iemCImpl_rep_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3459 3545 case IEMMODE_64BIT: 3460 3546 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3547 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3548 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3461 3549 iemCImpl_rep_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3462 3550 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3469 3557 case IEMMODE_16BIT: 3470 3558 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3559 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3560 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3471 3561 iemCImpl_rep_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3472 3562 case IEMMODE_32BIT: 3473 3563 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3564 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3565 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3474 3566 iemCImpl_rep_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3475 3567 case IEMMODE_64BIT: 3476 3568 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3569 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 3570 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 3477 3571 iemCImpl_rep_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3478 3572 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3492 3586 case IEMMODE_16BIT: 3493 3587 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3588 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3494 3589 iemCImpl_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false); 3495 3590 case IEMMODE_32BIT: 3496 3591 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3592 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3497 3593 iemCImpl_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false); 3498 3594 case IEMMODE_64BIT: 3499 3595 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3596 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3500 3597 iemCImpl_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false); 3501 3598 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 3508 3605 case IEMMODE_16BIT: 3509 3606 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3607 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3510 3608 iemCImpl_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false); 3511 3609 case IEMMODE_32BIT: 3512 3610 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3611 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3513 3612 iemCImpl_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false); 3514 3613 case IEMMODE_64BIT: 3515 3614 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 3615 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI), 3516 3616 iemCImpl_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false); 3517 3617 IEM_NOT_REACHED_DEFAULT_CASE_RET(); … … 6138 6238 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 6139 6239 else if (pVCpu->iem.s.fExec & IEM_F_X86_CTX_VMX) 6140 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmx_pause);6240 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_vmx_pause); 6141 6241 #endif 6142 6242 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM 6143 6243 else if (pVCpu->iem.s.fExec & IEM_F_X86_CTX_SVM) 6144 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_svm_pause);6244 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_svm_pause); 6145 6245 #endif 6146 6246 } … … 6343 6443 uint16_t u16Sel; IEM_OPCODE_GET_NEXT_U16(&u16Sel); 6344 6444 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 6345 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_BRANCH_DIRECT | IEM_CIMPL_F_BRANCH_FAR 6346 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 6445 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_BRANCH_DIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK 6446 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, UINT64_MAX, 6347 6447 iemCImpl_callf, u16Sel, off32Seg, pVCpu->iem.s.enmEffOpSize); 6448 /** @todo make task-switches, ring-switches, ++ return non-zero status */ 6348 6449 } 6349 6450 … … 6370 6471 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 6371 6472 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 6372 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_pushf, pVCpu->iem.s.enmEffOpSize); 6473 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP), 6474 iemCImpl_pushf, pVCpu->iem.s.enmEffOpSize); 6373 6475 } 6374 6476 … … 6383 6485 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 6384 6486 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER, 6487 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP), 6385 6488 iemCImpl_popf, pVCpu->iem.s.enmEffOpSize); 6386 6489 } … … 6642 6745 switch (pVCpu->iem.s.enmEffAddrMode) 6643 6746 { 6644 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op8_addr16, pVCpu->iem.s.iEffSeg); 6645 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op8_addr32, pVCpu->iem.s.iEffSeg); 6646 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op8_addr64, pVCpu->iem.s.iEffSeg); 6747 case IEMMODE_16BIT: 6748 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6749 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6750 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6751 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6752 iemCImpl_rep_movs_op8_addr16, pVCpu->iem.s.iEffSeg); 6753 case IEMMODE_32BIT: 6754 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6755 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6756 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6757 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6758 iemCImpl_rep_movs_op8_addr32, pVCpu->iem.s.iEffSeg); 6759 case IEMMODE_64BIT: 6760 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6761 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6762 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6763 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6764 iemCImpl_rep_movs_op8_addr64, pVCpu->iem.s.iEffSeg); 6647 6765 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6648 6766 } … … 6681 6799 switch (pVCpu->iem.s.enmEffAddrMode) 6682 6800 { 6683 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op16_addr16, pVCpu->iem.s.iEffSeg); 6684 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op16_addr32, pVCpu->iem.s.iEffSeg); 6685 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op16_addr64, pVCpu->iem.s.iEffSeg); 6801 case IEMMODE_16BIT: 6802 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6803 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6804 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6805 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6806 iemCImpl_rep_movs_op16_addr16, pVCpu->iem.s.iEffSeg); 6807 case IEMMODE_32BIT: 6808 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6809 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6810 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6811 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6812 iemCImpl_rep_movs_op16_addr32, pVCpu->iem.s.iEffSeg); 6813 case IEMMODE_64BIT: 6814 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6815 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6816 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6817 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6818 iemCImpl_rep_movs_op16_addr64, pVCpu->iem.s.iEffSeg); 6686 6819 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6687 6820 } … … 6690 6823 switch (pVCpu->iem.s.enmEffAddrMode) 6691 6824 { 6692 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op32_addr16, pVCpu->iem.s.iEffSeg); 6693 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op32_addr32, pVCpu->iem.s.iEffSeg); 6694 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op32_addr64, pVCpu->iem.s.iEffSeg); 6825 case IEMMODE_16BIT: 6826 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6827 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6828 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6829 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6830 iemCImpl_rep_movs_op32_addr16, pVCpu->iem.s.iEffSeg); 6831 case IEMMODE_32BIT: 6832 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6833 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6834 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6835 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6836 iemCImpl_rep_movs_op32_addr32, pVCpu->iem.s.iEffSeg); 6837 case IEMMODE_64BIT: 6838 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6839 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6840 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6841 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6842 iemCImpl_rep_movs_op32_addr64, pVCpu->iem.s.iEffSeg); 6695 6843 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6696 6844 } … … 6699 6847 { 6700 6848 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_6); 6701 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op64_addr32, pVCpu->iem.s.iEffSeg); 6702 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_rep_movs_op64_addr64, pVCpu->iem.s.iEffSeg); 6849 case IEMMODE_32BIT: 6850 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6851 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6852 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6853 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6854 iemCImpl_rep_movs_op64_addr32, pVCpu->iem.s.iEffSeg); 6855 case IEMMODE_64BIT: 6856 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 6857 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6858 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6859 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6860 iemCImpl_rep_movs_op64_addr64, pVCpu->iem.s.iEffSeg); 6703 6861 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6704 6862 } … … 6792 6950 switch (pVCpu->iem.s.enmEffAddrMode) 6793 6951 { 6794 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op8_addr16, pVCpu->iem.s.iEffSeg); 6795 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op8_addr32, pVCpu->iem.s.iEffSeg); 6796 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op8_addr64, pVCpu->iem.s.iEffSeg); 6952 case IEMMODE_16BIT: 6953 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 6954 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6955 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6956 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6957 iemCImpl_repe_cmps_op8_addr16, pVCpu->iem.s.iEffSeg); 6958 case IEMMODE_32BIT: 6959 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 6960 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6961 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6962 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6963 iemCImpl_repe_cmps_op8_addr32, pVCpu->iem.s.iEffSeg); 6964 case IEMMODE_64BIT: 6965 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 6966 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6967 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6968 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6969 iemCImpl_repe_cmps_op8_addr64, pVCpu->iem.s.iEffSeg); 6797 6970 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6798 6971 } … … 6804 6977 switch (pVCpu->iem.s.enmEffAddrMode) 6805 6978 { 6806 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op8_addr16, pVCpu->iem.s.iEffSeg); 6807 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op8_addr32, pVCpu->iem.s.iEffSeg); 6808 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op8_addr64, pVCpu->iem.s.iEffSeg); 6979 case IEMMODE_16BIT: 6980 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 6981 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6982 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6983 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6984 iemCImpl_repne_cmps_op8_addr16, pVCpu->iem.s.iEffSeg); 6985 case IEMMODE_32BIT: 6986 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 6987 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6988 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6989 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6990 iemCImpl_repne_cmps_op8_addr32, pVCpu->iem.s.iEffSeg); 6991 case IEMMODE_64BIT: 6992 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 6993 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 6994 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 6995 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 6996 iemCImpl_repne_cmps_op8_addr64, pVCpu->iem.s.iEffSeg); 6809 6997 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6810 6998 } … … 6842 7030 switch (pVCpu->iem.s.enmEffAddrMode) 6843 7031 { 6844 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op16_addr16, pVCpu->iem.s.iEffSeg); 6845 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op16_addr32, pVCpu->iem.s.iEffSeg); 6846 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op16_addr64, pVCpu->iem.s.iEffSeg); 7032 case IEMMODE_16BIT: 7033 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7034 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7035 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7036 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7037 iemCImpl_repe_cmps_op16_addr16, pVCpu->iem.s.iEffSeg); 7038 case IEMMODE_32BIT: 7039 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7040 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7041 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7042 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7043 iemCImpl_repe_cmps_op16_addr32, pVCpu->iem.s.iEffSeg); 7044 case IEMMODE_64BIT: 7045 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7046 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7047 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7048 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7049 iemCImpl_repe_cmps_op16_addr64, pVCpu->iem.s.iEffSeg); 6847 7050 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6848 7051 } … … 6851 7054 switch (pVCpu->iem.s.enmEffAddrMode) 6852 7055 { 6853 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op32_addr16, pVCpu->iem.s.iEffSeg); 6854 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op32_addr32, pVCpu->iem.s.iEffSeg); 6855 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op32_addr64, pVCpu->iem.s.iEffSeg); 7056 case IEMMODE_16BIT: 7057 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7058 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7059 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7060 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7061 iemCImpl_repe_cmps_op32_addr16, pVCpu->iem.s.iEffSeg); 7062 case IEMMODE_32BIT: 7063 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7064 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7065 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7066 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7067 iemCImpl_repe_cmps_op32_addr32, pVCpu->iem.s.iEffSeg); 7068 case IEMMODE_64BIT: 7069 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7070 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7071 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7072 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7073 iemCImpl_repe_cmps_op32_addr64, pVCpu->iem.s.iEffSeg); 6856 7074 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6857 7075 } … … 6860 7078 { 6861 7079 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_4); 6862 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op64_addr32, pVCpu->iem.s.iEffSeg); 6863 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_cmps_op64_addr64, pVCpu->iem.s.iEffSeg); 7080 case IEMMODE_32BIT: 7081 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7082 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7083 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7084 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7085 iemCImpl_repe_cmps_op64_addr32, pVCpu->iem.s.iEffSeg); 7086 case IEMMODE_64BIT: 7087 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7088 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7089 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7090 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7091 iemCImpl_repe_cmps_op64_addr64, pVCpu->iem.s.iEffSeg); 6864 7092 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6865 7093 } … … 6877 7105 switch (pVCpu->iem.s.enmEffAddrMode) 6878 7106 { 6879 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op16_addr16, pVCpu->iem.s.iEffSeg); 6880 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op16_addr32, pVCpu->iem.s.iEffSeg); 6881 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op16_addr64, pVCpu->iem.s.iEffSeg); 7107 case IEMMODE_16BIT: 7108 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7109 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7110 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7111 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7112 iemCImpl_repne_cmps_op16_addr16, pVCpu->iem.s.iEffSeg); 7113 case IEMMODE_32BIT: 7114 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7115 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7116 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7117 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7118 iemCImpl_repne_cmps_op16_addr32, pVCpu->iem.s.iEffSeg); 7119 case IEMMODE_64BIT: 7120 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7121 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7122 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7123 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7124 iemCImpl_repne_cmps_op16_addr64, pVCpu->iem.s.iEffSeg); 6882 7125 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6883 7126 } … … 6886 7129 switch (pVCpu->iem.s.enmEffAddrMode) 6887 7130 { 6888 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op32_addr16, pVCpu->iem.s.iEffSeg); 6889 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op32_addr32, pVCpu->iem.s.iEffSeg); 6890 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op32_addr64, pVCpu->iem.s.iEffSeg); 7131 case IEMMODE_16BIT: 7132 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7133 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7134 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7135 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7136 iemCImpl_repne_cmps_op32_addr16, pVCpu->iem.s.iEffSeg); 7137 case IEMMODE_32BIT: 7138 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7139 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7140 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7141 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7142 iemCImpl_repne_cmps_op32_addr32, pVCpu->iem.s.iEffSeg); 7143 case IEMMODE_64BIT: 7144 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7145 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7146 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7147 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7148 iemCImpl_repne_cmps_op32_addr64, pVCpu->iem.s.iEffSeg); 6891 7149 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6892 7150 } … … 6895 7153 { 6896 7154 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_2); 6897 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op64_addr32, pVCpu->iem.s.iEffSeg); 6898 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_cmps_op64_addr64, pVCpu->iem.s.iEffSeg); 7155 case IEMMODE_32BIT: 7156 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7157 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7158 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7159 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7160 iemCImpl_repne_cmps_op64_addr32, pVCpu->iem.s.iEffSeg); 7161 case IEMMODE_64BIT: 7162 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7163 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7164 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7165 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7166 iemCImpl_repne_cmps_op64_addr64, pVCpu->iem.s.iEffSeg); 6899 7167 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6900 7168 } … … 6998 7266 switch (pVCpu->iem.s.enmEffAddrMode) 6999 7267 { 7000 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, iemCImpl_stos_al_m16); 7001 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, iemCImpl_stos_al_m32); 7002 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, iemCImpl_stos_al_m64); 7268 case IEMMODE_16BIT: 7269 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, 7270 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7271 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7272 iemCImpl_stos_al_m16); 7273 case IEMMODE_32BIT: 7274 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, 7275 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7276 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7277 iemCImpl_stos_al_m32); 7278 case IEMMODE_64BIT: 7279 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP, 7280 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7281 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7282 iemCImpl_stos_al_m64); 7003 7283 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7004 7284 } … … 7036 7316 switch (pVCpu->iem.s.enmEffAddrMode) 7037 7317 { 7038 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_ax_m16); 7039 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_ax_m32); 7040 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_ax_m64); 7318 case IEMMODE_16BIT: 7319 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7320 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7321 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7322 iemCImpl_stos_ax_m16); 7323 case IEMMODE_32BIT: 7324 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7325 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7326 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7327 iemCImpl_stos_ax_m32); 7328 case IEMMODE_64BIT: 7329 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7330 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7331 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7332 iemCImpl_stos_ax_m64); 7041 7333 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7042 7334 } … … 7045 7337 switch (pVCpu->iem.s.enmEffAddrMode) 7046 7338 { 7047 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_eax_m16); 7048 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_eax_m32); 7049 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_eax_m64); 7339 case IEMMODE_16BIT: 7340 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7341 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7342 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7343 iemCImpl_stos_eax_m16); 7344 case IEMMODE_32BIT: 7345 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7346 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7347 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7348 iemCImpl_stos_eax_m32); 7349 case IEMMODE_64BIT: 7350 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7351 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7352 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7353 iemCImpl_stos_eax_m64); 7050 7354 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7051 7355 } … … 7054 7358 { 7055 7359 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_9); 7056 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_rax_m32); 7057 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, iemCImpl_stos_rax_m64); 7360 case IEMMODE_32BIT: 7361 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7362 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7363 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7364 iemCImpl_stos_rax_m32); 7365 case IEMMODE_64BIT: 7366 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_REP, 7367 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDI) 7368 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7369 iemCImpl_stos_rax_m64); 7058 7370 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7059 7371 } … … 7135 7447 switch (pVCpu->iem.s.enmEffAddrMode) 7136 7448 { 7137 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_al_m16, pVCpu->iem.s.iEffSeg); 7138 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_al_m32, pVCpu->iem.s.iEffSeg); 7139 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_al_m64, pVCpu->iem.s.iEffSeg); 7449 case IEMMODE_16BIT: 7450 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7451 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7452 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7453 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7454 iemCImpl_lods_al_m16, pVCpu->iem.s.iEffSeg); 7455 case IEMMODE_32BIT: 7456 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7457 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7458 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7459 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7460 iemCImpl_lods_al_m32, pVCpu->iem.s.iEffSeg); 7461 case IEMMODE_64BIT: 7462 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7463 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7464 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7465 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7466 iemCImpl_lods_al_m64, pVCpu->iem.s.iEffSeg); 7140 7467 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7141 7468 } … … 7173 7500 switch (pVCpu->iem.s.enmEffAddrMode) 7174 7501 { 7175 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_ax_m16, pVCpu->iem.s.iEffSeg); 7176 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_ax_m32, pVCpu->iem.s.iEffSeg); 7177 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_ax_m64, pVCpu->iem.s.iEffSeg); 7502 case IEMMODE_16BIT: 7503 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7504 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7505 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7506 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7507 iemCImpl_lods_ax_m16, pVCpu->iem.s.iEffSeg); 7508 case IEMMODE_32BIT: 7509 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7510 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7511 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7512 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7513 iemCImpl_lods_ax_m32, pVCpu->iem.s.iEffSeg); 7514 case IEMMODE_64BIT: 7515 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7516 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7517 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7518 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7519 iemCImpl_lods_ax_m64, pVCpu->iem.s.iEffSeg); 7178 7520 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7179 7521 } … … 7182 7524 switch (pVCpu->iem.s.enmEffAddrMode) 7183 7525 { 7184 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_eax_m16, pVCpu->iem.s.iEffSeg); 7185 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_eax_m32, pVCpu->iem.s.iEffSeg); 7186 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_eax_m64, pVCpu->iem.s.iEffSeg); 7526 case IEMMODE_16BIT: 7527 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7528 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7529 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7530 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7531 iemCImpl_lods_eax_m16, pVCpu->iem.s.iEffSeg); 7532 case IEMMODE_32BIT: 7533 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7534 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7535 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7536 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7537 iemCImpl_lods_eax_m32, pVCpu->iem.s.iEffSeg); 7538 case IEMMODE_64BIT: 7539 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7540 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7541 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7542 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7543 iemCImpl_lods_eax_m64, pVCpu->iem.s.iEffSeg); 7187 7544 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7188 7545 } … … 7191 7548 { 7192 7549 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_7); 7193 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_rax_m32, pVCpu->iem.s.iEffSeg); 7194 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, iemCImpl_lods_rax_m64, pVCpu->iem.s.iEffSeg); 7550 case IEMMODE_32BIT: 7551 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7552 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7553 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7554 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7555 iemCImpl_lods_rax_m32, pVCpu->iem.s.iEffSeg); 7556 case IEMMODE_64BIT: 7557 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_REP, 7558 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 7559 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7560 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7561 iemCImpl_lods_rax_m64, pVCpu->iem.s.iEffSeg); 7195 7562 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7196 7563 } … … 7278 7645 switch (pVCpu->iem.s.enmEffAddrMode) 7279 7646 { 7280 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_al_m16); 7281 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_al_m32); 7282 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_al_m64); 7647 case IEMMODE_16BIT: 7648 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7649 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7650 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7651 iemCImpl_repe_scas_al_m16); 7652 case IEMMODE_32BIT: 7653 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7654 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7655 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7656 iemCImpl_repe_scas_al_m32); 7657 case IEMMODE_64BIT: 7658 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7659 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7660 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7661 iemCImpl_repe_scas_al_m64); 7283 7662 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7284 7663 } … … 7290 7669 switch (pVCpu->iem.s.enmEffAddrMode) 7291 7670 { 7292 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_al_m16); 7293 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_al_m32); 7294 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_al_m64); 7671 case IEMMODE_16BIT: 7672 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7673 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7674 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7675 iemCImpl_repne_scas_al_m16); 7676 case IEMMODE_32BIT: 7677 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7678 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7679 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7680 iemCImpl_repne_scas_al_m32); 7681 case IEMMODE_64BIT: 7682 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7683 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7684 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7685 iemCImpl_repne_scas_al_m64); 7295 7686 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7296 7687 } … … 7328 7719 switch (pVCpu->iem.s.enmEffAddrMode) 7329 7720 { 7330 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_ax_m16); 7331 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_ax_m32); 7332 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_ax_m64); 7721 case IEMMODE_16BIT: 7722 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7723 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7724 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7725 iemCImpl_repe_scas_ax_m16); 7726 case IEMMODE_32BIT: 7727 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7728 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7729 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7730 iemCImpl_repe_scas_ax_m32); 7731 case IEMMODE_64BIT: 7732 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7733 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7734 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7735 iemCImpl_repe_scas_ax_m64); 7333 7736 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7334 7737 } … … 7337 7740 switch (pVCpu->iem.s.enmEffAddrMode) 7338 7741 { 7339 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_eax_m16); 7340 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_eax_m32); 7341 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_eax_m64); 7742 case IEMMODE_16BIT: 7743 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7744 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7745 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7746 iemCImpl_repe_scas_eax_m16); 7747 case IEMMODE_32BIT: 7748 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7749 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7750 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7751 iemCImpl_repe_scas_eax_m32); 7752 case IEMMODE_64BIT: 7753 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7754 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7755 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7756 iemCImpl_repe_scas_eax_m64); 7342 7757 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7343 7758 } … … 7346 7761 { 7347 7762 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_6); /** @todo It's this wrong, we can do 16-bit addressing in 64-bit mode, but not 32-bit. right? */ 7348 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_rax_m32); 7349 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repe_scas_rax_m64); 7763 case IEMMODE_32BIT: 7764 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7765 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7766 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7767 iemCImpl_repe_scas_rax_m32); 7768 case IEMMODE_64BIT: 7769 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7770 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7771 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7772 iemCImpl_repe_scas_rax_m64); 7350 7773 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7351 7774 } … … 7362 7785 switch (pVCpu->iem.s.enmEffAddrMode) 7363 7786 { 7364 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_ax_m16); 7365 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_ax_m32); 7366 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_ax_m64); 7787 case IEMMODE_16BIT: 7788 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7789 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7790 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7791 iemCImpl_repne_scas_ax_m16); 7792 case IEMMODE_32BIT: 7793 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7794 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7795 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7796 iemCImpl_repne_scas_ax_m32); 7797 case IEMMODE_64BIT: 7798 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7799 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7800 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7801 iemCImpl_repne_scas_ax_m64); 7367 7802 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7368 7803 } … … 7371 7806 switch (pVCpu->iem.s.enmEffAddrMode) 7372 7807 { 7373 case IEMMODE_16BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_eax_m16); 7374 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_eax_m32); 7375 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_eax_m64); 7808 case IEMMODE_16BIT: 7809 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7810 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7811 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7812 iemCImpl_repne_scas_eax_m16); 7813 case IEMMODE_32BIT: 7814 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7815 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7816 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7817 iemCImpl_repne_scas_eax_m32); 7818 case IEMMODE_64BIT: 7819 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7820 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7821 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7822 iemCImpl_repne_scas_eax_m64); 7376 7823 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7377 7824 } … … 7380 7827 { 7381 7828 case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_5); 7382 case IEMMODE_32BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_rax_m32); 7383 case IEMMODE_64BIT: IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_repne_scas_rax_m64); 7829 case IEMMODE_32BIT: 7830 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7831 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7832 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7833 iemCImpl_repne_scas_rax_m32); 7834 case IEMMODE_64BIT: 7835 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_REP | IEM_CIMPL_F_STATUS_FLAGS, 7836 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSI) 7837 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 7838 iemCImpl_repne_scas_rax_m64); 7384 7839 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7385 7840 } … … 7869 8324 { 7870 8325 case IEMMODE_16BIT: 7871 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_retn_iw_16, u16Imm);8326 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, 0, iemCImpl_retn_iw_16, u16Imm); 7872 8327 case IEMMODE_32BIT: 7873 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_retn_iw_32, u16Imm);8328 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, 0, iemCImpl_retn_iw_32, u16Imm); 7874 8329 case IEMMODE_64BIT: 7875 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_retn_iw_64, u16Imm);8330 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, 0, iemCImpl_retn_iw_64, u16Imm); 7876 8331 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7877 8332 } … … 7890 8345 { 7891 8346 case IEMMODE_16BIT: 7892 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_retn_16);8347 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, 0, iemCImpl_retn_16); 7893 8348 case IEMMODE_32BIT: 7894 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_retn_32);8349 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, 0, iemCImpl_retn_32); 7895 8350 case IEMMODE_64BIT: 7896 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_retn_64);8351 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, 0, iemCImpl_retn_64); 7897 8352 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 7898 8353 } … … 8153 8608 uint8_t u8NestingLevel; IEM_OPCODE_GET_NEXT_U8(&u8NestingLevel); 8154 8609 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8155 IEM_MC_DEFER_TO_CIMPL_3_RET(0, iemCImpl_enter, pVCpu->iem.s.enmEffOpSize, cbFrame, u8NestingLevel); 8610 IEM_MC_DEFER_TO_CIMPL_3_RET(0, 8611 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 8612 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBP), 8613 iemCImpl_enter, pVCpu->iem.s.enmEffOpSize, cbFrame, u8NestingLevel); 8156 8614 } 8157 8615 … … 8166 8624 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 8167 8625 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8168 IEM_MC_DEFER_TO_CIMPL_1_RET(0, iemCImpl_leave, pVCpu->iem.s.enmEffOpSize); 8626 IEM_MC_DEFER_TO_CIMPL_1_RET(0, 8627 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 8628 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBP), 8629 iemCImpl_leave, pVCpu->iem.s.enmEffOpSize); 8169 8630 } 8170 8631 … … 8178 8639 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); 8179 8640 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8180 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_MODE, 8641 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK 8642 | IEM_CIMPL_F_MODE, 8643 RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_DS) 8644 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_ES) 8645 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_FS) 8646 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_GS) 8647 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_DS) 8648 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_ES) 8649 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_FS) 8650 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_GS) 8651 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_DS) 8652 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_ES) 8653 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_FS) 8654 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_GS), 8181 8655 iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, u16Imm); 8182 8656 } … … 8190 8664 IEMOP_MNEMONIC(retf, "retf"); 8191 8665 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8192 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_MODE, 8666 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK 8667 | IEM_CIMPL_F_MODE, 8668 RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_DS) 8669 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_ES) 8670 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_FS) 8671 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_GS) 8672 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_DS) 8673 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_ES) 8674 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_FS) 8675 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_GS) 8676 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_DS) 8677 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_ES) 8678 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_FS) 8679 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_GS), 8193 8680 iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, 0); 8194 8681 } … … 8202 8689 IEMOP_MNEMONIC(int3, "int3"); 8203 8690 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8204 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 8205 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS ,8691 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 8692 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 0, 8206 8693 iemCImpl_int, X86_XCPT_BP, IEMINT_INT3); 8207 8694 } … … 8216 8703 uint8_t u8Int; IEM_OPCODE_GET_NEXT_U8(&u8Int); 8217 8704 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8218 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 8219 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 8705 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 8706 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, UINT64_MAX, 8220 8707 iemCImpl_int, u8Int, IEMINT_INTN); 8708 /** @todo make task-switches, ring-switches, ++ return non-zero status */ 8221 8709 } 8222 8710 … … 8229 8717 IEMOP_MNEMONIC(into, "into"); 8230 8718 IEMOP_HLP_NO_64BIT(); 8231 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_CONDITIONAL 8232 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 8719 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 8720 | IEM_CIMPL_F_BRANCH_CONDITIONAL | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS, 8721 UINT64_MAX, 8233 8722 iemCImpl_int, X86_XCPT_OF, IEMINT_INTO); 8723 /** @todo make task-switches, ring-switches, ++ return non-zero status */ 8234 8724 } 8235 8725 … … 8242 8732 IEMOP_MNEMONIC(iret, "iret"); 8243 8733 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8244 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 8734 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 8245 8735 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_CHECK_IRQ_BEFORE | IEM_CIMPL_F_VMEXIT, 8736 RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_DS) 8737 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_DS) 8738 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_DS) 8739 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_ES) 8740 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_ES) 8741 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_ES) 8742 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_FS) 8743 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_FS) 8744 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_FS) 8745 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_GS) 8746 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_GS) 8747 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_GS), 8246 8748 iemCImpl_iret, pVCpu->iem.s.enmEffOpSize); 8749 /* Segment registers are sanitized when returning to an outer ring, or fully 8750 reloaded when returning to v86 mode. Thus the large flush list above. */ 8247 8751 } 8248 8752 … … 8665 9169 if (!bImm) 8666 9170 IEMOP_RAISE_DIVIDE_ERROR_RET(); 8667 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aam, bImm);9171 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_aam, bImm); 8668 9172 } 8669 9173 … … 8678 9182 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8679 9183 IEMOP_HLP_NO_64BIT(); 8680 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_STATUS_FLAGS, iemCImpl_aad, bImm);9184 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_aad, bImm); 8681 9185 } 8682 9186 … … 10571 11075 IEMOP_MNEMONIC(fninit, "fninit"); 10572 11076 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 10573 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, iemCImpl_finit, false /*fCheckXcpts*/);11077 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, 0, iemCImpl_finit, false /*fCheckXcpts*/); 10574 11078 } 10575 11079 … … 10608 11112 { 10609 11113 IEMOP_MNEMONIC(fucomi_st0_stN, "fucomi st0,stN"); 10610 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 11114 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 0, 10611 11115 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), true /*fUCmp*/, 10612 11116 0 /*fPop*/ | pVCpu->iem.s.uFpuOpcode); … … 10618 11122 { 10619 11123 IEMOP_MNEMONIC(fcomi_st0_stN, "fcomi st0,stN"); 10620 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 11124 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 0, 10621 11125 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), false /*fUCmp*/, 10622 11126 false /*fPop*/ | pVCpu->iem.s.uFpuOpcode); … … 11539 12043 { 11540 12044 IEMOP_MNEMONIC(fucomip_st0_stN, "fucomip st0,stN"); 11541 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 12045 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 0, 11542 12046 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), false /*fUCmp*/, 11543 12047 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); … … 11549 12053 { 11550 12054 IEMOP_MNEMONIC(fcomip_st0_stN, "fcomip st0,stN"); 11551 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 12055 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_FPU | IEM_CIMPL_F_STATUS_FLAGS, 0, 11552 12056 iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), false /*fUCmp*/, 11553 12057 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); … … 12119 12623 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 12120 12624 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12121 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12625 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), 12122 12626 iemCImpl_in, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 12123 12627 } … … 12130 12634 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 12131 12635 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12132 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12636 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), 12133 12637 iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 12134 12638 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); … … 12142 12646 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 12143 12647 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12144 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12648 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 0, 12145 12649 iemCImpl_out, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 12146 12650 } … … 12153 12657 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 12154 12658 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12155 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12659 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 0, 12156 12660 iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 12157 12661 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); … … 12171 12675 { 12172 12676 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); 12173 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_RELATIVE, iemCImpl_call_rel_16, (int16_t)u16Imm); 12677 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_RELATIVE | IEM_CIMPL_F_BRANCH_STACK, 0, 12678 iemCImpl_call_rel_16, (int16_t)u16Imm); 12174 12679 } 12175 12680 … … 12177 12682 { 12178 12683 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); 12179 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_RELATIVE, iemCImpl_call_rel_32, (int32_t)u32Imm); 12684 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_RELATIVE | IEM_CIMPL_F_BRANCH_STACK, 0, 12685 iemCImpl_call_rel_32, (int32_t)u32Imm); 12180 12686 } 12181 12687 … … 12183 12689 { 12184 12690 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); 12185 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_RELATIVE, iemCImpl_call_rel_64, u64Imm); 12691 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_RELATIVE | IEM_CIMPL_F_BRANCH_STACK, 0, 12692 iemCImpl_call_rel_64, u64Imm); 12186 12693 } 12187 12694 … … 12239 12746 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12240 12747 IEM_MC_DEFER_TO_CIMPL_3_RET(IEM_CIMPL_F_BRANCH_DIRECT | IEM_CIMPL_F_BRANCH_FAR 12241 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, 12748 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, UINT64_MAX, 12242 12749 iemCImpl_FarJmp, u16Sel, off32Seg, pVCpu->iem.s.enmEffOpSize); 12750 /** @todo make task-switches, ring-switches, ++ return non-zero status */ 12243 12751 } 12244 12752 … … 12266 12774 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12267 12775 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12776 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), 12268 12777 iemCImpl_in_eAX_DX, 1, pVCpu->iem.s.enmEffAddrMode); 12269 12778 } … … 12276 12785 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12277 12786 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12787 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), 12278 12788 iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 12279 12789 pVCpu->iem.s.enmEffAddrMode); … … 12286 12796 IEMOP_MNEMONIC(out_DX_AL, "out DX,AL"); 12287 12797 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12288 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12798 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 0, 12289 12799 iemCImpl_out_DX_eAX, 1, pVCpu->iem.s.enmEffAddrMode); 12290 12800 } … … 12296 12806 IEMOP_MNEMONIC(out_DX_eAX, "out DX,eAX"); 12297 12807 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12298 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 12808 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_IO, 0, 12299 12809 iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 12300 12810 pVCpu->iem.s.enmEffAddrMode); … … 12327 12837 IEMOP_HLP_MIN_386(); 12328 12838 /** @todo testcase! */ 12329 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 12330 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS ,12839 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 12840 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 0, 12331 12841 iemCImpl_int, X86_XCPT_DB, IEMINT_INT1); 12332 12842 } … … 12378 12888 IEMOP_MNEMONIC(hlt, "hlt"); 12379 12889 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12380 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_END_TB | IEM_CIMPL_F_VMEXIT, iemCImpl_hlt);12890 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_END_TB | IEM_CIMPL_F_VMEXIT, 0, iemCImpl_hlt); 12381 12891 } 12382 12892 … … 13203 13713 IEMOP_MNEMONIC(cli, "cli"); 13204 13714 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13205 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_CHECK_IRQ_BEFORE, iemCImpl_cli);13715 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_CHECK_IRQ_BEFORE, 0, iemCImpl_cli); 13206 13716 } 13207 13717 … … 13212 13722 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13213 13723 IEM_MC_DEFER_TO_CIMPL_0_RET( IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_CHECK_IRQ_AFTER 13214 | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_INHIBIT_SHADOW, iemCImpl_sti);13724 | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_INHIBIT_SHADOW, 0, iemCImpl_sti); 13215 13725 } 13216 13726 … … 13320 13830 IEM_MC_ARG(uint16_t, u16Target, 0); 13321 13831 IEM_MC_FETCH_GREG_U16(u16Target, IEM_GET_MODRM_RM(pVCpu, bRm)); 13322 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_call_16, u16Target);13832 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, iemCImpl_call_16, u16Target); 13323 13833 IEM_MC_END(); 13324 13834 break; … … 13329 13839 IEM_MC_ARG(uint32_t, u32Target, 0); 13330 13840 IEM_MC_FETCH_GREG_U32(u32Target, IEM_GET_MODRM_RM(pVCpu, bRm)); 13331 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_call_32, u32Target);13841 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, iemCImpl_call_32, u32Target); 13332 13842 IEM_MC_END(); 13333 13843 break; … … 13338 13848 IEM_MC_ARG(uint64_t, u64Target, 0); 13339 13849 IEM_MC_FETCH_GREG_U64(u64Target, IEM_GET_MODRM_RM(pVCpu, bRm)); 13340 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_call_64, u64Target);13850 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, iemCImpl_call_64, u64Target); 13341 13851 IEM_MC_END(); 13342 13852 break; … … 13357 13867 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13358 13868 IEM_MC_FETCH_MEM_U16(u16Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 13359 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_call_16, u16Target);13869 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, iemCImpl_call_16, u16Target); 13360 13870 IEM_MC_END(); 13361 13871 break; … … 13368 13878 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13369 13879 IEM_MC_FETCH_MEM_U32(u32Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 13370 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_call_32, u32Target);13880 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, iemCImpl_call_32, u32Target); 13371 13881 IEM_MC_END(); 13372 13882 break; … … 13379 13889 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13380 13890 IEM_MC_FETCH_MEM_U64(u64Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 13381 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT , iemCImpl_call_64, u64Target);13891 IEM_MC_CALL_CIMPL_1(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_STACK, iemCImpl_call_64, u64Target); 13382 13892 IEM_MC_END(); 13383 13893 break; … … 13388 13898 } 13389 13899 13390 #define IEMOP_BODY_GRP5_FAR_EP(a_bRm, a_fnCImpl ) \13900 #define IEMOP_BODY_GRP5_FAR_EP(a_bRm, a_fnCImpl, a_fCImplExtra) \ 13391 13901 /* Registers? How?? */ \ 13392 13902 if (RT_LIKELY(IEM_IS_MODRM_MEM_MODE(a_bRm))) \ … … 13416 13926 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 2); \ 13417 13927 IEM_MC_HINT_FLUSH_GUEST_SHADOW_GREG(X86_GREG_xSP); \ 13418 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR \13928 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | (a_fCImplExtra) \ 13419 13929 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, \ 13420 13930 a_fnCImpl, u16Sel, offSeg, enmEffOpSize); \ … … 13433 13943 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 4); \ 13434 13944 IEM_MC_HINT_FLUSH_GUEST_SHADOW_GREG(X86_GREG_xSP); \ 13435 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR \13945 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | (a_fCImplExtra) \ 13436 13946 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT, \ 13437 13947 a_fnCImpl, u16Sel, offSeg, enmEffOpSize); \ … … 13451 13961 IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 8); \ 13452 13962 IEM_MC_HINT_FLUSH_GUEST_SHADOW_GREG(X86_GREG_xSP); \ 13453 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_MODE /* no gates */, \ 13963 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | (a_fCImplExtra) \ 13964 | IEM_CIMPL_F_MODE /* no gates */, \ 13454 13965 a_fnCImpl, u16Sel, offSeg, enmEffOpSize); \ 13455 13966 IEM_MC_END(); \ … … 13467 13978 { 13468 13979 IEMOP_MNEMONIC(callf_Ep, "callf Ep"); 13469 IEMOP_BODY_GRP5_FAR_EP(bRm, iemCImpl_callf );13980 IEMOP_BODY_GRP5_FAR_EP(bRm, iemCImpl_callf, IEM_CIMPL_F_BRANCH_STACK); 13470 13981 } 13471 13982 … … 13566 14077 { 13567 14078 IEMOP_MNEMONIC(jmpf_Ep, "jmpf Ep"); 13568 IEMOP_BODY_GRP5_FAR_EP(bRm, iemCImpl_FarJmp );14079 IEMOP_BODY_GRP5_FAR_EP(bRm, iemCImpl_FarJmp, 0); 13569 14080 } 13570 14081 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r101958 r101984 1959 1959 'IEM_CIMPL_F_BRANCH_ANY': ('IEM_CIMPL_F_BRANCH_DIRECT', 'IEM_CIMPL_F_BRANCH_INDIRECT', 1960 1960 'IEM_CIMPL_F_BRANCH_RELATIVE',), 1961 'IEM_CIMPL_F_BRANCH_STACK': (), 1962 'IEM_CIMPL_F_BRANCH_STACK_FAR': (), 1961 1963 'IEM_CIMPL_F_MODE': (), 1962 1964 'IEM_CIMPL_F_RFLAGS': (), … … 2214 2216 for sFlag in sFlags.split('|'): 2215 2217 sFlag = sFlag.strip(); 2218 if sFlag[0] == '(': sFlag = sFlag[1:].strip(); 2219 if sFlag[-1] == ')': sFlag = sFlag[:-1].strip(); 2216 2220 #print('debug: %s' % sFlag) 2217 2221 if sFlag not in g_kdCImplFlags: 2222 if sFlag == '0': 2223 continue; 2218 2224 self.raiseStmtError(sName, 'Unknown flag: %s' % (sFlag, )); 2219 2225 self.dsCImplFlags[sFlag] = True; … … 2233 2239 def parseMcDeferToCImpl(oSelf, sName, asParams): 2234 2240 """ IEM_MC_DEFER_TO_CIMPL_[0|1|2|3]_RET """ 2241 # Note! This code is called by workerIemMcDeferToCImplXRet. 2235 2242 #print('debug: %s, %s,...' % (sName, asParams[0],)); 2236 2243 cArgs = int(sName[-5]); 2237 oSelf.checkStmtParamCount(sName, asParams, 2+ cArgs);2244 oSelf.checkStmtParamCount(sName, asParams, 3 + cArgs); 2238 2245 oSelf.parseCImplFlags(sName, asParams[0]); 2239 return McStmtCall(sName, asParams, 1);2246 return McStmtCall(sName, asParams, 2); 2240 2247 2241 2248 @staticmethod … … 5186 5193 if asArgs is None: 5187 5194 self.raiseError('%s: Closing parenthesis not found!' % (sStmt,)); 5188 if len(asArgs) != cParams + 3:5189 self.raiseError('%s: findAndParseMacroInvocationEx returns %s args, expected %s! '5190 % (sStmt, len(asArgs), cParams + 3,));5195 if len(asArgs) != cParams + 4: 5196 self.raiseError('%s: findAndParseMacroInvocationEx returns %s args, expected %s! (%s)' 5197 % (sStmt, len(asArgs), cParams + 4, asArgs)); 5191 5198 5192 5199 oMcBlock.aoStmts = [ McBlock.parseMcDeferToCImpl(oMcBlock, asArgs[0], asArgs[1:]), ]; -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r101958 r101984 1200 1200 { 1201 1201 IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1202 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_sldt_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1202 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 0, 1203 iemCImpl_sldt_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1203 1204 } 1204 1205 … … 1225 1226 { 1226 1227 IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP); 1227 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_str_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1228 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 0, 1229 iemCImpl_str_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1228 1230 } 1229 1231 … … 1397 1399 hypercall isn't handled by GIM or HMSvm will raise an #UD. 1398 1400 (NEM/win makes ASSUMPTIONS about this behavior.) */ 1399 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT , iemCImpl_vmcall);1401 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, iemCImpl_vmcall); 1400 1402 } 1401 1403 … … 1410 1412 IEMOP_HLP_DONE_DECODING(); 1411 1413 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 1412 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 1414 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, 1413 1415 iemCImpl_vmlaunch); 1414 1416 } … … 1431 1433 IEMOP_HLP_DONE_DECODING(); 1432 1434 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 1433 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 1435 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, 1434 1436 iemCImpl_vmresume); 1435 1437 } … … 1451 1453 IEMOP_HLP_VMX_INSTR("vmxoff", kVmxVDiag_Vmxoff); 1452 1454 IEMOP_HLP_DONE_DECODING(); 1453 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmxoff);1455 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_vmxoff); 1454 1456 } 1455 1457 #else … … 1483 1485 IEMOP_MNEMONIC(monitor, "monitor"); 1484 1486 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo Verify that monitor is allergic to lock prefixes. */ 1485 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_monitor, pVCpu->iem.s.iEffSeg);1487 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_monitor, pVCpu->iem.s.iEffSeg); 1486 1488 } 1487 1489 … … 1492 1494 IEMOP_MNEMONIC(mwait, "mwait"); /** @todo Verify that mwait is allergic to lock prefixes. */ 1493 1495 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1494 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_END_TB | IEM_CIMPL_F_VMEXIT, iemCImpl_mwait);1496 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_END_TB | IEM_CIMPL_F_VMEXIT, 0, iemCImpl_mwait); 1495 1497 } 1496 1498 … … 1524 1526 * OPSIZE one ... */ 1525 1527 IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); 1526 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_xgetbv); 1528 IEM_MC_DEFER_TO_CIMPL_0_RET(0, 1529 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 1530 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX), 1531 iemCImpl_xgetbv); 1527 1532 } 1528 1533 IEMOP_RAISE_INVALID_OPCODE_RET(); … … 1542 1547 * OPSIZE one ... */ 1543 1548 IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); 1544 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_xsetbv);1549 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_xsetbv); 1545 1550 } 1546 1551 IEMOP_RAISE_INVALID_OPCODE_RET(); … … 1571 1576 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1572 1577 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 1573 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 1578 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, 1574 1579 iemCImpl_vmrun); 1575 1580 } … … 1591 1596 hypercall isn't handled by GIM or HMSvm will raise an #UD. 1592 1597 (NEM/win makes ASSUMPTIONS about this behavior.) */ 1593 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT , iemCImpl_vmmcall);1598 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, iemCImpl_vmmcall); 1594 1599 } 1595 1600 … … 1600 1605 IEMOP_MNEMONIC(vmload, "vmload"); 1601 1606 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1602 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmload);1607 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_vmload); 1603 1608 } 1604 1609 #else … … 1613 1618 IEMOP_MNEMONIC(vmsave, "vmsave"); 1614 1619 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1615 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_vmsave);1620 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_vmsave); 1616 1621 } 1617 1622 #else … … 1626 1631 IEMOP_MNEMONIC(stgi, "stgi"); 1627 1632 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1628 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_stgi);1633 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_stgi); 1629 1634 } 1630 1635 #else … … 1639 1644 IEMOP_MNEMONIC(clgi, "clgi"); 1640 1645 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1641 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_clgi);1646 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_clgi); 1642 1647 } 1643 1648 #else … … 1652 1657 IEMOP_MNEMONIC(invlpga, "invlpga"); 1653 1658 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1654 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_invlpga);1659 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_invlpga); 1655 1660 } 1656 1661 #else … … 1665 1670 IEMOP_MNEMONIC(skinit, "skinit"); 1666 1671 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo check prefix effect on the SVM instructions. ASSUMING no lock for now. */ 1667 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_skinit);1672 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_skinit); 1668 1673 } 1669 1674 #else … … 1680 1685 { 1681 1686 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1682 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_smsw_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1687 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 0, 1688 iemCImpl_smsw_reg, IEM_GET_MODRM_RM(pVCpu, bRm), pVCpu->iem.s.enmEffOpSize); 1683 1689 } 1684 1690 … … 1745 1751 IEMOP_HLP_ONLY_64BIT(); 1746 1752 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1747 IEM_MC_DEFER_TO_CIMPL_0_RET(0, iemCImpl_swapgs);1753 IEM_MC_DEFER_TO_CIMPL_0_RET(0, RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_GS), iemCImpl_swapgs); 1748 1754 } 1749 1755 … … 1754 1760 IEMOP_MNEMONIC(rdtscp, "rdtscp"); 1755 1761 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1756 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdtscp); 1762 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 1763 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 1764 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX) 1765 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX), 1766 iemCImpl_rdtscp); 1757 1767 } 1758 1768 … … 1958 1968 IEMOP_MNEMONIC(syscall, "syscall"); /** @todo 286 LOADALL */ 1959 1969 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1960 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 1961 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 1970 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 1971 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 0, 1962 1972 iemCImpl_syscall); 1963 1973 } … … 1969 1979 IEMOP_MNEMONIC(clts, "clts"); 1970 1980 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1971 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_clts);1981 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_clts); 1972 1982 } 1973 1983 … … 1978 1988 IEMOP_MNEMONIC(sysret, "sysret"); /** @todo 386 LOADALL */ 1979 1989 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1980 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 1981 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 1990 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 1991 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 0, 1982 1992 iemCImpl_sysret, pVCpu->iem.s.enmEffOpSize); 1983 1993 } … … 1990 2000 IEMOP_HLP_MIN_486(); 1991 2001 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1992 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_invd);2002 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_invd); 1993 2003 } 1994 2004 … … 2000 2010 IEMOP_HLP_MIN_486(); 2001 2011 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2002 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_wbinvd);2012 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_wbinvd); 2003 2013 } 2004 2014 … … 3284 3294 { 3285 3295 /* mod is ignored, as is operand size overrides. */ 3296 /** @todo testcase: check memory encoding. */ 3286 3297 IEMOP_MNEMONIC(mov_Rd_Cd, "mov Rd,Cd"); 3287 3298 IEMOP_HLP_MIN_386(); … … 3309 3320 IEMOP_HLP_DONE_DECODING(); 3310 3321 3311 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_mov_Rd_Cd, IEM_GET_MODRM_RM(pVCpu, bRm), iCrReg); 3322 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 3323 RT_BIT_64(kIemNativeGstReg_GprFirst + IEM_GET_MODRM_RM(pVCpu, bRm)), 3324 iemCImpl_mov_Rd_Cd, IEM_GET_MODRM_RM(pVCpu, bRm), iCrReg); 3312 3325 } 3313 3326 … … 3316 3329 FNIEMOP_DEF(iemOp_mov_Rd_Dd) 3317 3330 { 3331 /** @todo testcase: check memory encoding. */ 3318 3332 IEMOP_MNEMONIC(mov_Rd_Dd, "mov Rd,Dd"); 3319 3333 IEMOP_HLP_MIN_386(); … … 3322 3336 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R) 3323 3337 IEMOP_RAISE_INVALID_OPCODE_RET(); 3324 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_mov_Rd_Dd, IEM_GET_MODRM_RM(pVCpu, bRm), IEM_GET_MODRM_REG_8(bRm)); 3338 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 3339 RT_BIT_64(kIemNativeGstReg_GprFirst + IEM_GET_MODRM_RM(pVCpu, bRm)), 3340 iemCImpl_mov_Rd_Dd, IEM_GET_MODRM_RM(pVCpu, bRm), IEM_GET_MODRM_REG_8(bRm)); 3325 3341 } 3326 3342 … … 3356 3372 3357 3373 if (iCrReg & (2 | 8)) 3358 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 3374 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 0, 3359 3375 iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3360 3376 else 3361 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 3377 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 0, 3362 3378 iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3363 3379 } … … 3373 3389 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R) 3374 3390 IEMOP_RAISE_INVALID_OPCODE_RET(); 3375 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 3391 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 0, 3376 3392 iemCImpl_mov_Dd_Rd, IEM_GET_MODRM_REG_8(bRm), IEM_GET_MODRM_RM(pVCpu, bRm)); 3377 3393 } … … 3387 3403 if (RT_LIKELY(IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_PENTIUM)) 3388 3404 IEMOP_RAISE_INVALID_OPCODE_RET(); 3389 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_mov_Rd_Td, IEM_GET_MODRM_RM(pVCpu, bRm), IEM_GET_MODRM_REG_8(bRm)); 3405 IEM_MC_DEFER_TO_CIMPL_2_RET(0, RT_BIT_64(kIemNativeGstReg_GprFirst + IEM_GET_MODRM_RM(pVCpu, bRm)), 3406 iemCImpl_mov_Rd_Td, IEM_GET_MODRM_RM(pVCpu, bRm), IEM_GET_MODRM_REG_8(bRm)); 3390 3407 } 3391 3408 … … 3400 3417 if (RT_LIKELY(IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_PENTIUM)) 3401 3418 IEMOP_RAISE_INVALID_OPCODE_RET(); 3402 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_mov_Td_Rd, IEM_GET_MODRM_REG_8(bRm), IEM_GET_MODRM_RM(pVCpu, bRm));3419 IEM_MC_DEFER_TO_CIMPL_2_RET(0, 0, iemCImpl_mov_Td_Rd, IEM_GET_MODRM_REG_8(bRm), IEM_GET_MODRM_RM(pVCpu, bRm)); 3403 3420 } 3404 3421 … … 5139 5156 IEMOP_MNEMONIC(wrmsr, "wrmsr"); 5140 5157 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5141 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_wrmsr);5158 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_wrmsr); 5142 5159 } 5143 5160 … … 5148 5165 IEMOP_MNEMONIC(rdtsc, "rdtsc"); 5149 5166 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5150 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdtsc); 5167 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 5168 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 5169 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX), 5170 iemCImpl_rdtsc); 5151 5171 } 5152 5172 … … 5157 5177 IEMOP_MNEMONIC(rdmsr, "rdmsr"); 5158 5178 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5159 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdmsr); 5179 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 5180 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 5181 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX), 5182 iemCImpl_rdmsr); 5160 5183 } 5161 5184 … … 5166 5189 IEMOP_MNEMONIC(rdpmc, "rdpmc"); 5167 5190 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5168 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_rdpmc); 5191 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 5192 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 5193 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX), 5194 iemCImpl_rdpmc); 5169 5195 } 5170 5196 … … 5175 5201 IEMOP_MNEMONIC0(FIXED, SYSENTER, sysenter, DISOPTYPE_CONTROLFLOW | DISOPTYPE_UNCOND_CONTROLFLOW, 0); 5176 5202 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5177 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 5178 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 5203 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 5204 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, 5179 5205 iemCImpl_sysenter); 5180 5206 } … … 5185 5211 IEMOP_MNEMONIC0(FIXED, SYSEXIT, sysexit, DISOPTYPE_CONTROLFLOW | DISOPTYPE_UNCOND_CONTROLFLOW, 0); 5186 5212 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5187 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 5188 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 5213 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 5214 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, 5189 5215 iemCImpl_sysexit, pVCpu->iem.s.enmEffOpSize); 5190 5216 } … … 8901 8927 IEMOP_HLP_MIN_386(); 8902 8928 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8903 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize); 8929 IEM_MC_DEFER_TO_CIMPL_2_RET(0, 8930 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 8931 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_FS) 8932 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_FS) 8933 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_FS), 8934 iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize); 8904 8935 } 8905 8936 … … 8911 8942 IEMOP_HLP_MIN_486(); /* not all 486es. */ 8912 8943 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8913 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, iemCImpl_cpuid); 8944 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 8945 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX) 8946 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xCX) 8947 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xDX) 8948 | RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xBX), 8949 iemCImpl_cpuid); 8914 8950 } 8915 8951 … … 9692 9728 IEMOP_HLP_MIN_386(); 9693 9729 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9694 IEM_MC_DEFER_TO_CIMPL_2_RET(0, iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize); 9730 IEM_MC_DEFER_TO_CIMPL_2_RET(0, 9731 RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 9732 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_GS) 9733 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_GS) 9734 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_GS), 9735 iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize); 9695 9736 } 9696 9737 … … 9702 9743 IEMOP_HLP_MIN_386(); /* 386SL and later. */ 9703 9744 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9704 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR 9705 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 9745 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 9746 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_END_TB, 0, 9706 9747 iemCImpl_rsm); 9707 9748 } -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r101958 r101984 2160 2160 /* [kIemNativeGstReg_Pc] = */ { CPUMCTX_OFF_AND_SIZE(rip), "rip", }, 2161 2161 /* [kIemNativeGstReg_EFlags] = */ { CPUMCTX_OFF_AND_SIZE(eflags), "eflags", }, 2162 /* [18] = */ { UINT32_C(0xfffffff7), 0, NULL, },2163 /* [19] = */ { UINT32_C(0xfffffff5), 0, NULL, },2164 /* [20] = */ { UINT32_C(0xfffffff3), 0, NULL, },2165 /* [21] = */ { UINT32_C(0xfffffff1), 0, NULL, },2166 /* [22] = */ { UINT32_C(0xffffffef), 0, NULL, },2167 /* [23] = */ { UINT32_C(0xffffffed), 0, NULL, },2168 2162 /* [kIemNativeGstReg_SegSelFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].Sel), "es", }, 2169 2163 /* [kIemNativeGstReg_SegSelFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].Sel), "cs", }, … … 3460 3454 3461 3455 /** 3456 * Converts IEM_CIMPL_F_XXX flags into a guest register shadow copy flush mask. 3457 * 3458 * @returns The flush mask. 3459 * @param fCImpl The IEM_CIMPL_F_XXX flags. 3460 * @param fGstShwFlush The starting flush mask. 3461 */ 3462 DECL_FORCE_INLINE(uint64_t) iemNativeCImplFlagsToGuestShadowFlushMask(uint32_t fCImpl, uint64_t fGstShwFlush) 3463 { 3464 if (fCImpl & IEM_CIMPL_F_BRANCH_FAR) 3465 fGstShwFlush |= RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_CS) 3466 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_CS) 3467 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_CS); 3468 if (fCImpl & IEM_CIMPL_F_BRANCH_STACK_FAR) 3469 fGstShwFlush |= RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP) 3470 | RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_SS) 3471 | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_SS) 3472 | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_SS); 3473 else if (fCImpl & IEM_CIMPL_F_BRANCH_STACK) 3474 fGstShwFlush |= RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP); 3475 if (fCImpl & (IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_STATUS_FLAGS | IEM_CIMPL_F_INHIBIT_SHADOW)) 3476 fGstShwFlush |= RT_BIT_64(kIemNativeGstReg_EFlags); 3477 return fGstShwFlush; 3478 } 3479 3480 3481 /** 3462 3482 * Emits a call to a CImpl function or something similar. 3463 3483 */ 3464 static int32_t iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, 3484 static int32_t iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, uint64_t fGstShwFlush, 3465 3485 uintptr_t pfnCImpl, uint8_t cbInstr, uint8_t cAddParams, 3466 3486 uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) 3467 3487 { 3468 iemNativeRegFlushGuestShadows(pReNative, UINT64_MAX); /** @todo optimize this */ 3488 /* 3489 * Flush stuff. 3490 */ 3491 fGstShwFlush = iemNativeCImplFlagsToGuestShadowFlushMask(pReNative->fCImpl, fGstShwFlush | RT_BIT_64(kIemNativeGstReg_Pc)); 3492 iemNativeRegFlushGuestShadows(pReNative, fGstShwFlush); 3493 3469 3494 off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 4); 3470 3495 … … 3916 3941 *********************************************************************************************************************************/ 3917 3942 3918 #define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl) \3943 #define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl) \ 3919 3944 pReNative->fMc = 0; \ 3920 3945 pReNative->fCImpl = (a_fFlags); \ 3921 return iemNativeEmitCImplCall0(pReNative, off, pCallEntry->idxInstr, (uintptr_t)a_pfnCImpl, a_cbInstr) /** @todo not used ... */3922 3923 3924 #define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0) \3946 return iemNativeEmitCImplCall0(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a_cbInstr) /** @todo not used ... */ 3947 3948 3949 #define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \ 3925 3950 pReNative->fMc = 0; \ 3926 3951 pReNative->fCImpl = (a_fFlags); \ 3927 return iemNativeEmitCImplCall1(pReNative, off, pCallEntry->idxInstr, (uintptr_t)a_pfnCImpl, a_cbInstr, a0) 3928 3929 DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall1(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, 3952 return iemNativeEmitCImplCall1(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a_cbInstr, a0) 3953 3954 DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall1(PIEMRECOMPILERSTATE pReNative, uint32_t off, 3955 uint8_t idxInstr, uint64_t a_fGstShwFlush, 3930 3956 uintptr_t pfnCImpl, uint8_t cbInstr, uint64_t uArg0) 3931 3957 { 3932 return iemNativeEmitCImplCall(pReNative, off, idxInstr, pfnCImpl, cbInstr, 1, uArg0, 0, 0);3933 } 3934 3935 3936 #define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0, a1) \3958 return iemNativeEmitCImplCall(pReNative, off, idxInstr, a_fGstShwFlush, pfnCImpl, cbInstr, 1, uArg0, 0, 0); 3959 } 3960 3961 3962 #define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \ 3937 3963 pReNative->fMc = 0; \ 3938 3964 pReNative->fCImpl = (a_fFlags); \ 3939 return iemNativeEmitCImplCall2(pReNative, off, pCallEntry->idxInstr, (uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1) 3940 3941 DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall2(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, 3965 return iemNativeEmitCImplCall2(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, \ 3966 (uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1) 3967 3968 DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall2(PIEMRECOMPILERSTATE pReNative, uint32_t off, 3969 uint8_t idxInstr, uint64_t a_fGstShwFlush, 3942 3970 uintptr_t pfnCImpl, uint8_t cbInstr, uint64_t uArg0, uint64_t uArg1) 3943 3971 { 3944 return iemNativeEmitCImplCall(pReNative, off, idxInstr, pfnCImpl, cbInstr, 2, uArg0, uArg1, 0);3945 } 3946 3947 3948 #define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0, a1, a2) \3972 return iemNativeEmitCImplCall(pReNative, off, idxInstr, a_fGstShwFlush, pfnCImpl, cbInstr, 2, uArg0, uArg1, 0); 3973 } 3974 3975 3976 #define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \ 3949 3977 pReNative->fMc = 0; \ 3950 3978 pReNative->fCImpl = (a_fFlags); \ 3951 return iemNativeEmitCImplCall3(pReNative, off, pCallEntry->idxInstr, (uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1, a2) 3952 3953 DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, 3979 return iemNativeEmitCImplCall3(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, \ 3980 (uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1, a2) 3981 3982 DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall3(PIEMRECOMPILERSTATE pReNative, uint32_t off, 3983 uint8_t idxInstr, uint64_t a_fGstShwFlush, 3954 3984 uintptr_t pfnCImpl, uint8_t cbInstr, uint64_t uArg0, uint64_t uArg1, 3955 3985 uint64_t uArg2) 3956 3986 { 3957 return iemNativeEmitCImplCall(pReNative, off, idxInstr, pfnCImpl, cbInstr, 3, uArg0, uArg1, uArg2);3987 return iemNativeEmitCImplCall(pReNative, off, idxInstr, a_fGstShwFlush, pfnCImpl, cbInstr, 3, uArg0, uArg1, uArg2); 3958 3988 } 3959 3989 … … 5537 5567 /** @todo Always flush EFLAGS if this is an xxF variation. */ 5538 5568 iemNativeRegFlushGuestShadows(pReNative, 5539 RT_BIT_64(kIemNativeGstReg_Pc) 5540 | (pReNative->fCImpl & ( IEM_CIMPL_F_RFLAGS 5541 | IEM_CIMPL_F_STATUS_FLAGS 5542 | IEM_CIMPL_F_INHIBIT_SHADOW) 5543 ? RT_BIT_64(kIemNativeGstReg_EFlags) : 0) 5544 ); 5569 iemNativeCImplFlagsToGuestShadowFlushMask(pReNative->fCImpl, RT_BIT_64(kIemNativeGstReg_Pc)) ); 5545 5570 5546 5571 return iemNativeEmitCheckCallRetAndPassUp(pReNative, off, idxInstr); … … 5924 5949 PFNIEMCIMPL0 const pfnCImpl = (PFNIEMCIMPL0)(uintptr_t)pCallEntry->auParams[0]; 5925 5950 uint8_t const cbInstr = (uint8_t)pCallEntry->auParams[1]; 5926 return iemNativeEmitCImplCall(pReNative, off, pCallEntry->idxInstr, (uintptr_t)pfnCImpl, cbInstr, 0, 0, 0, 0); 5951 /** @todo Drop this crap hack? 5952 * We don't have the flush mask here so we we must pass UINT64_MAX. */ 5953 return iemNativeEmitCImplCall(pReNative, off, pCallEntry->idxInstr, UINT64_MAX, (uintptr_t)pfnCImpl, cbInstr, 0, 0, 0, 0); 5927 5954 } 5928 5955 -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp
r101694 r101984 278 278 /** Variant of IEM_MC_DEFER_TO_CIMPL_0_RET with explicit instruction 279 279 * length parameter. */ 280 #define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl) \280 #define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl) \ 281 281 return (a_pfnCImpl)(pVCpu, (a_cbInstr)) 282 282 #undef IEM_MC_DEFER_TO_CIMPL_0_RET … … 284 284 /** Variant of IEM_MC_DEFER_TO_CIMPL_1_RET with explicit instruction 285 285 * length parameter. */ 286 #define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0) \286 #define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \ 287 287 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0) 288 288 #undef IEM_MC_DEFER_TO_CIMPL_1_RET 289 289 290 290 /** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */ 291 #define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0, a1) \291 #define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \ 292 292 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1) 293 293 #undef IEM_MC_DEFER_TO_CIMPL_2_RET … … 295 295 /** Variant of IEM_MC_DEFER_TO_CIMPL_3 with explicit instruction length 296 296 * parameter. */ 297 #define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0, a1, a2) \297 #define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \ 298 298 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2) 299 299 #undef IEM_MC_DEFER_TO_CIMPL_3_RET … … 301 301 /** Variant of IEM_MC_DEFER_TO_CIMPL_4 with explicit instruction length 302 302 * parameter. */ 303 #define IEM_MC_DEFER_TO_CIMPL_4_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0, a1, a2, a3) \303 #define IEM_MC_DEFER_TO_CIMPL_4_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \ 304 304 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3) 305 305 #undef IEM_MC_DEFER_TO_CIMPL_4_RET … … 307 307 /** Variant of IEM_MC_DEFER_TO_CIMPL_5 with explicit instruction length 308 308 * parameter. */ 309 #define IEM_MC_DEFER_TO_CIMPL_5_RET_THREADED(a_cbInstr, a_fFlags, a_ pfnCImpl, a0, a1, a2, a3, a4) \309 #define IEM_MC_DEFER_TO_CIMPL_5_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \ 310 310 return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4) 311 311 #undef IEM_MC_DEFER_TO_CIMPL_5_RET -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r101950 r101984 407 407 'IEM_CIMPL_F_BRANCH_CONDITIONAL': False, 408 408 # IEM_CIMPL_F_BRANCH_ANY should only be used for testing, so not included here. 409 'IEM_CIMPL_F_BRANCH_STACK': False, 410 'IEM_CIMPL_F_BRANCH_STACK_FAR': False, 409 411 'IEM_CIMPL_F_RFLAGS': False, 410 412 'IEM_CIMPL_F_INHIBIT_SHADOW': False, … … 1126 1128 or sRef.startswith('g_') 1127 1129 or sRef.startswith('iemAImpl_') 1130 or sRef.startswith('kIemNativeGstReg_') 1128 1131 or sRef in ( 'int8_t', 'int16_t', 'int32_t', 'int64_t', 1129 1132 'INT8_C', 'INT16_C', 'INT32_C', 'INT64_C', … … 1133 1136 'INT8_MIN', 'INT16_MIN', 'INT32_MIN', 'INT64_MIN', 1134 1137 'sizeof', 'NOREF', 'RT_NOREF', 'IEMMODE_64BIT', 1135 'RT_BIT_32', 'true', 'false', 'NIL_RTGCPTR',) ): 1138 'RT_BIT_32', 'RT_BIT_64', 'true', 'false', 1139 'NIL_RTGCPTR',) ): 1136 1140 pass; 1137 1141 -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdTables.h
r101538 r101984 301 301 */ 302 302 #undef IEM_MC_DEFER_TO_CIMPL_0_RET 303 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_ pfnCImpl) \303 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl) \ 304 304 return iemThreadedRecompilerMcDeferToCImpl0(pVCpu, a_fFlags, a_pfnCImpl) 305 305 -
trunk/src/VBox/VMM/include/IEMInternal.h
r101722 r101984 619 619 /** Force end of TB after the instruction. */ 620 620 #define IEM_CIMPL_F_END_TB RT_BIT_32(15) 621 /** Flag set if a branch may also modify the stack (push/pop return address). */ 622 #define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16) 623 /** Flag set if a branch may also modify the stack (push/pop return address) 624 * and switch it (load/restore SS:RSP). */ 625 #define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17) 621 626 /** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */ 622 627 #define IEM_CIMPL_F_XCPT \ 623 (IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT) 628 (IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR \ 629 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT) 624 630 625 631 /** The block calls a C-implementation instruction function with two implicit arguments. … … 627 633 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE. 628 634 * @note The python scripts will add this is missing. */ 629 #define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(1 6)635 #define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18) 630 636 /** The block calls an ASM-implementation instruction function. 631 637 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and 632 638 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE. 633 639 * @note The python scripts will add this is missing. */ 634 #define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(1 7)640 #define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19) 635 641 /** The block calls an ASM-implementation instruction function with an implicit 636 642 * X86FXSTATE pointer argument. 637 643 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and IEM_CIMPL_F_CALLS_AIMPL. 638 644 * @note The python scripts will add this is missing. */ 639 #define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32( 18)645 #define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20) 640 646 /** @} */ 641 647 … … 1305 1311 /** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched). 1306 1312 * 1307 * These flags parallels IEM_CIMPL_F_BRANCH_XXX.1313 * These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags. 1308 1314 * 1309 1315 * @{ */ … … 1320 1326 /** Flag set if it's a far branch. */ 1321 1327 #define IEMBRANCHED_F_FAR UINT8_C(0x10) 1328 /** Flag set if the stack pointer is modified. */ 1329 #define IEMBRANCHED_F_STACK UINT8_C(0x20) 1330 /** Flag set if the stack pointer and (maybe) the stack segment are modified. */ 1331 #define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40) 1322 1332 /** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */ 1323 #define IEMBRANCHED_F_ZERO UINT8_C(0x 20)1333 #define IEMBRANCHED_F_ZERO UINT8_C(0x80) 1324 1334 /** @} */ 1325 1335 … … 4920 4930 * @return Strict VBox status code. 4921 4931 */ 4922 #define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)4932 #define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError) 4923 4933 4924 4934 /** … … 4930 4940 * @return Strict VBox status code. 4931 4941 */ 4932 #define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)4942 #define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix) 4933 4943 4934 4944 /** … … 4940 4950 * @return Strict VBox status code. 4941 4951 */ 4942 #define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)4952 #define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode) 4943 4953 4944 4954 /** … … 4951 4961 * @see IEMOP_RAISE_INVALID_OPCODE_RET 4952 4962 */ 4953 #define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)4963 #define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode) 4954 4964 4955 4965 /** @} */ -
trunk/src/VBox/VMM/include/IEMMc.h
r101958 r101984 2101 2101 * 2102 2102 * @param a_fFlags IEM_CIMPL_F_XXX. 2103 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed 2104 * in the native recompiler. 2103 2105 * @param a_pfnCImpl The pointer to the C routine. 2104 2106 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0. 2105 2107 */ 2106 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_ pfnCImpl) \2108 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl) \ 2107 2109 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))) 2108 2110 … … 2114 2116 * 2115 2117 * @param a_fFlags IEM_CIMPL_F_XXX. 2118 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed 2119 * in the native recompiler. 2116 2120 * @param a_pfnCImpl The pointer to the C routine. 2117 2121 * @param a0 The argument. 2118 2122 */ 2119 #define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_ pfnCImpl, a0) \2123 #define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \ 2120 2124 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)) 2121 2125 … … 2127 2131 * 2128 2132 * @param a_fFlags IEM_CIMPL_F_XXX. 2133 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed 2134 * in the native recompiler. 2129 2135 * @param a_pfnCImpl The pointer to the C routine. 2130 2136 * @param a0 The first extra argument. 2131 2137 * @param a1 The second extra argument. 2132 2138 */ 2133 #define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_ pfnCImpl, a0, a1) \2139 #define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \ 2134 2140 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)) 2135 2141 … … 2141 2147 * 2142 2148 * @param a_fFlags IEM_CIMPL_F_XXX. 2149 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed 2150 * in the native recompiler. 2143 2151 * @param a_pfnCImpl The pointer to the C routine. 2144 2152 * @param a0 The first extra argument. … … 2146 2154 * @param a2 The third extra argument. 2147 2155 */ 2148 #define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_ pfnCImpl, a0, a1, a2) \2156 #define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \ 2149 2157 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)) 2150 2158 -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r101913 r101984 348 348 { 349 349 kIemNativeGstReg_GprFirst = 0, 350 kIemNativeGstReg_GprLast = 15,350 kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15, 351 351 kIemNativeGstReg_Pc, 352 kIemNativeGstReg_EFlags, /**< This one is problematic since the higher bits are used internally. */ 353 /* gap: 18..23 */ 354 kIemNativeGstReg_SegSelFirst = 24, 355 kIemNativeGstReg_SegSelLast = 29, 356 kIemNativeGstReg_SegBaseFirst = 30, 357 kIemNativeGstReg_SegBaseLast = 35, 358 kIemNativeGstReg_SegLimitFirst = 36, 359 kIemNativeGstReg_SegLimitLast = 41, 352 kIemNativeGstReg_EFlags, /**< 32-bit, includes internal flags. */ 353 kIemNativeGstReg_SegSelFirst, 354 kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5, 355 kIemNativeGstReg_SegBaseFirst, 356 kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5, 357 kIemNativeGstReg_SegLimitFirst, 358 kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5, 360 359 kIemNativeGstReg_End 361 360 } IEMNATIVEGSTREG; -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r101958 r101984 941 941 #define IEM_MC_CALL_CIMPL_5(a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \ 942 942 do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; return VINF_SUCCESS; } while (0) 943 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_ pfnCImpl)return VINF_SUCCESS944 #define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_ pfnCImpl, a0)return VINF_SUCCESS945 #define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_ pfnCImpl, a0, a1)return VINF_SUCCESS946 #define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_ pfnCImpl, a0, a1, a2)return VINF_SUCCESS943 #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl) return VINF_SUCCESS 944 #define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) return VINF_SUCCESS 945 #define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) return VINF_SUCCESS 946 #define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) return VINF_SUCCESS 947 947 948 948 #define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
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