- Timestamp:
- Jul 4, 2008 9:17:59 AM (16 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/CPUM.cpp
r10123 r10208 343 343 344 344 /* 345 * Determin the default.345 * Determine the default. 346 346 * 347 347 * Intel returns values of the highest standard function, while AMD … … 352 352 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx, 353 353 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx); 354 355 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers. 356 * Safe to pass on to the guest. 357 * 358 * Intel: 0x800000005 reserved 359 * 0x800000006 L2 cache information 360 * AMD: 0x800000005 L1 cache information 361 * 0x800000006 L2/L3 cache information 362 */ 354 363 355 364 /* … … 365 374 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef; 366 375 367 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x8000000 4))368 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x8000000 4);376 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000006)) 377 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000006); 369 378 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000) 370 379 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1 … … 376 385 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then 377 386 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1. 378 * We don't support more than 1 processor.387 * We currently don't support more than 1 processor. 379 388 */ 380 389 pCPUM->aGuestCpuIdStd[4].eax = 0;
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