Index: trunk/include/iprt/err.mac
===================================================================
--- trunk/include/iprt/err.mac	(revision 102092)
+++ trunk/include/iprt/err.mac	(revision 102126)
@@ -936,4 +936,7 @@
 %define VERR_CR_PKIX_NOT_RSA_PRIVATE_KEY    (-23523)
 %define VERR_CR_PKIX_NOT_RSA_PUBLIC_KEY    (-23524)
+%define VERR_CR_PKIX_NOT_ECDSA_PRIVATE_KEY    (-23525)
+%define VERR_CR_PKIX_NOT_ECDSA_PUBLIC_KEY    (-23526)
+%define VERR_CR_PKIX_OSSL_D2I_KEY_PARAMS_FAILED    (-23527)
 %define VERR_CR_STORE_GENERIC_ERROR    (-23700)
 %define VERR_CR_KEY_UNKNOWN_TYPE    (-23800)
@@ -953,4 +956,8 @@
 %define VINF_CR_KEY_WAS_DECRYPTED    (23814)
 %define VERR_CR_KEY_GEN_FAILED_RSA    (-23815)
+%define VERR_CR_KEY_ALGO_PARAMS_UNEXPECTED    (-23816)
+%define VERR_CR_KEY_ALGO_PARAMS_MISSING    (-23817)
+%define VERR_CR_KEY_ALGO_PARAMS_UNKNOWN    (-23818)
+%define VERR_CR_KEY_ALGO_PARAMS_MISMATCH    (-23819)
 %define VERR_CR_RSA_GENERIC_ERROR    (-23900)
 %define VERR_BIGNUM_SENSITIVE_INPUT    (-24000)
@@ -966,4 +973,5 @@
 %define VERR_CR_DIGEST_SEVERELY_COMPROMISED    (-24204)
 %define VERR_CR_DIGEST_NOT_SUPPORTED    (-24205)
+%define VERR_CR_OPENSSL_VERSION_TOO_OLD    (-24395)
 %define VERR_CR_PASSWORD_2_KEY_DERIVIATION_FAILED    (-24396)
 %define VERR_CR_RANDOM_SETUP_FAILED    (-24397)
@@ -1200,2 +1208,21 @@
 %define VERR_HARDAVL_BAD_HEIGHT    (-26819)
 %define VERR_HARDAVL_UNBALANCED    (-26820)
+%define VERR_FDT_DTB_MALFORMED    (-27000)
+%define VERR_FDT_DTB_HDR_MAGIC_INVALID    (-27001)
+%define VERR_FDT_DTB_HDR_VERSION_NOT_SUPPORTED    (-27002)
+%define VERR_FDT_DTB_HDR_LAST_COMPAT_VERSION_INVALID    (-27003)
+%define VERR_FDT_DTB_HDR_SIZE_INVALID    (-27004)
+%define VERR_FDT_DTB_HDR_MEM_RSV_BLOCK_OFF_INVALID    (-27005)
+%define VERR_FDT_DTB_HDR_STRUCT_BLOCK_OFF_INVALID    (-27006)
+%define VERR_FDT_DTB_HDR_STRINGS_BLOCK_OFF_INVALID    (-27007)
+%define VERR_FDT_DTB_MEM_RSV_BLOCK_TERMINATOR_MISSING    (-27008)
+%define VERR_FDT_DTB_STRINGS_BLOCK_NOT_TERMINATED    (-27009)
+%define VERR_FDT_DTB_STRUCTS_BLOCK_TOKEN_INVALID    (-27010)
+%define VERR_FDT_DTB_STRUCTS_BLOCK_NODE_NAME_INVALID    (-27011)
+%define VERR_FDT_DTB_STRUCTS_BLOCK_STRING_NOT_TERMINATED    (-27012)
+%define VERR_FDT_DTB_STRUCTS_BLOCK_MALFORMED_PADDING    (-27013)
+%define VERR_FDT_DTB_STRUCTS_BLOCK_PREMATURE_END    (-27014)
+%define VERR_FDT_DTB_PROP_NAME_OFF_TOO_LARGE    (-27015)
+%define VERR_FDT_DTB_PROP_SIZE_MALFORMED    (-27016)
+%define VERR_FDT_DTB_PROP_STRING_NOT_TERMINATED    (-27017)
+%define VERR_FDT_AT_ROOT_LEVEL    (-27018)
Index: trunk/include/iprt/formats/dwarf.mac
===================================================================
--- trunk/include/iprt/formats/dwarf.mac	(revision 102092)
+++ trunk/include/iprt/formats/dwarf.mac	(revision 102126)
@@ -469,3 +469,127 @@
 %define DWREG_AMD64_FCW     65
 %define DWREG_AMD64_FSW     66
+%define DWREG_ARM64_X0              0
+%define DWREG_ARM64_X1              1
+%define DWREG_ARM64_X2              2
+%define DWREG_ARM64_X3              3
+%define DWREG_ARM64_X4              4
+%define DWREG_ARM64_X5              5
+%define DWREG_ARM64_X6              6
+%define DWREG_ARM64_X7              7
+%define DWREG_ARM64_X8              8
+%define DWREG_ARM64_X9              9
+%define DWREG_ARM64_X10             10
+%define DWREG_ARM64_X11             11
+%define DWREG_ARM64_X12             12
+%define DWREG_ARM64_X13             13
+%define DWREG_ARM64_X14             14
+%define DWREG_ARM64_X15             15
+%define DWREG_ARM64_X16             16
+%define DWREG_ARM64_X17             17
+%define DWREG_ARM64_X18             18
+%define DWREG_ARM64_X19             19
+%define DWREG_ARM64_X20             20
+%define DWREG_ARM64_X21             21
+%define DWREG_ARM64_X22             22
+%define DWREG_ARM64_X23             23
+%define DWREG_ARM64_X24             24
+%define DWREG_ARM64_X25             25
+%define DWREG_ARM64_X26             26
+%define DWREG_ARM64_X27             27
+%define DWREG_ARM64_X28             28
+%define DWREG_ARM64_X29             29
+%define DWREG_ARM64_X30             30
+%define DWREG_ARM64_SP              31
+%define DWREG_ARM64_BP              DWREG_ARM64_X29
+%define DWREG_ARM64_LR              DWREG_ARM64_X30
+%define DWREG_ARM64_PC              32
+%define DWREG_ARM64_ELR_MODE        33
+%define DWREG_ARM64_RA_SIGN_STATE   34
+%define DWREG_ARM64_TPIDRRO_ELO     35
+%define DWREG_ARM64_TPIDR_ELO       36
+%define DWREG_ARM64_TPIDR_EL1       37
+%define DWREG_ARM64_TPIDR_EL2       38
+%define DWREG_ARM64_TPIDR_EL3       39
+%define DWREG_ARM64_VG              46
+%define DWREG_ARM64_FFR             47
+%define DWREG_ARM64_P0              48
+%define DWREG_ARM64_P1              49
+%define DWREG_ARM64_P2              50
+%define DWREG_ARM64_P3              51
+%define DWREG_ARM64_P4              52
+%define DWREG_ARM64_P5              53
+%define DWREG_ARM64_P6              54
+%define DWREG_ARM64_P7              55
+%define DWREG_ARM64_P8              56
+%define DWREG_ARM64_P9              57
+%define DWREG_ARM64_P10             58
+%define DWREG_ARM64_P11             59
+%define DWREG_ARM64_P12             60
+%define DWREG_ARM64_P13             61
+%define DWREG_ARM64_P14             62
+%define DWREG_ARM64_P15             63
+%define DWREG_ARM64_V0              64
+%define DWREG_ARM64_V1              65
+%define DWREG_ARM64_V2              66
+%define DWREG_ARM64_V3              67
+%define DWREG_ARM64_V4              68
+%define DWREG_ARM64_V5              69
+%define DWREG_ARM64_V6              70
+%define DWREG_ARM64_V7              71
+%define DWREG_ARM64_V8              72
+%define DWREG_ARM64_V9              73
+%define DWREG_ARM64_V10             74
+%define DWREG_ARM64_V11             75
+%define DWREG_ARM64_V12             76
+%define DWREG_ARM64_V13             77
+%define DWREG_ARM64_V14             78
+%define DWREG_ARM64_V15             79
+%define DWREG_ARM64_V16             80
+%define DWREG_ARM64_V17             81
+%define DWREG_ARM64_V18             82
+%define DWREG_ARM64_V19             83
+%define DWREG_ARM64_V20             84
+%define DWREG_ARM64_V21             85
+%define DWREG_ARM64_V22             86
+%define DWREG_ARM64_V23             87
+%define DWREG_ARM64_V24             88
+%define DWREG_ARM64_V25             89
+%define DWREG_ARM64_V26             90
+%define DWREG_ARM64_V27             91
+%define DWREG_ARM64_V28             92
+%define DWREG_ARM64_V29             93
+%define DWREG_ARM64_V30             94
+%define DWREG_ARM64_V31             95
+%define DWREG_ARM64_Z0              96
+%define DWREG_ARM64_Z1              97
+%define DWREG_ARM64_Z2              98
+%define DWREG_ARM64_Z3              99
+%define DWREG_ARM64_Z4              100
+%define DWREG_ARM64_Z5              101
+%define DWREG_ARM64_Z6              102
+%define DWREG_ARM64_Z7              103
+%define DWREG_ARM64_Z8              104
+%define DWREG_ARM64_Z9              105
+%define DWREG_ARM64_Z10             106
+%define DWREG_ARM64_Z11             107
+%define DWREG_ARM64_Z12             108
+%define DWREG_ARM64_Z13             109
+%define DWREG_ARM64_Z14             110
+%define DWREG_ARM64_Z15             111
+%define DWREG_ARM64_Z16             112
+%define DWREG_ARM64_Z17             113
+%define DWREG_ARM64_Z18             114
+%define DWREG_ARM64_Z19             115
+%define DWREG_ARM64_Z20             116
+%define DWREG_ARM64_Z21             117
+%define DWREG_ARM64_Z22             118
+%define DWREG_ARM64_Z23             119
+%define DWREG_ARM64_Z24             120
+%define DWREG_ARM64_Z25             121
+%define DWREG_ARM64_Z26             122
+%define DWREG_ARM64_Z27             123
+%define DWREG_ARM64_Z28             124
+%define DWREG_ARM64_Z29             125
+%define DWREG_ARM64_Z30             126
+%define DWREG_ARM64_Z31             127
 %endif
Index: trunk/include/iprt/x86.mac
===================================================================
--- trunk/include/iprt/x86.mac	(revision 102092)
+++ trunk/include/iprt/x86.mac	(revision 102126)
@@ -87,4 +87,6 @@
 %define X86_EFL_LIVE_MASK   0x003f7fd5
 %define X86_EFL_RA1_MASK    RT_BIT_32(1)
+%define X86_EFL_RAZ_MASK    0xffc08028
+%define X86_EFL_RAZ_LO_MASK 0x00008028
 %define X86_EFL_IOPL_SHIFT  12
 %define X86_EFL_GET_IOPL(efl)   (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
@@ -209,8 +211,10 @@
 %define X86_CPUID_STEXT_FEATURE_ECX_PKU               RT_BIT_32(3)
 %define X86_CPUID_STEXT_FEATURE_ECX_OSPKE             RT_BIT_32(4)
+%define X86_CPUID_STEXT_FEATURE_ECX_CET_SS            RT_BIT_32(7)
 %define X86_CPUID_STEXT_FEATURE_ECX_MAWAU             0x003e0000
 %define X86_CPUID_STEXT_FEATURE_ECX_RDPID             RT_BIT_32(2)
 %define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC            RT_BIT_32(30)
 %define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR          RT_BIT_32(10)
+%define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT           RT_BIT_32(20)
 %define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT_32(26)
 %define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
@@ -305,8 +309,15 @@
 %define X86_CPUID_SVM_FEATURE_EDX_VGIF                      RT_BIT(16)
 %define X86_CPUID_SVM_FEATURE_EDX_GMET                      RT_BIT(17)
+%define X86_CPUID_SVM_FEATURE_EDX_X2AVIC                    RT_BIT(18)
 %define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK                  RT_BIT(19)
 %define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL                 RT_BIT(20)
+%define X86_CPUID_SVM_FEATURE_EDX_ROGPT                     RT_BIT(21)
 %define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE         RT_BIT(23)
 %define X86_CPUID_SVM_FEATURE_EDX_TLBICTL                   RT_BIT(24)
+%define X86_CPUID_SVM_FEATURE_EDX_VNMI                      RT_BIT(25)
+%define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT                  RT_BIT(26)
+%define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG   RT_BIT(27)
+%define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK    RT_BIT(28)
+%define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD        RT_BIT(29)
 %define X86_CR0_PE                          RT_BIT_32(0)
 %define X86_CR0_PROTECTION_ENABLE           RT_BIT_32(0)
@@ -337,5 +348,5 @@
 %define X86_CR3_PAE_PAGE_MASK               (0xffffffe0)
 %define X86_CR3_AMD64_PAGE_MASK             0x000ffffffffff000
-%define X86_CR3_EPT_PAGE_MASK               0x0000fffffffff000
+%define X86_CR3_EPT_PAGE_MASK               0x000ffffffffff000
 %define X86_CR4_VME                         RT_BIT_32(0)
 %define X86_CR4_PVI                         RT_BIT_32(1)
@@ -413,4 +424,12 @@
 %define X86_DR7_RW_ALL_MASKS                0x33330000
 %ifndef VBOX_FOR_DTRACE_LIB
+ %define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp)   ( ((a_uDR7) & (0x000f0000 << ((a_iBp) * 4))) == 0 )
+ %define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
+    ( ((a_uDR7) & (0x03 << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
+ %define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
+    (   (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
+     || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
+     || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
+     || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
  %define X86_DR7_ANY_RW_IO(uDR7) \
     (   (    0x22220000 & (uDR7) )
@@ -486,4 +505,16 @@
 %define MSR_IA32_APERF                      0xE8
 %define MSR_IA32_MTRR_CAP                   0xFE
+%define MSR_IA32_MTRR_CAP_VCNT_MASK         0x00000000000000ff
+%define MSR_IA32_MTRR_CAP_FIX               RT_BIT_64(8)
+%define MSR_IA32_MTRR_CAP_WC                RT_BIT_64(10)
+%define MSR_IA32_MTRR_CAP_SMRR              RT_BIT_64(11)
+%define MSR_IA32_MTRR_CAP_PRMRR             RT_BIT_64(12)
+%ifndef VBOX_FOR_DTRACE_LIB
+%endif
+%define X86_MTRR_MT_UC                      0
+%define X86_MTRR_MT_WC                      1
+%define X86_MTRR_MT_WT                      4
+%define X86_MTRR_MT_WP                      5
+%define X86_MTRR_MT_WB                      6
 %define MSR_IA32_ARCH_CAPABILITIES          0x10a
 %define MSR_IA32_ARCH_CAP_F_RDCL_NO         RT_BIT_32(0)
@@ -505,4 +536,12 @@
 %define MSR_IA32_CR_PAT                     0x277
 %define MSR_IA32_CR_PAT_INIT_VAL            0x0007040600070406
+%define MSR_IA32_PAT_MT_UC                  0
+%define MSR_IA32_PAT_MT_WC                  1
+%define MSR_IA32_PAT_MT_RSVD_2              2
+%define MSR_IA32_PAT_MT_RSVD_3              3
+%define MSR_IA32_PAT_MT_WT                  4
+%define MSR_IA32_PAT_MT_WP                  5
+%define MSR_IA32_PAT_MT_WB                  6
+%define MSR_IA32_PAT_MT_UCD                 7
 %define MSR_IA32_PERFEVTSEL0                0x186
 %define MSR_IA32_PERFEVTSEL1                0x187
@@ -694,4 +733,11 @@
 %define MSR_IA32_MTRR_FIX4K_F8000           0x26f
 %define MSR_IA32_MTRR_DEF_TYPE              0x2FF
+%define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK  0xFF
+%define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN     RT_BIT_64(10)
+%define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN      RT_BIT_64(11)
+%define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK   (  MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
+                                             | MSR_IA32_MTRR_DEF_TYPE_FIXED_EN    \
+                                             | MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
+%define MSR_IA32_MTRR_PHYSMASK_VALID        RT_BIT_64(11)
 %define MSR_IA32_PERF_GLOBAL_STATUS         0x38E
 %define MSR_IA32_PERF_GLOBAL_CTRL           0x38F
@@ -719,4 +765,5 @@
 %define MSR_IA32_VMX_VMFUNC                 0x491
 %define MSR_IA32_VMX_PROCBASED_CTLS3        0x492
+%define MSR_IA32_VMX_EXIT_CTLS2             0x493
 %define MSR_IA32_RTIT_CTL                   0x570
 %define MSR_IA32_DS_AREA                    0x600
@@ -739,4 +786,15 @@
 %define MSR_TURBO_ACTIVATION_RATIO          0x64c
 %define MSR_CORE_PERF_LIMIT_REASONS         0x64f
+%define MSR_IA32_U_CET                      0x6a0
+%define MSR_IA32_S_CET                      0x6a2
+ %define MSR_IA32_CET_SH_STK_EN             RT_BIT_64(0)
+ %define MSR_IA32_CET_WR_SHSTK_EN           RT_BIT_64(1)
+ %define MSR_IA32_CET_ENDBR_EN              RT_BIT_64(2)
+ %define MSR_IA32_CET_LEG_IW_EN             RT_BIT_64(3)
+ %define MSR_IA32_CET_NO_TRACK_EN           RT_BIT_64(4)
+ %define MSR_IA32_CET_SUPPRESS_DIS          RT_BIT_64(5)
+ %define MSR_IA32_CET_SUPPRESS              RT_BIT_64(10)
+ %define MSR_IA32_CET_TRACKER               RT_BIT_64(11)
+ %define MSR_IA32_CET_EB_LEG_BITMAP_BASE    0xfffffffffffff000
 %define MSR_IA32_X2APIC_START               0x800
 %define MSR_IA32_X2APIC_ID                  0x802
@@ -1355,4 +1413,8 @@
 %define X86_MODRM_MOD_SMASK     0x03
 %define X86_MODRM_MOD_SHIFT     6
+%define X86_MOD_MEM0            0
+%define X86_MOD_MEM1            1
+%define X86_MOD_MEM4            2
+%define X86_MOD_REG             3
 %ifndef VBOX_FOR_DTRACE_LIB
  %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
@@ -1366,4 +1428,6 @@
 %define X86_SIB_SCALE_SHIFT   6
 %ifndef VBOX_FOR_DTRACE_LIB
+ %define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
+    (((a_Scale) << X86_SIB_SCALE_SHIFT) | ((a_IndexReg) << X86_SIB_INDEX_SHIFT) | (a_BaseReg))
 %endif
 %define X86_GREG_xAX            0
@@ -1402,4 +1466,5 @@
 %define X86_OP_PRF_REPZ         0xf3
 %define X86_OP_PRF_REPNZ        0xf2
+%define X86_OP_REX              0x40
 %define X86_OP_REX_B            0x41
 %define X86_OP_REX_X            0x42
