Changeset 102425 in vbox
- Timestamp:
- Dec 1, 2023 11:00:26 PM (16 months ago)
- svn:sync-xref-src-repo-rev:
- 160568
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 6 edited
-
VMMAll/IEMAllInstOneByte.cpp.h (modified) (3 diffs)
-
VMMAll/IEMAllInstPython.py (modified) (2 diffs)
-
VMMAll/IEMAllN8vePython.py (modified) (1 diff)
-
VMMAll/IEMAllThrdPython.py (modified) (2 diffs)
-
include/IEMMc.h (modified) (1 diff)
-
testcase/tstIEMCheckMc.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r102424 r102425 11530 11530 { 11531 11531 IEMOP_MNEMONIC(fisttp_m64i, "fisttp m64i"); 11532 IEM_MC_BEGIN(3, 2, 0, 0);11532 IEM_MC_BEGIN(3, 3, 0, 0); 11533 11533 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 11534 IEM_MC_LOCAL(uint16_t, u16Fsw);11535 IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);11536 IEM_MC_ARG(int64_t *, pi64Dst, 1);11537 IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);11538 11539 11534 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 11535 11540 11536 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11541 11537 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 11542 11538 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 11543 11544 IEM_MC_MEM_MAP(pi64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);11545 11539 IEM_MC_PREPARE_FPU_USAGE(); 11540 11541 IEM_MC_LOCAL(uint8_t, bUnmapInfo); 11542 IEM_MC_ARG(int64_t *, pi64Dst, 1); 11543 IEM_MC_MEM_MAP_I64_WO(pi64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11544 11545 IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2); 11546 11546 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) { 11547 IEM_MC_LOCAL(uint16_t, u16Fsw); 11548 IEM_MC_ARG_LOCAL_REF(uint16_t *,pu16Fsw, u16Fsw, 0); 11547 11549 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i64, pu16Fsw, pi64Dst, pr80Value); 11548 IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE (pi64Dst, IEM_ACCESS_DATA_W, u16Fsw);11550 IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(pi64Dst, bUnmapInfo, u16Fsw); 11549 11551 IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 11550 11552 } IEM_MC_ELSE() { 11551 11553 IEM_MC_IF_FCW_IM() { 11552 11554 IEM_MC_STORE_MEM_I64_CONST_BY_REF(pi64Dst, INT64_MIN /* (integer indefinite) */); 11553 IEM_MC_MEM_COMMIT_AND_UNMAP(pi64Dst, IEM_ACCESS_DATA_W); 11555 IEM_MC_MEM_COMMIT_AND_UNMAP_WO(pi64Dst, bUnmapInfo); 11556 } IEM_MC_ELSE() { 11557 IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(pi64Dst, bUnmapInfo); 11554 11558 } IEM_MC_ENDIF(); 11555 11559 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); … … 11565 11569 { 11566 11570 IEMOP_MNEMONIC(fst_m64r, "fst m64r"); 11567 IEM_MC_BEGIN(3, 2, 0, 0);11571 IEM_MC_BEGIN(3, 3, 0, 0); 11568 11572 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 11569 IEM_MC_LOCAL(uint16_t, u16Fsw);11570 IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);11571 IEM_MC_ARG(PRTFLOAT64U, pr64Dst, 1);11572 IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);11573 11574 11573 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 11574 11575 11575 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11576 11576 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 11577 11577 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 11578 11579 IEM_MC_MEM_MAP(pr64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);11580 11578 IEM_MC_PREPARE_FPU_USAGE(); 11579 11580 IEM_MC_LOCAL(uint8_t, bUnmapInfo); 11581 IEM_MC_ARG(PRTFLOAT64U, pr64Dst, 1); 11582 IEM_MC_MEM_MAP_R64_WO(pr64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11583 11584 IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2); 11581 11585 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) { 11586 IEM_MC_LOCAL(uint16_t, u16Fsw); 11587 IEM_MC_ARG_LOCAL_REF(uint16_t *,pu16Fsw, u16Fsw, 0); 11582 11588 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r64, pu16Fsw, pr64Dst, pr80Value); 11583 IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE (pr64Dst, IEM_ACCESS_DATA_W, u16Fsw);11589 IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(pr64Dst, bUnmapInfo, u16Fsw); 11584 11590 IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 11585 11591 } IEM_MC_ELSE() { 11586 11592 IEM_MC_IF_FCW_IM() { 11587 11593 IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(pr64Dst); 11588 IEM_MC_MEM_COMMIT_AND_UNMAP(pr64Dst, IEM_ACCESS_DATA_W); 11594 IEM_MC_MEM_COMMIT_AND_UNMAP_WO(pr64Dst, bUnmapInfo); 11595 } IEM_MC_ELSE() { 11596 IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(pr64Dst, bUnmapInfo); 11589 11597 } IEM_MC_ENDIF(); 11590 11598 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); … … 11602 11610 { 11603 11611 IEMOP_MNEMONIC(fstp_m64r, "fstp m64r"); 11604 IEM_MC_BEGIN(3, 2, 0, 0);11612 IEM_MC_BEGIN(3, 3, 0, 0); 11605 11613 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 11606 IEM_MC_LOCAL(uint16_t, u16Fsw);11607 IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);11608 IEM_MC_ARG(PRTFLOAT64U, pr64Dst, 1);11609 IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);11610 11611 11614 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 11615 11612 11616 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11613 11617 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 11614 11618 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 11615 11616 IEM_MC_MEM_MAP(pr64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);11617 11619 IEM_MC_PREPARE_FPU_USAGE(); 11620 11621 IEM_MC_LOCAL(uint8_t, bUnmapInfo); 11622 IEM_MC_ARG(PRTFLOAT64U, pr64Dst, 1); 11623 IEM_MC_MEM_MAP_R64_WO(pr64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11624 11625 IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2); 11618 11626 IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0) { 11627 IEM_MC_LOCAL(uint16_t, u16Fsw); 11628 IEM_MC_ARG_LOCAL_REF(uint16_t *,pu16Fsw, u16Fsw, 0); 11619 11629 IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r64, pu16Fsw, pr64Dst, pr80Value); 11620 IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE (pr64Dst, IEM_ACCESS_DATA_W, u16Fsw);11630 IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(pr64Dst, bUnmapInfo, u16Fsw); 11621 11631 IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 11622 11632 } IEM_MC_ELSE() { 11623 11633 IEM_MC_IF_FCW_IM() { 11624 11634 IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(pr64Dst); 11625 IEM_MC_MEM_COMMIT_AND_UNMAP(pr64Dst, IEM_ACCESS_DATA_W); 11635 IEM_MC_MEM_COMMIT_AND_UNMAP_WO(pr64Dst, bUnmapInfo); 11636 } IEM_MC_ELSE() { 11637 IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(pr64Dst, bUnmapInfo); 11626 11638 } IEM_MC_ENDIF(); 11627 11639 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r102424 r102425 3029 3029 'IEM_MC_MEM_MAP_EX': (McBlock.parseMcGeneric, True, False, ), 3030 3030 'IEM_MC_MEM_MAP_I32_WO': (McBlock.parseMcGeneric, True, False, ), 3031 'IEM_MC_MEM_MAP_I64_WO': (McBlock.parseMcGeneric, True, False, ), 3031 3032 'IEM_MC_MEM_MAP_R32_WO': (McBlock.parseMcGeneric, True, False, ), 3033 'IEM_MC_MEM_MAP_R64_WO': (McBlock.parseMcGeneric, True, False, ), 3034 'IEM_MC_MEM_MAP_R80_WO': (McBlock.parseMcGeneric, True, False, ), 3032 3035 'IEM_MC_MEM_MAP_U8_RW': (McBlock.parseMcGeneric, True, False, ), 3033 3036 'IEM_MC_MEM_MAP_U8_RO': (McBlock.parseMcGeneric, True, False, ), … … 3042 3045 'IEM_MC_MEM_MAP_U64_RO': (McBlock.parseMcGeneric, True, False, ), 3043 3046 'IEM_MC_MEM_MAP_U64_WO': (McBlock.parseMcGeneric, True, False, ), 3044 'IEM_MC_MEM_MAP_R80_WO': (McBlock.parseMcGeneric, True, False, ),3045 3047 'IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO': (McBlock.parseMcGeneric, True, False, ), 3046 3048 'IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX': (McBlock.parseMcGeneric, True, False, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py
r102424 r102425 146 146 'IEM_MC_MEM_FLAT_MAP_EX': (None, True, False, ), 147 147 'IEM_MC_MEM_FLAT_MAP': (None, True, False, ), 148 'IEM_MC_MEM_FLAT_MAP_I32_WO': (None, True, False, ), 149 'IEM_MC_MEM_FLAT_MAP_I64_WO': (None, True, False, ), 150 'IEM_MC_MEM_FLAT_MAP_R32_WO': (None, True, False, ), 151 'IEM_MC_MEM_FLAT_MAP_R64_WO': (None, True, False, ), 152 'IEM_MC_MEM_FLAT_MAP_R80_WO': (None, True, False, ), 148 153 'IEM_MC_MEM_FLAT_MAP_U16_RO': (None, True, False, ), 149 154 'IEM_MC_MEM_FLAT_MAP_U16_RW': (None, True, False, ), 150 155 'IEM_MC_MEM_FLAT_MAP_U32_RO': (None, True, False, ), 151 156 'IEM_MC_MEM_FLAT_MAP_U32_RW': (None, True, False, ), 152 'IEM_MC_MEM_FLAT_MAP_I32_WO': (None, True, False, ),153 'IEM_MC_MEM_FLAT_MAP_R32_WO': (None, True, False, ),154 157 'IEM_MC_MEM_FLAT_MAP_U64_RO': (None, True, False, ), 155 158 'IEM_MC_MEM_FLAT_MAP_U64_RW': (None, True, False, ), 156 159 'IEM_MC_MEM_FLAT_MAP_U8_RO': (None, True, False, ), 157 160 'IEM_MC_MEM_FLAT_MAP_U8_RW': (None, True, False, ), 158 'IEM_MC_MEM_FLAT_MAP_R80_WO': (None, True, False, ),159 161 'IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE': (None, True, False, ), 160 162 'IEM_MC_STORE_MEM_FLAT_U128': (None, True, False, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r102424 r102425 705 705 'IEM_MC_STORE_MEM_U256_ALIGN_AVX': ( 0, 'IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX' ), 706 706 'IEM_MC_MEM_MAP': ( 2, 'IEM_MC_MEM_FLAT_MAP' ), 707 'IEM_MC_MEM_MAP_I32_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_I32_WO' ), 708 'IEM_MC_MEM_MAP_I64_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_I64_WO' ), 709 'IEM_MC_MEM_MAP_R32_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_R32_WO' ), 710 'IEM_MC_MEM_MAP_R64_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_R64_WO' ), 711 'IEM_MC_MEM_MAP_R80_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_R80_WO' ), 707 712 'IEM_MC_MEM_MAP_U8_RW': ( 2, 'IEM_MC_MEM_FLAT_MAP_U8_RW' ), 708 713 'IEM_MC_MEM_MAP_U8_RO': ( 2, 'IEM_MC_MEM_FLAT_MAP_U8_RO' ), … … 714 719 'IEM_MC_MEM_MAP_U32_RO': ( 2, 'IEM_MC_MEM_FLAT_MAP_U32_RO' ), 715 720 'IEM_MC_MEM_MAP_U32_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_U32_WO' ), 716 'IEM_MC_MEM_MAP_I32_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_I32_WO' ),717 'IEM_MC_MEM_MAP_R32_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_R32_WO' ),718 721 'IEM_MC_MEM_MAP_U64_RW': ( 2, 'IEM_MC_MEM_FLAT_MAP_U64_RW' ), 719 722 'IEM_MC_MEM_MAP_U64_RO': ( 2, 'IEM_MC_MEM_FLAT_MAP_U64_RO' ), 720 723 'IEM_MC_MEM_MAP_U64_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_U64_WO' ), 721 'IEM_MC_MEM_MAP_R80_WO': ( 2, 'IEM_MC_MEM_FLAT_MAP_R80_WO' ),722 724 'IEM_MC_MEM_MAP_EX': ( 3, 'IEM_MC_MEM_FLAT_MAP_EX' ), 723 725 }; -
trunk/src/VBox/VMM/include/IEMMc.h
r102424 r102425 2095 2095 # define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \ 2096 2096 (a_pu64Mem) = iemMemFlatMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem)) 2097 #endif 2098 2099 /** int64_t alias. */ 2100 #ifndef IEM_WITH_SETJMP 2101 # define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \ 2102 IEM_MC_MEM_MAP_U64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) 2103 #else 2104 # define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \ 2105 (a_pi64Mem) = (int64_t *)iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem)) 2106 #endif 2107 2108 /** Flat int64_t alias. */ 2109 #ifndef IEM_WITH_SETJMP 2110 # define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \ 2111 IEM_MC_MEM_FLAT_MAP_U64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) 2112 #else 2113 # define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \ 2114 (a_pi64Mem) = (int64_t *)iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem)) 2115 #endif 2116 2117 /** RTFLOAT64U alias. */ 2118 #ifndef IEM_WITH_SETJMP 2119 # define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \ 2120 IEM_MC_MEM_MAP_U64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) 2121 #else 2122 # define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \ 2123 (a_pr64Mem) = (PRTFLOAT64U)iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem)) 2124 #endif 2125 2126 /** Flat RTFLOAT64U alias. */ 2127 #ifndef IEM_WITH_SETJMP 2128 # define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \ 2129 IEM_MC_MEM_FLAT_MAP_U64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) 2130 #else 2131 # define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \ 2132 (a_pr64Mem) = (PRTFLOAT64U)iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem)) 2097 2133 #endif 2098 2134 -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r102424 r102425 930 930 #define IEM_MC_POP_U64(a_pu64Value) do { CHK_VAR(a_pu64Value); (void)fMcBegin; } while (0) 931 931 932 #define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pi32Mem); (a_pi32Mem) = NULL; CHK_PTYPE(int32_t *, a_pi32Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 933 #define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pi64Mem); (a_pi64Mem) = NULL; CHK_PTYPE(int64_t *, a_pi64Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 934 #define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pr32Mem); (a_pr32Mem) = NULL; CHK_PTYPE(RTFLOAT32U *, a_pr32Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 935 #define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pr64Mem); (a_pr64Mem) = NULL; CHK_PTYPE(RTFLOAT64U *, a_pr64Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 936 #define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pr80Mem); (a_pr80Mem) = NULL; CHK_PTYPE(RTFLOAT80U *, a_pr80Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 932 937 #define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu8Mem); (a_pu8Mem) = NULL; CHK_PTYPE(uint8_t *, a_pu8Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 933 938 #define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu8Mem); (a_pu8Mem) = NULL; CHK_PTYPE(uint8_t const *, a_pu8Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) … … 939 944 #define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu32Mem); (a_pu32Mem) = NULL; CHK_PTYPE(uint32_t const *, a_pu32Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 940 945 #define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu32Mem); (a_pu32Mem) = NULL; CHK_PTYPE(uint32_t *, a_pu32Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 941 #define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pi32Mem); (a_pi32Mem) = NULL; CHK_PTYPE(int32_t *, a_pi32Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)942 #define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pr32Mem); (a_pr32Mem) = NULL; CHK_PTYPE(RTFLOAT32U *, a_pr32Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)943 946 #define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu64Mem); (a_pu64Mem) = NULL; CHK_PTYPE(uint64_t *, a_pu64Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 944 947 #define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu64Mem); (a_pu64Mem) = NULL; CHK_PTYPE(uint64_t const *, a_pu64Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 945 948 #define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pu64Mem); (a_pu64Mem) = NULL; CHK_PTYPE(uint64_t *, a_pu64Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0) 946 #define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { CHK_VAR(a_pr80Mem); (a_pr80Mem) = NULL; CHK_PTYPE(RTFLOAT80U *, a_pr80Mem); CHK_VAR(a_bUnmapInfo); CHK_TYPE(uint8_t, a_bUnmapInfo); a_bUnmapInfo = 1; CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)947 949 948 950 #define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_pvMem, a_bMapInfo) do { CHK_VAR(a_pvMem); CHK_VAR(a_bMapInfo); CHK_TYPE(uint8_t, a_bMapInfo); (void)fMcBegin; } while (0)
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