Changeset 102445 in vbox
- Timestamp:
- Dec 4, 2023 8:42:02 AM (12 months ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r101386 r102445 3359 3359 EMIT_INSTR_PLUS_ICEBP vpaddsw, YMM8, YMM9, YMM10 3360 3360 EMIT_INSTR_PLUS_ICEBP vpaddsw, YMM8, YMM9, FSxBX 3361 %endif 3362 3363 ; 3364 ; [V]PSLLW 3365 ; 3366 EMIT_INSTR_PLUS_ICEBP psllw, MM1, MM2 3367 EMIT_INSTR_PLUS_ICEBP psllw, MM1, FSxBX 3368 EMIT_INSTR_PLUS_ICEBP psllw, MM1, 001h 3369 EMIT_INSTR_PLUS_ICEBP psllw, MM1, 012h 3370 EMIT_INSTR_PLUS_ICEBP psllw, XMM1, XMM2 3371 EMIT_INSTR_PLUS_ICEBP psllw, XMM1, FSxBX 3372 EMIT_INSTR_PLUS_ICEBP psllw, XMM1, 001h 3373 EMIT_INSTR_PLUS_ICEBP psllw, XMM1, 012h 3374 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM1, XMM2, XMM3 3375 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM1, XMM2, FSxBX 3376 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM1, XMM2, 001h 3377 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM1, XMM2, 012h 3378 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM1, YMM2, XMM3 3379 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM1, YMM2, FSxBX 3380 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM1, YMM2, 001h 3381 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM1, YMM2, 012h 3382 %if TMPL_BITS == 64 3383 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM8, XMM9, XMM10 3384 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM8, XMM9, FSxBX 3385 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM8, XMM9, 001h 3386 EMIT_INSTR_PLUS_ICEBP vpsllw, XMM8, XMM9, 012h 3387 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM8, YMM9, XMM10 3388 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM8, YMM9, FSxBX 3389 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM8, YMM9, 001h 3390 EMIT_INSTR_PLUS_ICEBP vpsllw, YMM8, YMM9, 012h 3391 %endif 3392 3393 ; 3394 ; [V]PSLLD 3395 ; 3396 EMIT_INSTR_PLUS_ICEBP pslld, MM1, MM2 3397 EMIT_INSTR_PLUS_ICEBP pslld, MM1, FSxBX 3398 EMIT_INSTR_PLUS_ICEBP pslld, MM1, 001h 3399 EMIT_INSTR_PLUS_ICEBP pslld, MM1, 012h 3400 EMIT_INSTR_PLUS_ICEBP pslld, XMM1, XMM2 3401 EMIT_INSTR_PLUS_ICEBP pslld, XMM1, FSxBX 3402 EMIT_INSTR_PLUS_ICEBP pslld, XMM1, 001h 3403 EMIT_INSTR_PLUS_ICEBP pslld, XMM1, 012h 3404 EMIT_INSTR_PLUS_ICEBP vpslld, XMM1, XMM2, XMM3 3405 EMIT_INSTR_PLUS_ICEBP vpslld, XMM1, XMM2, FSxBX 3406 EMIT_INSTR_PLUS_ICEBP vpslld, XMM1, XMM2, 001h 3407 EMIT_INSTR_PLUS_ICEBP vpslld, XMM1, XMM2, 012h 3408 EMIT_INSTR_PLUS_ICEBP vpslld, YMM1, YMM2, XMM3 3409 EMIT_INSTR_PLUS_ICEBP vpslld, YMM1, YMM2, FSxBX 3410 EMIT_INSTR_PLUS_ICEBP vpslld, YMM1, YMM2, 001h 3411 EMIT_INSTR_PLUS_ICEBP vpslld, YMM1, YMM2, 012h 3412 %if TMPL_BITS == 64 3413 EMIT_INSTR_PLUS_ICEBP vpslld, XMM8, XMM9, XMM10 3414 EMIT_INSTR_PLUS_ICEBP vpslld, XMM8, XMM9, FSxBX 3415 EMIT_INSTR_PLUS_ICEBP vpslld, XMM8, XMM9, 001h 3416 EMIT_INSTR_PLUS_ICEBP vpslld, XMM8, XMM9, 012h 3417 EMIT_INSTR_PLUS_ICEBP vpslld, YMM8, YMM9, XMM10 3418 EMIT_INSTR_PLUS_ICEBP vpslld, YMM8, YMM9, FSxBX 3419 EMIT_INSTR_PLUS_ICEBP vpslld, YMM8, YMM9, 001h 3420 EMIT_INSTR_PLUS_ICEBP vpslld, YMM8, YMM9, 012h 3421 %endif 3422 3423 ; 3424 ; [V]PSLLQ 3425 ; 3426 EMIT_INSTR_PLUS_ICEBP psllq, MM1, MM2 3427 EMIT_INSTR_PLUS_ICEBP psllq, MM1, FSxBX 3428 EMIT_INSTR_PLUS_ICEBP psllq, MM1, 001h 3429 EMIT_INSTR_PLUS_ICEBP psllq, MM1, 012h 3430 EMIT_INSTR_PLUS_ICEBP psllq, XMM1, XMM2 3431 EMIT_INSTR_PLUS_ICEBP psllq, XMM1, FSxBX 3432 EMIT_INSTR_PLUS_ICEBP psllq, XMM1, 001h 3433 EMIT_INSTR_PLUS_ICEBP psllq, XMM1, 012h 3434 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM1, XMM2, XMM3 3435 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM1, XMM2, FSxBX 3436 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM1, XMM2, 001h 3437 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM1, XMM2, 012h 3438 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM1, YMM2, XMM3 3439 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM1, YMM2, FSxBX 3440 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM1, YMM2, 001h 3441 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM1, YMM2, 012h 3442 %if TMPL_BITS == 64 3443 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM8, XMM9, XMM10 3444 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM8, XMM9, FSxBX 3445 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM8, XMM9, 001h 3446 EMIT_INSTR_PLUS_ICEBP vpsllq, XMM8, XMM9, 012h 3447 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM8, YMM9, XMM10 3448 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM8, YMM9, FSxBX 3449 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM8, YMM9, 001h 3450 EMIT_INSTR_PLUS_ICEBP vpsllq, YMM8, YMM9, 012h 3451 %endif 3452 3453 ; 3454 ; [V]PSRAW 3455 ; 3456 EMIT_INSTR_PLUS_ICEBP psraw, MM1, MM2 3457 EMIT_INSTR_PLUS_ICEBP psraw, MM1, FSxBX 3458 EMIT_INSTR_PLUS_ICEBP psraw, MM1, 001h 3459 EMIT_INSTR_PLUS_ICEBP psraw, MM1, 012h 3460 EMIT_INSTR_PLUS_ICEBP psraw, XMM1, XMM2 3461 EMIT_INSTR_PLUS_ICEBP psraw, XMM1, FSxBX 3462 EMIT_INSTR_PLUS_ICEBP psraw, XMM1, 001h 3463 EMIT_INSTR_PLUS_ICEBP psraw, XMM1, 012h 3464 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM1, XMM2, XMM3 3465 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM1, XMM2, FSxBX 3466 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM1, XMM2, 001h 3467 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM1, XMM2, 012h 3468 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM1, YMM2, XMM3 3469 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM1, YMM2, FSxBX 3470 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM1, YMM2, 001h 3471 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM1, YMM2, 012h 3472 %if TMPL_BITS == 64 3473 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM8, XMM9, XMM10 3474 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM8, XMM9, FSxBX 3475 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM8, XMM9, 001h 3476 EMIT_INSTR_PLUS_ICEBP vpsraw, XMM8, XMM9, 012h 3477 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM8, YMM9, XMM10 3478 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM8, YMM9, FSxBX 3479 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM8, YMM9, 001h 3480 EMIT_INSTR_PLUS_ICEBP vpsraw, YMM8, YMM9, 012h 3481 %endif 3482 3483 ; 3484 ; [V]PSRAD 3485 ; 3486 EMIT_INSTR_PLUS_ICEBP psrad, MM1, MM2 3487 EMIT_INSTR_PLUS_ICEBP psrad, MM1, FSxBX 3488 EMIT_INSTR_PLUS_ICEBP psrad, MM1, 001h 3489 EMIT_INSTR_PLUS_ICEBP psrad, MM1, 012h 3490 EMIT_INSTR_PLUS_ICEBP psrad, XMM1, XMM2 3491 EMIT_INSTR_PLUS_ICEBP psrad, XMM1, FSxBX 3492 EMIT_INSTR_PLUS_ICEBP psrad, XMM1, 001h 3493 EMIT_INSTR_PLUS_ICEBP psrad, XMM1, 012h 3494 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM1, XMM2, XMM3 3495 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM1, XMM2, FSxBX 3496 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM1, XMM2, 001h 3497 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM1, XMM2, 012h 3498 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM1, YMM2, XMM3 3499 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM1, YMM2, FSxBX 3500 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM1, YMM2, 001h 3501 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM1, YMM2, 012h 3502 %if TMPL_BITS == 64 3503 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM8, XMM9, XMM10 3504 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM8, XMM9, FSxBX 3505 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM8, XMM9, 001h 3506 EMIT_INSTR_PLUS_ICEBP vpsrad, XMM8, XMM9, 012h 3507 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM8, YMM9, XMM10 3508 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM8, YMM9, FSxBX 3509 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM8, YMM9, 001h 3510 EMIT_INSTR_PLUS_ICEBP vpsrad, YMM8, YMM9, 012h 3511 %endif 3512 3513 ; 3514 ; no VPSRAQ -- does not exist until AVX512 3515 ; 3516 3517 ; 3518 ; [V]PSRLW 3519 ; 3520 EMIT_INSTR_PLUS_ICEBP psrlw, MM1, MM2 3521 EMIT_INSTR_PLUS_ICEBP psrlw, MM1, FSxBX 3522 EMIT_INSTR_PLUS_ICEBP psrlw, MM1, 001h 3523 EMIT_INSTR_PLUS_ICEBP psrlw, MM1, 012h 3524 EMIT_INSTR_PLUS_ICEBP psrlw, XMM1, XMM2 3525 EMIT_INSTR_PLUS_ICEBP psrlw, XMM1, FSxBX 3526 EMIT_INSTR_PLUS_ICEBP psrlw, XMM1, 001h 3527 EMIT_INSTR_PLUS_ICEBP psrlw, XMM1, 012h 3528 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM1, XMM2, XMM3 3529 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM1, XMM2, FSxBX 3530 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM1, XMM2, 001h 3531 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM1, XMM2, 012h 3532 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM1, YMM2, XMM3 3533 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM1, YMM2, FSxBX 3534 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM1, YMM2, 001h 3535 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM1, YMM2, 012h 3536 %if TMPL_BITS == 64 3537 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM8, XMM9, XMM10 3538 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM8, XMM9, FSxBX 3539 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM8, XMM9, 001h 3540 EMIT_INSTR_PLUS_ICEBP vpsrlw, XMM8, XMM9, 012h 3541 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM8, YMM9, XMM10 3542 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM8, YMM9, FSxBX 3543 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM8, YMM9, 001h 3544 EMIT_INSTR_PLUS_ICEBP vpsrlw, YMM8, YMM9, 012h 3545 %endif 3546 3547 ; 3548 ; [V]PSRLD 3549 ; 3550 EMIT_INSTR_PLUS_ICEBP psrld, MM1, MM2 3551 EMIT_INSTR_PLUS_ICEBP psrld, MM1, FSxBX 3552 EMIT_INSTR_PLUS_ICEBP psrld, MM1, 001h 3553 EMIT_INSTR_PLUS_ICEBP psrld, MM1, 012h 3554 EMIT_INSTR_PLUS_ICEBP psrld, XMM1, XMM2 3555 EMIT_INSTR_PLUS_ICEBP psrld, XMM1, FSxBX 3556 EMIT_INSTR_PLUS_ICEBP psrld, XMM1, 001h 3557 EMIT_INSTR_PLUS_ICEBP psrld, XMM1, 012h 3558 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM1, XMM2, XMM3 3559 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM1, XMM2, FSxBX 3560 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM1, XMM2, 001h 3561 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM1, XMM2, 012h 3562 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM1, YMM2, XMM3 3563 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM1, YMM2, FSxBX 3564 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM1, YMM2, 001h 3565 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM1, YMM2, 012h 3566 %if TMPL_BITS == 64 3567 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM8, XMM9, XMM10 3568 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM8, XMM9, FSxBX 3569 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM8, XMM9, 001h 3570 EMIT_INSTR_PLUS_ICEBP vpsrld, XMM8, XMM9, 012h 3571 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM8, YMM9, XMM10 3572 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM8, YMM9, FSxBX 3573 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM8, YMM9, 001h 3574 EMIT_INSTR_PLUS_ICEBP vpsrld, YMM8, YMM9, 012h 3575 %endif 3576 3577 ; 3578 ; [V]PSRLQ 3579 ; 3580 EMIT_INSTR_PLUS_ICEBP psrlq, MM1, MM2 3581 EMIT_INSTR_PLUS_ICEBP psrlq, MM1, FSxBX 3582 EMIT_INSTR_PLUS_ICEBP psrlq, MM1, 001h 3583 EMIT_INSTR_PLUS_ICEBP psrlq, MM1, 012h 3584 EMIT_INSTR_PLUS_ICEBP psrlq, XMM1, XMM2 3585 EMIT_INSTR_PLUS_ICEBP psrlq, XMM1, FSxBX 3586 EMIT_INSTR_PLUS_ICEBP psrlq, XMM1, 001h 3587 EMIT_INSTR_PLUS_ICEBP psrlq, XMM1, 012h 3588 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM1, XMM2, XMM3 3589 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM1, XMM2, FSxBX 3590 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM1, XMM2, 001h 3591 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM1, XMM2, 012h 3592 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM1, YMM2, XMM3 3593 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM1, YMM2, FSxBX 3594 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM1, YMM2, 001h 3595 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM1, YMM2, 012h 3596 %if TMPL_BITS == 64 3597 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM8, XMM9, XMM10 3598 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM8, XMM9, FSxBX 3599 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM8, XMM9, 001h 3600 EMIT_INSTR_PLUS_ICEBP vpsrlq, XMM8, XMM9, 012h 3601 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM8, YMM9, XMM10 3602 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM8, YMM9, FSxBX 3603 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM8, YMM9, 001h 3604 EMIT_INSTR_PLUS_ICEBP vpsrlq, YMM8, YMM9, 012h 3361 3605 %endif 3362 3606 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r101375 r102445 205 205 206 206 /** Exception type \#4 test configurations, for the SSE version of movups. */ 207 /** Tests 10:SSE & 11:SSE expect success, not GP */ 207 208 static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4Unaligned[] = 208 209 { … … 223 224 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ 224 225 /* Memory misalignment and alignment checks: */ 225 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ 226 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_DB, X86_XCPT_AC }, /* #11 */ 226 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* movups special */ 227 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_DB, X86_XCPT_AC }, /* #11 */ /* movups special */ 228 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ 229 /* AMD only: */ 230 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ 231 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ 232 }; 233 234 /** Exception type \#4 test configurations, for psll/psra/psrl. */ 235 /** Test 11:AVX expects success, not AC */ 236 /** @todo proliferation of exception test config tables is not sustainable, find a better way? */ 237 static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4psll[] = 238 { 239 /* 240 * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to 241 * +AVX +AMD/SSE 242 * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR 243 * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ 244 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ 245 { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ 246 { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ 247 { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ 248 { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ 249 { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ 250 { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ 251 { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ 252 { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ 253 { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ 254 /* Memory misalignment and alignment checks: */ 255 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */ 256 { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_DB }, /* #11 */ /* psll special */ 227 257 { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ 228 258 /* AMD only: */ … … 8573 8603 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 8574 8604 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 8605 } 8606 8607 8608 /* 8609 * [V]PSLLW/[V]PSLLD/[V]PSLLQ - Shift packed data left logical 8610 */ 8611 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_MM1_MM2_icebp); 8612 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_MM1_FSxBX_icebp); 8613 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_MM1_001h_icebp); 8614 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_MM1_012h_icebp); 8615 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_XMM1_XMM2_icebp); 8616 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_XMM1_FSxBX_icebp); 8617 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_XMM1_001h_icebp); 8618 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllw_XMM1_012h_icebp); 8619 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp); 8620 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp); 8621 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp); 8622 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp); 8623 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp); 8624 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp); 8625 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp); 8626 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp); 8627 extern FNBS3FAR bs3CpuInstr3_vpsllw_XMM8_XMM9_XMM10_icebp_c64; 8628 extern FNBS3FAR bs3CpuInstr3_vpsllw_XMM8_XMM9_FSxBX_icebp_c64; 8629 extern FNBS3FAR bs3CpuInstr3_vpsllw_XMM8_XMM9_001h_icebp_c64; 8630 extern FNBS3FAR bs3CpuInstr3_vpsllw_XMM8_XMM9_012h_icebp_c64; 8631 extern FNBS3FAR bs3CpuInstr3_vpsllw_YMM8_YMM9_XMM10_icebp_c64; 8632 extern FNBS3FAR bs3CpuInstr3_vpsllw_YMM8_YMM9_FSxBX_icebp_c64; 8633 extern FNBS3FAR bs3CpuInstr3_vpsllw_YMM8_YMM9_001h_icebp_c64; 8634 extern FNBS3FAR bs3CpuInstr3_vpsllw_YMM8_YMM9_012h_icebp_c64; 8635 8636 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_MM1_MM2_icebp); 8637 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_MM1_FSxBX_icebp); 8638 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_MM1_001h_icebp); 8639 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_MM1_012h_icebp); 8640 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_XMM1_XMM2_icebp); 8641 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_XMM1_FSxBX_icebp); 8642 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_XMM1_001h_icebp); 8643 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pslld_XMM1_012h_icebp); 8644 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp); 8645 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp); 8646 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp); 8647 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp); 8648 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp); 8649 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp); 8650 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp); 8651 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp); 8652 extern FNBS3FAR bs3CpuInstr3_vpslld_XMM8_XMM9_XMM10_icebp_c64; 8653 extern FNBS3FAR bs3CpuInstr3_vpslld_XMM8_XMM9_FSxBX_icebp_c64; 8654 extern FNBS3FAR bs3CpuInstr3_vpslld_XMM8_XMM9_001h_icebp_c64; 8655 extern FNBS3FAR bs3CpuInstr3_vpslld_XMM8_XMM9_012h_icebp_c64; 8656 extern FNBS3FAR bs3CpuInstr3_vpslld_YMM8_YMM9_XMM10_icebp_c64; 8657 extern FNBS3FAR bs3CpuInstr3_vpslld_YMM8_YMM9_FSxBX_icebp_c64; 8658 extern FNBS3FAR bs3CpuInstr3_vpslld_YMM8_YMM9_001h_icebp_c64; 8659 extern FNBS3FAR bs3CpuInstr3_vpslld_YMM8_YMM9_012h_icebp_c64; 8660 8661 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_MM1_MM2_icebp); 8662 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_MM1_FSxBX_icebp); 8663 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_MM1_001h_icebp); 8664 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_MM1_012h_icebp); 8665 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_XMM1_XMM2_icebp); 8666 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_XMM1_FSxBX_icebp); 8667 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_XMM1_001h_icebp); 8668 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psllq_XMM1_012h_icebp); 8669 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp); 8670 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp); 8671 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp); 8672 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp); 8673 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp); 8674 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp); 8675 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp); 8676 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp); 8677 extern FNBS3FAR bs3CpuInstr3_vpsllq_XMM8_XMM9_XMM10_icebp_c64; 8678 extern FNBS3FAR bs3CpuInstr3_vpsllq_XMM8_XMM9_FSxBX_icebp_c64; 8679 extern FNBS3FAR bs3CpuInstr3_vpsllq_XMM8_XMM9_001h_icebp_c64; 8680 extern FNBS3FAR bs3CpuInstr3_vpsllq_XMM8_XMM9_012h_icebp_c64; 8681 extern FNBS3FAR bs3CpuInstr3_vpsllq_YMM8_YMM9_XMM10_icebp_c64; 8682 extern FNBS3FAR bs3CpuInstr3_vpsllq_YMM8_YMM9_FSxBX_icebp_c64; 8683 extern FNBS3FAR bs3CpuInstr3_vpsllq_YMM8_YMM9_001h_icebp_c64; 8684 extern FNBS3FAR bs3CpuInstr3_vpsllq_YMM8_YMM9_012h_icebp_c64; 8685 8686 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psllw_pslld_psllq(uint8_t bMode) 8687 { 8688 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = 8689 { 8690 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 8691 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 8692 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 8693 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 8694 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8695 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-16 */ 8696 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8697 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8698 /* => */ RTUINT256_INIT_C(0x3dbabb5812c66528, 0xf2b81dd880e4ac66, 0x1000d2b67f32c586, 0x87a69b40470833fa) }, /* sll 1-by-16 */ 8699 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 8700 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8701 /* => */ RTUINT256_INIT_C(0xb7406b0058c0a500, 0x5700bb001c808cc0, 0x000056c0e640b0c0, 0xf4c06800e1007f40) }, /* sll 6-by-16 */ 8702 }; 8703 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_01[] = 8704 { 8705 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8706 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8707 /* => */ RTUINT256_INIT_C(0x3dbabb5812c66528, 0xf2b81dd880e4ac66, 0x1000d2b67f32c586, 0x87a69b40470833fa) }, /* sll 1-by-16 */ 8708 }; 8709 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_12[] = 8710 { 8711 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8712 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8713 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll 0x12-by-16 */ 8714 }; 8715 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = 8716 { 8717 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 8718 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 8719 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 8720 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 8721 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8722 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-32 */ 8723 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8724 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8725 /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b67f32c586, 0x87a79b40470933fa) }, /* sll 1-by-32 */ 8726 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 8727 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8728 /* => */ RTUINT256_INIT_C(0xb7776b0058cca500, 0x5723bb001c958cc0, 0x003a56c0e658b0c0, 0xf4f36800e1267f40) }, /* sll 6-by-32 */ 8729 }; 8730 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_01[] = 8731 { 8732 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8733 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8734 /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b67f32c586, 0x87a79b40470933fa) }, /* sll 1-by-32 */ 8735 }; 8736 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_12[] = 8737 { 8738 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8739 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8740 /* => */ RTUINT256_INIT_C(0x76b00000ca500000, 0x3bb0000058cc0000, 0xa56c00008b0c0000, 0x3680000067f40000) }, /* sll 0x12-by-32 */ 8741 }; 8742 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = 8743 { 8744 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 8745 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 8746 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 8747 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 8748 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8749 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-64 */ 8750 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8751 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8752 /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b77f32c586, 0x87a79b40470933fa) }, /* sll 1-by-64 */ 8753 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 8754 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8755 /* => */ RTUINT256_INIT_C(0xb7776b0258cca500, 0x5723bb101c958cc0, 0x003a56efe658b0c0, 0xf4f36808e1267f40) }, /* sll 6-by-64 */ 8756 }; 8757 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_01[] = 8758 { 8759 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8760 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8761 /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b77f32c586, 0x87a79b40470933fa) }, /* sll 1-by-64 */ 8762 }; 8763 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_12[] = 8764 { 8765 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 8766 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8767 /* => */ RTUINT256_INIT_C(0x76b0258cca500000, 0x3bb101c958cc0000, 0xa56efe658b0c0000, 0x36808e1267f40000) }, /* sll 0x12-by-64 */ 8768 }; 8769 8770 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 8771 { 8772 { bs3CpuInstr3_psllw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8773 { bs3CpuInstr3_psllw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8774 { bs3CpuInstr3_psllw_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8775 { bs3CpuInstr3_psllw_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8776 { bs3CpuInstr3_psllw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8777 { bs3CpuInstr3_psllw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8778 { bs3CpuInstr3_psllw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8779 { bs3CpuInstr3_psllw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8780 { bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8781 { bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8782 { bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8783 { bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8784 { bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8785 { bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8786 { bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8787 { bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8788 8789 { bs3CpuInstr3_pslld_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8790 { bs3CpuInstr3_pslld_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8791 { bs3CpuInstr3_pslld_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8792 { bs3CpuInstr3_pslld_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8793 { bs3CpuInstr3_pslld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8794 { bs3CpuInstr3_pslld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8795 { bs3CpuInstr3_pslld_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8796 { bs3CpuInstr3_pslld_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8797 { bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8798 { bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8799 { bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8800 { bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8801 { bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8802 { bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8803 { bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8804 { bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8805 8806 { bs3CpuInstr3_psllq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8807 { bs3CpuInstr3_psllq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8808 { bs3CpuInstr3_psllq_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8809 { bs3CpuInstr3_psllq_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8810 { bs3CpuInstr3_psllq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8811 { bs3CpuInstr3_psllq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8812 { bs3CpuInstr3_psllq_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8813 { bs3CpuInstr3_psllq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8814 { bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8815 { bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8816 { bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8817 { bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8818 { bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8819 { bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8820 { bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8821 { bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8822 }; 8823 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 8824 { 8825 { bs3CpuInstr3_psllw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8826 { bs3CpuInstr3_psllw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8827 { bs3CpuInstr3_psllw_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8828 { bs3CpuInstr3_psllw_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8829 { bs3CpuInstr3_psllw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8830 { bs3CpuInstr3_psllw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8831 { bs3CpuInstr3_psllw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8832 { bs3CpuInstr3_psllw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8833 { bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8834 { bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8835 { bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8836 { bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8837 { bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8838 { bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8839 { bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8840 { bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8841 8842 { bs3CpuInstr3_pslld_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8843 { bs3CpuInstr3_pslld_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8844 { bs3CpuInstr3_pslld_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8845 { bs3CpuInstr3_pslld_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8846 { bs3CpuInstr3_pslld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8847 { bs3CpuInstr3_pslld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8848 { bs3CpuInstr3_pslld_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8849 { bs3CpuInstr3_pslld_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8850 { bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8851 { bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8852 { bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8853 { bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8854 { bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8855 { bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8856 { bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8857 { bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8858 8859 { bs3CpuInstr3_psllq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8860 { bs3CpuInstr3_psllq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8861 { bs3CpuInstr3_psllq_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8862 { bs3CpuInstr3_psllq_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8863 { bs3CpuInstr3_psllq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8864 { bs3CpuInstr3_psllq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8865 { bs3CpuInstr3_psllq_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8866 { bs3CpuInstr3_psllq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8867 { bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8868 { bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8869 { bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8870 { bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8871 { bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8872 { bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8873 { bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8874 { bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8875 }; 8876 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 8877 { 8878 { bs3CpuInstr3_psllw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8879 { bs3CpuInstr3_psllw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8880 { bs3CpuInstr3_psllw_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8881 { bs3CpuInstr3_psllw_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8882 { bs3CpuInstr3_psllw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8883 { bs3CpuInstr3_psllw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8884 { bs3CpuInstr3_psllw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8885 { bs3CpuInstr3_psllw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8886 { bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8887 { bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8888 { bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8889 { bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8890 { bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8891 { bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 8892 { bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 8893 { bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 8894 8895 { bs3CpuInstr3_pslld_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8896 { bs3CpuInstr3_pslld_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8897 { bs3CpuInstr3_pslld_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8898 { bs3CpuInstr3_pslld_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8899 { bs3CpuInstr3_pslld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8900 { bs3CpuInstr3_pslld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8901 { bs3CpuInstr3_pslld_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8902 { bs3CpuInstr3_pslld_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8903 { bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8904 { bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8905 { bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8906 { bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8907 { bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8908 { bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 8909 { bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 8910 { bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 8911 8912 { bs3CpuInstr3_psllq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8913 { bs3CpuInstr3_psllq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8914 { bs3CpuInstr3_psllq_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8915 { bs3CpuInstr3_psllq_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8916 { bs3CpuInstr3_psllq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8917 { bs3CpuInstr3_psllq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8918 { bs3CpuInstr3_psllq_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8919 { bs3CpuInstr3_psllq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8920 { bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8921 { bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8922 { bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8923 { bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8924 { bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8925 { bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 8926 { bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 8927 { bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 8928 }; 8929 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 8930 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 8931 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 8932 g_aXcptConfig4psll, RT_ELEMENTS(g_aXcptConfig4psll)); 8933 } 8934 8935 8936 /* 8937 * [V]PSRAW/[V]PSRAD - Shift packed data right arithmetic (PSRAQ doesn't exist until AVX512) 8938 */ 8939 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_MM1_MM2_icebp); 8940 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_MM1_FSxBX_icebp); 8941 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_MM1_001h_icebp); 8942 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_MM1_012h_icebp); 8943 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_XMM1_XMM2_icebp); 8944 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_XMM1_FSxBX_icebp); 8945 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_XMM1_001h_icebp); 8946 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psraw_XMM1_012h_icebp); 8947 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp); 8948 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp); 8949 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp); 8950 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp); 8951 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp); 8952 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp); 8953 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp); 8954 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp); 8955 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM8_XMM9_XMM10_icebp); 8956 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM8_XMM9_FSxBX_icebp); 8957 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM8_XMM9_001h_icebp); 8958 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_XMM8_XMM9_012h_icebp); 8959 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM8_YMM9_XMM10_icebp); 8960 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM8_YMM9_FSxBX_icebp); 8961 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM8_YMM9_001h_icebp); 8962 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsraw_YMM8_YMM9_012h_icebp); 8963 8964 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_MM1_MM2_icebp); 8965 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_MM1_FSxBX_icebp); 8966 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_MM1_001h_icebp); 8967 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_MM1_012h_icebp); 8968 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_XMM1_XMM2_icebp); 8969 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_XMM1_FSxBX_icebp); 8970 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_XMM1_001h_icebp); 8971 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrad_XMM1_012h_icebp); 8972 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp); 8973 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp); 8974 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp); 8975 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp); 8976 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp); 8977 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp); 8978 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp); 8979 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp); 8980 extern FNBS3FAR bs3CpuInstr3_vpsrad_XMM8_XMM9_XMM10_icebp_c64; 8981 extern FNBS3FAR bs3CpuInstr3_vpsrad_XMM8_XMM9_FSxBX_icebp_c64; 8982 extern FNBS3FAR bs3CpuInstr3_vpsrad_XMM8_XMM9_001h_icebp_c64; 8983 extern FNBS3FAR bs3CpuInstr3_vpsrad_XMM8_XMM9_012h_icebp_c64; 8984 extern FNBS3FAR bs3CpuInstr3_vpsrad_YMM8_YMM9_XMM10_icebp_c64; 8985 extern FNBS3FAR bs3CpuInstr3_vpsrad_YMM8_YMM9_FSxBX_icebp_c64; 8986 extern FNBS3FAR bs3CpuInstr3_vpsrad_YMM8_YMM9_001h_icebp_c64; 8987 extern FNBS3FAR bs3CpuInstr3_vpsrad_YMM8_YMM9_012h_icebp_c64; 8988 8989 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psraw_psrad(uint8_t bMode) 8990 { 8991 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = 8992 { 8993 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 8994 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 8995 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 8996 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 8997 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 8998 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sra 0-by-16 */ 8999 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9000 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9001 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1194a, 0xfcaec77620392b19, 0xc400f4addfcc3161, 0x21e9e6d011c2ccfe) }, /* sra 1-by-16 */ 9002 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 9003 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9004 /* => */ RTUINT256_INIT_C(0x007bff76002500ca, 0xffe5fe3b01010158, 0xfe20ffa5fefe018b, 0x010fff36008efe67) }, /* sra 6-by-16 */ 9005 }; 9006 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_01[] = 9007 { 9008 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9009 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9010 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1194a, 0xfcaec77620392b19, 0xc400f4addfcc3161, 0x21e9e6d011c2ccfe) }, /* sra 1-by-16 */ 9011 }; 9012 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_12[] = 9013 { 9014 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9015 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9016 /* => */ RTUINT256_INIT_C(0x0000ffff00000000, 0xffffffff00000000, 0xffffffffffff0000, 0x0000ffff0000ffff) }, /* sra 0x12-by-16 */ 9017 }; 9018 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = 9019 { 9020 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 9021 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 9022 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 9023 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 9024 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9025 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sra 0-by-32 */ 9026 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9027 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9028 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0xfcae477620392b19, 0xc40074addfccb161, 0x21e9e6d011c24cfe) }, /* sra 1-by-32 */ 9029 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 9030 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9031 /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0xffe5723b0101c958, 0xfe2003a5fefe658b, 0x010f4f36008e1267) }, /* sra 6-by-32 */ 9032 }; 9033 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_01[] = 9034 { 9035 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9036 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9037 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0xfcae477620392b19, 0xc40074addfccb161, 0x21e9e6d011c24cfe) }, /* sra 1-by-32 */ 9038 }; 9039 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_12[] = 9040 { 9041 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9042 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9043 /* => */ RTUINT256_INIT_C(0x000007b700000258, 0xfffffe570000101c, 0xffffe200ffffefe6, 0x000010f4000008e1) }, /* sra 0x12-by-32 */ 9044 }; 9045 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 9046 { 9047 { bs3CpuInstr3_psraw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9048 { bs3CpuInstr3_psraw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9049 { bs3CpuInstr3_psraw_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9050 { bs3CpuInstr3_psraw_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9051 { bs3CpuInstr3_psraw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9052 { bs3CpuInstr3_psraw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9053 { bs3CpuInstr3_psraw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9054 { bs3CpuInstr3_psraw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9055 { bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9056 { bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9057 { bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9058 { bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9059 { bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9060 { bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9061 { bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9062 { bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9063 9064 { bs3CpuInstr3_psrad_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9065 { bs3CpuInstr3_psrad_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9066 { bs3CpuInstr3_psrad_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9067 { bs3CpuInstr3_psrad_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9068 { bs3CpuInstr3_psrad_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9069 { bs3CpuInstr3_psrad_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9070 { bs3CpuInstr3_psrad_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9071 { bs3CpuInstr3_psrad_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9072 { bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9073 { bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9074 { bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9075 { bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9076 { bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9077 { bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9078 { bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9079 { bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9080 }; 9081 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 9082 { 9083 { bs3CpuInstr3_psraw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9084 { bs3CpuInstr3_psraw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9085 { bs3CpuInstr3_psraw_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9086 { bs3CpuInstr3_psraw_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9087 { bs3CpuInstr3_psraw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9088 { bs3CpuInstr3_psraw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9089 { bs3CpuInstr3_psraw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9090 { bs3CpuInstr3_psraw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9091 { bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9092 { bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9093 { bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9094 { bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9095 { bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9096 { bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9097 { bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9098 { bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9099 9100 { bs3CpuInstr3_psrad_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9101 { bs3CpuInstr3_psrad_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9102 { bs3CpuInstr3_psrad_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9103 { bs3CpuInstr3_psrad_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9104 { bs3CpuInstr3_psrad_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9105 { bs3CpuInstr3_psrad_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9106 { bs3CpuInstr3_psrad_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9107 { bs3CpuInstr3_psrad_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9108 { bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9109 { bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9110 { bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9111 { bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9112 { bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9113 { bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9114 { bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9115 { bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9116 }; 9117 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 9118 { 9119 { bs3CpuInstr3_psraw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9120 { bs3CpuInstr3_psraw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9121 { bs3CpuInstr3_psraw_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9122 { bs3CpuInstr3_psraw_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9123 { bs3CpuInstr3_psraw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9124 { bs3CpuInstr3_psraw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9125 { bs3CpuInstr3_psraw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9126 { bs3CpuInstr3_psraw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9127 { bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9128 { bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9129 { bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9130 { bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9131 { bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9132 { bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9133 { bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9134 { bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9135 9136 { bs3CpuInstr3_psrad_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9137 { bs3CpuInstr3_psrad_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9138 { bs3CpuInstr3_psrad_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9139 { bs3CpuInstr3_psrad_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9140 { bs3CpuInstr3_psrad_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9141 { bs3CpuInstr3_psrad_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9142 { bs3CpuInstr3_psrad_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9143 { bs3CpuInstr3_psrad_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9144 { bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9145 { bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9146 { bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9147 { bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9148 { bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9149 { bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9150 { bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9151 { bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9152 }; 9153 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 9154 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 9155 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 9156 g_aXcptConfig4psll, RT_ELEMENTS(g_aXcptConfig4psll)); 9157 } 9158 9159 9160 /* 9161 * [V]PSRLW/[V]PSRLD/[V]PSRLQ - Shift packed data right logical 9162 */ 9163 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_MM1_MM2_icebp); 9164 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_MM1_FSxBX_icebp); 9165 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_MM1_001h_icebp); 9166 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_MM1_012h_icebp); 9167 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_XMM1_XMM2_icebp); 9168 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp); 9169 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_XMM1_001h_icebp); 9170 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlw_XMM1_012h_icebp); 9171 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp); 9172 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp); 9173 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp); 9174 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp); 9175 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp); 9176 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp); 9177 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp); 9178 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp); 9179 extern FNBS3FAR bs3CpuInstr3_vpsrlw_XMM8_XMM9_XMM10_icebp_c64; 9180 extern FNBS3FAR bs3CpuInstr3_vpsrlw_XMM8_XMM9_FSxBX_icebp_c64; 9181 extern FNBS3FAR bs3CpuInstr3_vpsrlw_XMM8_XMM9_001h_icebp_c64; 9182 extern FNBS3FAR bs3CpuInstr3_vpsrlw_XMM8_XMM9_012h_icebp_c64; 9183 extern FNBS3FAR bs3CpuInstr3_vpsrlw_YMM8_YMM9_XMM10_icebp_c64; 9184 extern FNBS3FAR bs3CpuInstr3_vpsrlw_YMM8_YMM9_FSxBX_icebp_c64; 9185 extern FNBS3FAR bs3CpuInstr3_vpsrlw_YMM8_YMM9_001h_icebp_c64; 9186 extern FNBS3FAR bs3CpuInstr3_vpsrlw_YMM8_YMM9_012h_icebp_c64; 9187 9188 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_MM1_MM2_icebp); 9189 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_MM1_FSxBX_icebp); 9190 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_MM1_001h_icebp); 9191 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_MM1_012h_icebp); 9192 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_XMM1_XMM2_icebp); 9193 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_XMM1_FSxBX_icebp); 9194 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_XMM1_001h_icebp); 9195 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrld_XMM1_012h_icebp); 9196 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp); 9197 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp); 9198 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp); 9199 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp); 9200 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp); 9201 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp); 9202 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp); 9203 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp); 9204 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM8_XMM9_XMM10_icebp); 9205 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM8_XMM9_FSxBX_icebp); 9206 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM8_XMM9_001h_icebp); 9207 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_XMM8_XMM9_012h_icebp); 9208 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM8_YMM9_XMM10_icebp); 9209 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM8_YMM9_FSxBX_icebp); 9210 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM8_YMM9_001h_icebp); 9211 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrld_YMM8_YMM9_012h_icebp); 9212 9213 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_MM1_MM2_icebp); 9214 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_MM1_FSxBX_icebp); 9215 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_MM1_001h_icebp); 9216 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_MM1_012h_icebp); 9217 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_XMM1_XMM2_icebp); 9218 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp); 9219 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_XMM1_001h_icebp); 9220 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psrlq_XMM1_012h_icebp); 9221 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp); 9222 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp); 9223 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp); 9224 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp); 9225 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp); 9226 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp); 9227 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp); 9228 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp); 9229 extern FNBS3FAR bs3CpuInstr3_vpsrlq_XMM8_XMM9_XMM10_icebp_c64; 9230 extern FNBS3FAR bs3CpuInstr3_vpsrlq_XMM8_XMM9_FSxBX_icebp_c64; 9231 extern FNBS3FAR bs3CpuInstr3_vpsrlq_XMM8_XMM9_001h_icebp_c64; 9232 extern FNBS3FAR bs3CpuInstr3_vpsrlq_XMM8_XMM9_012h_icebp_c64; 9233 extern FNBS3FAR bs3CpuInstr3_vpsrlq_YMM8_YMM9_XMM10_icebp_c64; 9234 extern FNBS3FAR bs3CpuInstr3_vpsrlq_YMM8_YMM9_FSxBX_icebp_c64; 9235 extern FNBS3FAR bs3CpuInstr3_vpsrlq_YMM8_YMM9_001h_icebp_c64; 9236 extern FNBS3FAR bs3CpuInstr3_vpsrlq_YMM8_YMM9_012h_icebp_c64; 9237 9238 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psrlw_psrld_psrlq(uint8_t bMode) 9239 { 9240 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = 9241 { 9242 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 9243 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 9244 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 9245 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 9246 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9247 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-16 */ 9248 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9249 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9250 /* => */ RTUINT256_INIT_C(0x0f6e6ed604b1194a, 0x7cae477620392b19, 0x440074ad5fcc3161, 0x21e966d011c24cfe) }, /* srl 1-by-16 */ 9251 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 9252 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9253 /* => */ RTUINT256_INIT_C(0x007b0376002500ca, 0x03e5023b01010158, 0x022003a502fe018b, 0x010f0336008e0267) }, /* srl 6-by-16 */ 9254 }; 9255 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_01[] = 9256 { 9257 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9258 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9259 /* => */ RTUINT256_INIT_C(0x0f6e6ed604b1194a, 0x7cae477620392b19, 0x440074ad5fcc3161, 0x21e966d011c24cfe) }, /* srl 1-by-16 */ 9260 }; 9261 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_12[] = 9262 { 9263 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9264 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9265 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl 0x12-by-16 */ 9266 }; 9267 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = 9268 { 9269 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 9270 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 9271 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 9272 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 9273 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9274 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-32 */ 9275 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9276 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9277 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074ad5fccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-32 */ 9278 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 9279 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9280 /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0x03e5723b0101c958, 0x022003a502fe658b, 0x010f4f36008e1267) }, /* srl 6-by-32 */ 9281 }; 9282 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_01[] = 9283 { 9284 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9285 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9286 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074ad5fccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-32 */ 9287 }; 9288 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_12[] = 9289 { 9290 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9291 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9292 /* => */ RTUINT256_INIT_C(0x000007b700000258, 0x00003e570000101c, 0x0000220000002fe6, 0x000010f4000008e1) }, /* srl 0x12-by-32 */ 9293 9294 }; 9295 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = 9296 { 9297 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 9298 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 9299 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 9300 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 9301 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9302 /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-64 */ 9303 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9304 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9305 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074addfccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-64 */ 9306 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), 9307 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9308 /* => */ RTUINT256_INIT_C(0x007b7776b0258cca, 0x03e5723bb101c958, 0x022003a56efe658b, 0x010f4f36808e1267) }, /* srl 6-by-64 */ 9309 }; 9310 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_01[] = 9311 { 9312 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9313 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9314 /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074addfccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-64 */ 9315 }; 9316 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_12[] = 9317 { 9318 { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), 9319 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 9320 /* => */ RTUINT256_INIT_C(0x000007b7776b0258, 0x00003e5723bb101c, 0x000022003a56efe6, 0x000010f4f36808e1) }, /* srl 0x12-by-64 */ 9321 }; 9322 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 9323 { 9324 { bs3CpuInstr3_psrlw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9325 { bs3CpuInstr3_psrlw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9326 { bs3CpuInstr3_psrlw_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9327 { bs3CpuInstr3_psrlw_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9328 { bs3CpuInstr3_psrlw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9329 { bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9330 { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9331 { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9332 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9333 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9334 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9335 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9336 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9337 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9338 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9339 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9340 9341 { bs3CpuInstr3_psrld_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9342 { bs3CpuInstr3_psrld_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9343 { bs3CpuInstr3_psrld_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9344 { bs3CpuInstr3_psrld_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9345 { bs3CpuInstr3_psrld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9346 { bs3CpuInstr3_psrld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9347 { bs3CpuInstr3_psrld_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9348 { bs3CpuInstr3_psrld_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9349 { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9350 { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9351 { bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9352 { bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9353 { bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9354 { bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9355 { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9356 { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9357 9358 { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9359 { bs3CpuInstr3_psrlq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9360 { bs3CpuInstr3_psrlq_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9361 { bs3CpuInstr3_psrlq_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9362 { bs3CpuInstr3_psrlq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9363 { bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9364 { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9365 { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9366 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9367 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9368 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9369 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9370 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9371 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9372 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9373 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9374 }; 9375 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 9376 { 9377 { bs3CpuInstr3_psrlw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9378 { bs3CpuInstr3_psrlw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9379 { bs3CpuInstr3_psrlw_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9380 { bs3CpuInstr3_psrlw_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9381 { bs3CpuInstr3_psrlw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9382 { bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9383 { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9384 { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9385 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9386 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9387 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9388 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9389 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9390 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9391 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9392 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9393 9394 { bs3CpuInstr3_psrld_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9395 { bs3CpuInstr3_psrld_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9396 { bs3CpuInstr3_psrld_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9397 { bs3CpuInstr3_psrld_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9398 { bs3CpuInstr3_psrld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9399 { bs3CpuInstr3_psrld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9400 { bs3CpuInstr3_psrld_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9401 { bs3CpuInstr3_psrld_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9402 { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9403 { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9404 { bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9405 { bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9406 { bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9407 { bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9408 { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9409 { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9410 9411 { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9412 { bs3CpuInstr3_psrlq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9413 { bs3CpuInstr3_psrlq_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9414 { bs3CpuInstr3_psrlq_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9415 { bs3CpuInstr3_psrlq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9416 { bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9417 { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9418 { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9419 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9420 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9421 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9422 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9423 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9424 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9425 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9426 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9427 }; 9428 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 9429 { 9430 { bs3CpuInstr3_psrlw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9431 { bs3CpuInstr3_psrlw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9432 { bs3CpuInstr3_psrlw_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9433 { bs3CpuInstr3_psrlw_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9434 { bs3CpuInstr3_psrlw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9435 { bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9436 { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9437 { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9438 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9439 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9440 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9441 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9442 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9443 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9444 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9445 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9446 9447 { bs3CpuInstr3_psrld_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9448 { bs3CpuInstr3_psrld_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9449 { bs3CpuInstr3_psrld_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9450 { bs3CpuInstr3_psrld_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9451 { bs3CpuInstr3_psrld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9452 { bs3CpuInstr3_psrld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9453 { bs3CpuInstr3_psrld_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9454 { bs3CpuInstr3_psrld_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9455 { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9456 { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9457 { bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9458 { bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9459 { bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9460 { bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9461 { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9462 { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9463 9464 { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9465 { bs3CpuInstr3_psrlq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9466 { bs3CpuInstr3_psrlq_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9467 { bs3CpuInstr3_psrlq_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9468 { bs3CpuInstr3_psrlq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9469 { bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9470 { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9471 { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9472 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9473 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9474 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9475 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9476 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9477 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9478 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9479 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9480 }; 9481 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 9482 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 9483 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 9484 g_aXcptConfig4psll, RT_ELEMENTS(g_aXcptConfig4psll)); 8575 9485 } 8576 9486 … … 13911 14821 #endif 13912 14822 #if defined (ALL_TESTS) 14823 { "[v]psllw/[v]pslld/[v]psllq", bs3CpuInstr3_v_psllw_pslld_psllq, 0 }, 14824 { "[v]psraw/[v]psrad", bs3CpuInstr3_v_psraw_psrad, 0 }, 14825 { "[v]psrlw/[v]psrld/[v]psrlq", bs3CpuInstr3_v_psrlw_psrld_psrlq, 0 }, 14826 #endif 14827 #if defined (ALL_TESTS) 13913 14828 { "vperm2i128/vperm2f128", bs3CpuInstr3_vperm2i128_vperm2f128, 0 }, 13914 14829 #endif
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