Changeset 102586 in vbox for trunk/src/VBox/VMM

Timestamp:

Dec 12, 2023 1:30:02 PM (14 months ago)

Author:

vboxsync

Message:

VMM/IEM: Refactored the IEM_MC_SET_RIP_Uxx_AND_FINISH MCs in prep for native translation. [build fix] bugref:10371

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllThrdFuncs.cpp (modified) (3 diffs)
• include/IEMInline.h (modified) (10 diffs)
• include/IEMMc.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp

@@ -242 +242 @@
  *  clears flags. */
 #define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_u16NewIP) \
-    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP))
+    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
 
 /** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets that checks and
  *  clears flags. */
 #define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u16NewIP) \
-    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP))
+    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
 
 /** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code that checks and
  *  clears flags. */
 #define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u16NewIP) \
-    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP))
+    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), 0 /* cbInstr - not used */)
 
 #undef IEM_MC_SET_RIP_U16_AND_FINISH
@@ -268 +268 @@
  *  clears flags. */
 #define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u32NewEIP) \
-    return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP))
+    return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
 
 /** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code that checks
  *  and clears flags. */
 #define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
-    return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP))
+    return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
 
 #undef IEM_MC_SET_RIP_U32_AND_FINISH
@@ -285 +285 @@
  *  and clears flags. */
 #define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
-    return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u32NewEIP))
+    return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u32NewEIP), 0 /* cbInstr - not used */)
 
 #undef IEM_MC_SET_RIP_U64_AND_FINISH

trunk/src/VBox/VMM/include/IEMInline.h

@@ -2773 +2773 @@
 
 
+#ifdef IEM_WITH_CODE_TLB
 
 /**
@@ -2790 +2791 @@
     else
         return iemRaiseGeneralProtectionFault0(pVCpu);
-#ifndef IEM_WITH_CODE_TLB
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
-#endif
     return iemRegFinishNoFlags(pVCpu);
 }
@@ -2814 +2812 @@
     else
         return iemRaiseGeneralProtectionFault0(pVCpu);
-#ifndef IEM_WITH_CODE_TLB
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
-#endif
     return iemRegFinishNoFlags(pVCpu);
 }
@@ -2838 +2833 @@
     else
         return iemRaiseGeneralProtectionFault0(pVCpu);
-#ifndef IEM_WITH_CODE_TLB
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
-#endif
     return iemRegFinishNoFlags(pVCpu);
 }
 
+#endif /* IEM_WITH_CODE_TLB */
 
 /**
@@ -2852 +2845 @@
  * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
  * @param   uNewIp              The new IP value.
- */
-DECLINLINE(VBOXSTRICTRC) iemRegRipJumpU16AndFinishClearingRF(PVMCPUCC pVCpu, uint16_t uNewIp) RT_NOEXCEPT
+ * @param   cbInstr             The instruction length, for flushing in the non-TLB case.
+ */
+DECLINLINE(VBOXSTRICTRC) iemRegRipJumpU16AndFinishClearingRF(PVMCPUCC pVCpu, uint16_t uNewIp, uint8_t cbInstr) RT_NOEXCEPT
 {
     if (RT_LIKELY(   uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit
@@ -2861 +2855 @@
         return iemRaiseGeneralProtectionFault0(pVCpu);
 #ifndef IEM_WITH_CODE_TLB
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#else
+    RT_NOREF_PV(cbInstr);
 #endif
     return iemRegFinishClearingRF(pVCpu);
@@ -2874 +2870 @@
  * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
  * @param   uNewEip             The new EIP value.
- */
-DECLINLINE(VBOXSTRICTRC) iemRegRipJumpU32AndFinishClearingRF(PVMCPUCC pVCpu, uint32_t uNewEip) RT_NOEXCEPT
+ * @param   cbInstr             The instruction length, for flushing in the non-TLB case.
+ */
+DECLINLINE(VBOXSTRICTRC) iemRegRipJumpU32AndFinishClearingRF(PVMCPUCC pVCpu, uint32_t uNewEip, uint8_t cbInstr) RT_NOEXCEPT
 {
     Assert(pVCpu->cpum.GstCtx.rip <= UINT32_MAX);
@@ -2884 +2881 @@
         return iemRaiseGeneralProtectionFault0(pVCpu);
 #ifndef IEM_WITH_CODE_TLB
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#else
+    RT_NOREF_PV(cbInstr);
 #endif
     return iemRegFinishClearingRF(pVCpu);
@@ -2898 +2897 @@
  * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
  * @param   uNewRip             The new RIP value.
- */
-DECLINLINE(VBOXSTRICTRC) iemRegRipJumpU64AndFinishClearingRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT
+ * @param   cbInstr             The instruction length, for flushing in the non-TLB case.
+ */
+DECLINLINE(VBOXSTRICTRC) iemRegRipJumpU64AndFinishClearingRF(PVMCPUCC pVCpu, uint64_t uNewRip, uint8_t cbInstr) RT_NOEXCEPT
 {
     Assert(IEM_IS_64BIT_CODE(pVCpu));
@@ -2907 +2907 @@
         return iemRaiseGeneralProtectionFault0(pVCpu);
 #ifndef IEM_WITH_CODE_TLB
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
+    iemOpcodeFlushLight(pVCpu, cbInstr);
+#else
+    RT_NOREF_PV(cbInstr);
 #endif
     return iemRegFinishClearingRF(pVCpu);

trunk/src/VBox/VMM/include/IEMMc.h

@@ -73 +73 @@
     return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
 /** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
-#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP)       return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP))
+#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) \
+    return iemRegRipJumpU16AndFinishClearingRF((pVCpu), (a_u16NewIP), IEM_GET_INSTR_LEN(pVCpu))
 /** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
-#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP)       return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewIP))
+#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) \
+    return iemRegRipJumpU32AndFinishClearingRF((pVCpu), (a_u32NewIP), IEM_GET_INSTR_LEN(pVCpu))
 /** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
-#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP)       return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u64NewIP))
+#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) \
+    return iemRegRipJumpU64AndFinishClearingRF((pVCpu), (a_u64NewIP), IEM_GET_INSTR_LEN(pVCpu))
 
 #define IEM_MC_RAISE_DIVIDE_ERROR()                     return iemRaiseDivideError(pVCpu)